JP2585709B2 - Synchronous signal recording / playback method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for recording and reproducing digital signals, and more particularly to a method for recording and reproducing synchronous signals.

[Summary of the Invention]

When reproducing digital data recorded by serialization, it is necessary to detect a synchronization pattern and grasp a break in a data string. In addition, word mapping is performed to suppress the DC component of the serialized recording signal.
As the 4 to 5 bit pattern used in a word, a similar pattern is used in each word. That is, if the serialized data is bit-shifted, the same pattern as in the case where the synchronous pattern is serialized in the data is likely to appear. For this reason, there has been a problem that the probability of erroneously dividing the data string increases.

Therefore, the words used in the synchronization pattern are deviated from the bit weight, and include words peculiar to other data patterns. In the entire synchronization pattern, the bit weight approaches 0. The first w is b
Set it 0 more and 2W bit 1 more ... as a solution to the problem. As a result, even if a data string including a synchronization signal is serialized and recorded / reproduced, the synchronization signal portion has a peculiar bit pattern from other data portions because bit 0 and bit 1 are continuous for almost 7 to 8 bits. The probability of false detection is reduced.

[Conventional technology]

The prior art will be described below. Related to this is, for example, JP-A-58-9486 and JP-A-58-9486.
No. 9487 can be mentioned.

In recent years, in order to realize more accurate recording / reproducing, a technology for digitizing a signal and recording / reproducing on a recording medium such as a magnetic tape has been developed. In particular, various technologies have been incorporated in the digitization of video tape recorders that mainly handle video signals.

The video data is usually digitized into 70-ms, 8-bit parallel data per pixel.
It is performed in the form converted to serial data instead of 8 bits.
By the way, in the case of magnetic recording, etc., recording and reproduction of the DC component
Impossible. Therefore, word mapping called 8-9 conversion is performed without serializing the parallel data as it is.
8-bit parallel data can represent 256 kinds of codes, among which are "0000 0000" and "1111 1111". If the data of “0000 0000” is continuous, for example, the data is recorded as a direct current, and accurate data is not restored at the time of reproduction. Therefore, in the 8-9 conversion, since 9-bit parallel data can represent 512 types of codes, "0" or "1" selects only about 4 to 5 codes, and performs 8-bit parallel data. Assign to data. As a result, even if the same value continues in 8-bit parallel data, bit 1 and bit 0
However, since almost the same number is included, generation of a DC component can be suppressed. The sum of bit 1 and bit 0 as +1 and -1 is referred to as bit weight.

After the word mapping as described above, the serialized and recorded serial data sequence is 9bi
After restoring to t parallel data, it is necessary to perform reverse word mapping to return to the original 8-bit parallel data. However, from the serialized data string, which bit is the L
SB can not be determined at all. Therefore, recording is performed by adding a specific data string called a synchronization signal at the beginning of the data in units of an appropriate number of parallel data. As a result, during playback,
First, a serialized synchronization signal is searched for from the serial data group, and then the serial data group is converted into parallel data based on the position of the synchronization signal.

Hereinafter, a conventional synchronization signal detection method will be described. C6, D3, A1 in hexadecimal code as an example of the synchronization signal pattern
Consider the case of three words. This synchronizing signal is converted into the following 9 bits 3 by 8-9 conversion as shown in FIG.
It becomes word data. In FIG. 4, the data obtained by adding each data in the uppermost row to each data in the leftmost column indicated by the hexadecimal code in (a) is converted into data at the intersection point, and the uppermost data of the data is obtained. This indicates that the data at the same position in (b) is added to the bit and converted to 9 bits.

C6, D3, A1 → 13C, 165,0B9 These are serialized and recorded as the following binary data.

If the bit sequence of (1) is shifted left by 1 bit, it can be regarded as the data sequence of (2).

If the same 8-bit data as in (2) is traced back through the 8-9 conversion table in FIG. 4, a code corresponding to each word exists.

079, OCA, 172 → 92,3D, D9 Conversely, if the bit sequence of (1) is shifted right by 1 bit, it is considered to be the data sequence of (3).

The same 8-bit data as (3) also exists as follows.

097,0B2,15C → 96,36, D0 As described above, when the data subjected to the 8-9 conversion for reducing the bit weight is serialized and the synchronization signal is detected, the data string included after the synchronization signal is appropriately converted. It becomes easier to match with bit shifted serial data 27 bits. In other words, in addition to the original synchronizing signal sequence (1), a case where certain words are arranged (eg, 92, 3D, D9, or 96, 36, D0, etc.) is erroneously detected as a synchronizing pattern. .

As a result, since the parallelization process is started from an erroneous segment, the LSB and MSB of the parallelized data are completely scattered.

Erroneous detection of the synchronization pattern, while the data C6, D3, if the A1 that synchronization pattern arranged exactly the same data is also naturally occurring, this probability is _{^{(1/256) 3 = 6}} × 10 -8 .

However, in the above-described example, the number of 1s and 0s in the bits is set to 4 to 5 by the 8-9 conversion so that the bit weight is reduced.

Bit-shift the 8-9 converted data example to 9bi
Even if it is re-divided into t, the number of 1s and 0s in the bits contained therein is likely to be 4-5. Therefore, no matter what bit shift is performed, it corresponds to some word, and therefore, the probability of erroneously detecting the synchronization pattern is high.

[Problems to be Solved by the Invention] As described above, the conventional technique has a disadvantage that a bit string in data is easily erroneously determined as a synchronization pattern. An object of the present invention is to provide a method of recording / reproducing a synchronization signal in which the synchronization pattern is unique and the detection accuracy of the synchronization signal is improved, in order to solve this drawback.

[Means for solving the problem]

In order to achieve the above object of the present invention, the words constituting the synchronization pattern are converted so as to include ones in which the bit weights of each word are offset. However, these words are set so that the bit weight is close to 0 for the entire synchronization pattern.

Specifically, words used for the synchronization patterns C6, D3, and A1 are mapped to 081,165 and OFE.

[Action]

As a result, the synchronization pattern section has the following bit sequence.

In the entire synchronization pattern, 13 bits 0 and 1
The bit weight is +1 and is close to 0. However, the bit weights for each word are -5, +1 and +5, respectively, which is unique to other words. For this reason, 7 bits 0 are set as in 081, and 1 bit as in OFE.
Does not occur from other data parts.

〔Example〕

Hereinafter, words used for the embodiment of the present invention. An example of the mapping is shown in FIG. 3 and described. Note that FIG. 3 also shows that the conversion is performed in the same manner as FIG. 4 as described above. In this embodiment, the synchronization pattern is a word
Before mapping, it was assumed that the word sequence was C6, D3, A1. Therefore, the bit weight in word units is set to 081.165, OFE including the word in which the bit weight is shifted. Of these, 081 and OFE have bit weights of −5 and +5, respectively, and the bit weights of other words are within ± 2, which is significantly different from the others. In this example, since the synchronous pattern has a three-word configuration, the second word D3 is mapped to a code having a bit weight of 165 and +1. As a result, the bit weight of the entire synchronous pattern becomes +1. , DC components are suppressed. Further, in this example, mapping is performed on a word in which the number of bits 0 is large in the first half of the synchronization pattern and the number of bits 1 is large in the second half. Effects can be obtained.

Next, a specific circuit example for realizing this example is shown in FIG.
1 is an input terminal for inputting a word mapping data before, 2 according to the rising of the clock pulse CK ₁ ROM, 3 is applied to output 9 bits data corresponding to the 8-bit binary code applied to the address Te, flip-flop for holding the input (FF), 4 is to serialize the 9-bit data input in the rate of CK _1, the clock pulse CK ₂
Parallel-serial converter for outputting at a rate, 5 is a timing circuit for supplying CK _1, and CK ₂ for determining operation timing of FF3 and parallel-serial converter 4. Frequency ratio of CK ₁ and CK ₂ For 8-9 conversion 1: 9 to become. Reference numeral 6 denotes a recording / reproducing device which records the serial-converted signal on a recording medium, and comprises an electric circuit for reproducing and a drive system for moving the recording medium, and 7 a direct reproducing bit sequence reproduced from the device into an original parallel 9-bit signal. The parallel converter 8 converts the parallel 9-bit signal from the converter into a parallel 8-bit signal before word mapping.
This is an inverse conversion ROM for returning signals.

The contents of ROM2 are shown in FIG. Note that the ROM 8 has the contents of FIG. 3 mapped in reverse. Reference numeral 9 denotes an output terminal for outputting a recorded and reproduced signal.

The synchronization signal portion of the data serialized and recorded on the recording medium via the ROM2 and FF3 is as shown in Expression (4), and 6 to 7 bits 0 and 1 are continuous. When this is reproduced and returned to the original parallel data, the other data is not mapped consecutively with bits 0 and 1 as shown in FIG.
Only the synchronizing signal portion has a very unique bit string as compared with other portions. For this reason, when the serial-parallel converter 7 is reproduced, a portion where the expression (4) is satisfied is detected in the bit string of the reproduced serial data sent from the recording / reproducing device 5, and the position is parallelized to 9 bits based on the position. I do. And
The 9-bit data is input to the address of the ROM 8, and the original 8-bit parallel data is output from the data output terminal 9.

Since the data terminal of the ROM is usually 8 bits,
As shown in Fig. 2, it is necessary to input a common address value, that is, data, to two ROMs A and B, to assign lower 8 bits to ROM A and upper 1 bit to ROM B to obtain 9-bit data. There is.

〔The invention's effect〕

According to the present invention, by changing some characteristics of the means for suppressing the DC component of data, the detection accuracy of the synchronization signal, which is the most important processing at the time of reproduction, is improved. The device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a configuration example of a ROM outputting 9 bits, FIG. 3 is a diagram showing an example of a word map method of the present invention, FIG. The figure shows an example of a conventional word map method. 2 Word map ROM, 4 Parallel converter, 5 Timing circuit, 6 Recording / reproducing device, 7 Serial converter, 8
Reverse word map ROM.

Claims (3)

(57) [Claims] In a recording / reproducing method for recording / reproducing a digital signal serially on a recording medium, a bit weight of an entire synchronous pattern is set to be close to 0, and a bit weight of each word of the synchronous pattern is set. Using a synchronization pattern including a word that is more than twice as deviated from other data words. 2. The recording / reproducing method of a synchronization signal according to claim 1, wherein the bit weight of the entire synchronization pattern is made equal to the bit weight of another data word. 3. The recording / reproducing method of a synchronous signal according to claim 1, wherein the bit weight of the entire synchronous pattern is set to +1 or -1.