JP2584150B2 - High resistance ground fault detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-resistance ground fault detection device for stably detecting a high-resistance ground fault in a distribution line of a multiple grounding or direct grounding type.

[0002] In particular, the high-resistance ground fault detection device of the present invention provides a zero-sequence current (Zero Sequence Curren) generated due to load imbalance in a multiple grounding or direct grounding distribution line.
It is a device that can safely detect a high-resistance ground fault, where any existing protective relay could not be detected because it is difficult to distinguish between t) and current in the event of a high-resistance ground fault.

The high-resistance ground fault detection device of the present invention is embodied as a digital protection relay using a microprocessor other than an existing electromechanical analog device, and is generated when a high-resistance ground fault occurs. After sampling the waveform of the arc current, perform the frequency analysis, and when the ratio of the even harmonic power to the even harmonic power and the odd harmonic power and the change amount of the even harmonic power during the continuous period exceed a certain specified value. Circuit Breaker Systemor Reclosure
sing System).

[0004]

2. Description of the Related Art Generally, a three-phase four-wire power distribution system (a three-phase four-wire power distribution system) is one of power distribution systems for supplying power.
r wire distribution system) and three-phase three-wire system (three ph
ase-three wire) The protective relay method for direct grounding is an overcurrent relay with the function of detecting an accident due to ground fault in the distribution line, and an overcurrent ground relay with the function of detecting an accident due to ground fault in the distribution line. Is used.

[0005] Therefore, when the above-mentioned accident or the like occurs,
The above-mentioned relays not only cut off the power supply to the power line or other power equipment and prevent electric shock accidents or fire accidents, but also eliminate the possibility of spreading the accident to other sound equipment and prevent unnecessary leakage power. Has been used.

More specifically, the above-mentioned overcurrent relay system compares a difference between a fault current caused by a short circuit fault during power supply and a predetermined current set to about 1.5 to 2 times the load current. Then, when the fault current is larger than the setting current, it is determined that a short circuit fault has occurred and the power supply is cut off.

[0007] The ground fault overcurrent relay system is used during power supply.
This method determines a ground fault by sensing the magnitude of the zero-phase current that appears unbalanced when the fault current generated by the ground fault is fed back. In such a three-phase three-wire system or a three-phase four-wire directly-grounded distribution system using a relay system, the power load often fluctuates even during normal times, so the current that appears in each phase Is no longer balanced, and a residual current is generated in the zero-phase or neutral line (N-phase). At this time, the residual current (IN) of the zero-phase or neutral line is expressed by the following equation.

[0008]

IN = IA + IB + IC = 3I ₀ where IA, IB, IC and I ₀ represent the A-phase, B-phase, C-phase and N-phase current, respectively.

At this time, if the magnitude of the normal zero-phase current (IN) is larger than the operation tap (Setting tap-Value) of the overcurrent ground fault relay that operates at the time of a ground fault, malfunction is likely to occur. The operation tap is adjusted upward by an appropriate amount to drive.

[0010]

In such a state, when a high-resistance ground fault occurs on the distribution line, that is, when the distribution line breaks and comes into contact with the ground, a large resistance component is generated by the arc. When it becomes present or comes into contact with a substance with a large resistance component (sand, asphalt, etc.), the fault current is not increased and is maintained at about the load current, so that the relay cannot detect a line fault as described above. , And continuous incomplete power is supplied.

Therefore, the above-mentioned ground fault accident causes unexpected electric shock accidents, fire accidents, equipment accidents, and the like, resulting in an economic loss.

[0012] On the other hand, such a high-resistance ground fault has a short circuit in a power line, and the contact surface of the electric wire is generated due to imperfect grounding of trees, gravel, sand, asphalt, and the like. Even with a protective relay, it was impossible to detect the ground fault.

In recent years, the use of insulated wires has been gradually increasing due to the use of insulated wires in distribution lines. Therefore, when an insulated wire is disconnected and a ground fault occurs, almost all of the wires are incompletely grounded by coating. The fact is that the detection of the above-mentioned high-resistance ground fault has become more difficult, and the incidence of human life and economic loss has increased.

[0014]

OBJECTIVE present invention comprises a digital protective relay apparatus highly resistive ground fault detecting apparatus using the microprocessor of the present invention in which has been made to solve the conventional problems as described above, from the distribution line path even harmonics power amount by using the digital signal after conversion into a digital signal by sampling the phase of the current signal provided, even harmonics power amount for odd harmonics power amount ratio and continuous current waveform Calculate the variation of the power of the even harmonics between the periods and compare the values thus calculated with the values already set to the high resistance ground generated in the distribution line of the multiple grounding and direct grounding systems. An object of the present invention is to provide a stable detection of a collision accident.

[0015]

In order to achieve the above object, the present invention samples an arc current waveform generated at the time of a high-resistance ground fault and converts it into a digital signal, and then performs a frequency analysis of the converted signal. And the arc current waveform 1
Even harmonic components due to asymmetry within the period (even- or
der ha rmonics) (360Hz-1920Hz) is extracted, and if the information related to the even harmonics exceeds a certain specified value, it is determined that there is a high resistance ground fault and a signal for controlling the protective relay is output. The configuration has

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of an apparatus for detecting a high-resistance ground fault according to the present invention. In the present invention, each phase current, which is an analog signal provided from a distribution line, is converted into a digital signal and collected. And a fault signal detecting unit that processes the collected data using a fault detection algorithm and detects that a high-resistance ground fault has occurred in the distribution line.

[0018] The data collection unit described above includes A, B,
Input conversion means (10) for converting C and N-phase currents into voltage signals of an appropriate level, and filtering of each signal provided from the input conversion means (10) to easily obtain necessary even harmonic components. A band-pass filter (20) for outputting only a signal of a predetermined band for detection, an analog multiplexer (30) for sequentially selecting and outputting the above-mentioned band signal for each phase current signal, and an output of the multiplexer A sampling folder (sample) so that a signal of a predetermined level can be output by the output pulse of the timing pulse
and hold circuit), analog-to-digital conversion means (50) for sampling the output of the sampling holder (40) 64 points per period and converting it to a 12-bit digital signal, and this conversion means (40). When the conversion operation of (50) is completed, the conversion end signal output from the conversion means (50) is used to output the DM signal.
DMA for outputting A (Direct memory access) request signal
It comprises a request signal generating means (60), a multiplexer (30), a sampling pulse holder (40), and a timing pulse generator (70) for providing an output pulse to the converting means (50).

The above-mentioned fault signal detecting section is provided with the above-mentioned analog signal.
A buffer (80) for temporarily storing the output of the digital conversion means (50), and a DMA recognition signal is generated by inputting the DMA request signal, and data is directly supplied from the buffer (80) to the storage device. Controller (90) for controlling data transmission as described above, and a storage device (10) for storing output data of the buffer (80), data as a result of arithmetic processing, and a failure detection algorithm.
0) and a central processing unit (11) for controlling various functions of the data collection unit and the accident signal detection unit and executing the failure detection algorithm.
0) and a predetermined data sharing communication so that an operator using an external system and a display keyboard performing the status of the digital relay, the notation function, the input / output function of the data through the keyboard, and the external system can be checked. An input / output means (120) for outputting data through a port or inputting / outputting data through a shared communication port at a remote place.

The operation of the detection device of the present invention having the above structure will be described with reference to FIG. The input conversion means (10) receives the currents Ia, Ib, Ic and In of the A, B, C and N phases on the secondary side of the distribution line and converts them into voltage signals of a predetermined level. (Current transduc
er).

The four-line signal (step 200) provided by the input conversion means (10) is filtered by a band-pass filter (20) having a number of filters corresponding to the number of signals, and the necessary even number is filtered. The harmonic component (360 Hz to 1920 Hz) is converted into a signal of a predetermined band pass for easy detection (step 210).

The four-line band-pass signals and the like are applied to a multiplexer (30) and sequentially selected (step 2).
20). The signal output from the multiplexer (30) is converted to an analog signal through a sampling folder (40).
The digital conversion means (50) is provided.

The sampling folder (40) has a large error when a new analog signal is input to the conversion means (50) during the data conversion operation of the analog-digital conversion means (50) for converting an analog signal into a digital signal. This is a circuit having a function of temporarily holding the output signal of the multiplexer (30) until the analog signal preceding the conversion is completed in order to prevent the occurrence of the above.

The output signal of the sampling folder (40) is converted into a digital signal by analog-digital conversion means (step 230), and the converted digital signal is buffered (80) connected to a data bus or the like.
To store. The conversion means (50) includes an analog-to-digital converter having a function of converting an analog signal into a digital signal, and a digital filter having a function of filtering the converted digital signal to remove noise. digitalfilter)
The above-described analog-digital converter samples an analog current waveform having an even harmonic component at 64 points per cycle and converts it into a digital signal.

The above digital filter is a photocoupler
(photo coupler). On the other hand, the conversion means (5
0), the conversion means (5)
0), the conversion end signal STS is output and provided to the DMA request signal generating means (60). At this time, the DMA request signal generating means (60) outputs the DMA request signal DMAREQ.
And provides it to the DMA controller (90) (step 2).
40).

The DMA controller (90) transmits the signal DM
When AREQ is input, DMA recognition signal DMAA
CK is output and provided to the control terminal OE of the buffer (80). At this time, the temporarily stored data is output from the enabled buffer (80),
The data is stored in the storage device (100) through the bus (step 250). The data stored in the storage device (100) is a digital signal containing even harmonic components from each of the A, B, C, and N phase current signals. The storage device (100) stores data stored in the buffer (80) and data calculated in a data processing process of the central processing unit (110).
mory) and a ROM (read only memory) storing a function control algorithm and a failure detection algorithm of the central processing unit (110) for controlling the operation of all circuits. As described above, the data collection unit performs a function of converting a current, which is an analog signal, into digital data.

Next, the storage device (10
The process of detecting the occurrence of a ground fault from the digital signals sequentially stored in (0) will be described with reference to the flowchart of FIG. Returning to FIG. 1, the DMA controller (9
0) performs the function of controlling data transmission as described above, but directly to the storage device (100) by the buffer (80) without passing through the central processing unit (110) or directly to the external system from the storage device. Is controlled to be transmitted. The fault signal detector analyzes the data stored in the storage device (100) according to a fault detection algorithm executed by the central processing unit (110) to detect a high-resistance ground fault (step 270 in FIG. 2) and outputs a cutoff signal. Is transmitted by a circuit breaker or the like (step 280).

The means for detecting a ground fault includes a fault detection calculation routine which is a fault detection algorithm executed by the central processing unit (110). The fault detection calculation routine which was stored in the ROM of the storage device (100), analyzes the data to calculate the even harmonics power and odd harmonics power, even-for odd harmonics power from this power, etc. preset data the data by calculating the deviation of the even harmonics power amount each calculated for successive periods with calculating the ratio (ratio) of the harmonic power, i.e., as compared to the ground fault detection data This is a means to determine a ground fault.

On the other hand, a process in which the central processing unit (110) calls the data stored at the address designated by the DMA controller (90) and calculates the even harmonic power and the odd harmonic power will be described. Each phase of the current flowing through the distribution line has a frequency of 50Hz or 60 Hz, is converted into a subsequently digital signal is stored in the storage device. The central processing unit (110) sequentially calls the stored The data, divided data corresponding to one period in a half cycle, the starting point of the data corresponding to 1/2 period of the out destination of divided data From the data corresponding to each position corresponding to the subsequent 1/2 cycle, that is, the first 1/2 cycle and the next 1/2 cycle.
The corresponding data time difference 2 cycles exits addition, to obtain even harmonics power and obtain odd harmonics power pull out the data corresponding to 1/2 period after the data corresponding to 1/2 period of the previous .

[0030] In other words, the calculation of such power is as follows expressed in the formula.

(Equation 4)

(Equation 5) Here, i is a sequential number of data sampled at 64 points in one cycle.

In step 270a of FIG. 3, the DMA controller (90) is initialized and the following counter is cleared to "0", and at the same time, the storage device (100) is prepared to call sequentially designated information and the like. . In step 271, information corresponding to one cycle is called from the storage device (100), and the flow advances to step 272. Step 27
After the calculation results example 蓄in a predetermined area of the storage device (100) to calculate the even harmonics power Peven to 2, as described above and odd harmonic power Podd, proceeds to step 273. In step 273, the odd harmonic power Po
ratio of even harmonic power Peven to dd
o, ie

(Equation 6) Is calculated, and the process proceeds to step 274.

The calculated amount of change even harmonics power and the next perimeter of even harmonics power cycle of the previous step 274, and proceeds to step 275a after calculating the amount of change of even harmonics power of successive periods. In step 275a, the even harmonic power is compared with the set value for the even harmonic power of the fault detection. If the even harmonic power is greater than the set value, the process proceeds to step 275a , the counter CNT1 is incremented by one, and the process proceeds to step 276a, where the even harmonic power is smaller than the set value. In this case, the process proceeds directly to step 276a.

In step 276a, step 27
The ratio Pratio of the even harmonic power to the odd harmonic power calculated in step 3 is compared with the set value of the failure detection ratio Pref. Wakashi, Pratio proceeds to if step 276b larger than Pref, then proceed counters CNT2 one increased by the step 277a, the above Prati
If o is smaller than Pref, the process directly proceeds to step 277a. In step 277a, the change amount Pvar of the even harmonic power in the continuous cycle calculated in step 274 is set.
There proceeds to greater if step 277b than the change amount Pvref fault detection, and proceeds to <br/> after step 278 one increment counter CNT3, in the case of this reverse proceeds directly to step 278.

In the above step 278, the counter CN
T4 is increased one step 279 after being stored again
Proceed to The increase of the counter CNT4 by one means that one or more of the counters CNT1 to CNT3 is increased by one and an even harmonic component related to the high-resistance ground fault is detected. means. That is, if the counter CNT4 is initially increased by one, it indicates that the even harmonic component is detected for the first time from the current input signal.

Therefore, the counters CNT1 to CNT
Each time any one of 3K is counted, the counter CNT4 counts up to a count value for a set cycle.
The counter CNT4 is cleared again after a predetermined period of the input current signal has passed, and is counted each time information on an even harmonic component from a new current signal period to a predetermined period is detected. Therefore, the counter CNT4 is incremented by one each time information on an even harmonic component related to the high-resistance ground fault is detected while analyzing information corresponding to one cycle of the current signal. on the other hand,
At step 279, if the data of the counter CNT4 is larger than the predetermined period required for the judgment of the detection of the high-resistance ground fault, the trip routine is performed while proceeding to step 279a. Is smaller than the set value, the process jumps to step 270a.

For example, when the above set value is 30 days, only when the counter CNT4 is 30 or more, step 27 is executed.
Proceed to 9a. The above trip routine (step 27)
In 9a), the contents of the counters CNT1 to CNT4 are analyzed to judge whether or not a fault has been detected for a high-resistance ground fault. That is, in the trip routine, as in the above example, the current signal of 30 cycles is analyzed, the data stored in each of the counters CNT1 to CNT3 is analyzed and compared with the set value determined to be the failure detection. If the stored data is larger than the above set value, the signal for controlling the circuit breaker or recloser is transmitted through the input / output device through the process of judging that the high resistance ground fault has occurred on the distribution line. Conversely, if the data stored in each counter is smaller than the set value, the process jumps to step 270 to detect a high-resistance ground fault.

As described above, the execution of the fault detection algorithm in the central processing unit (110) has been described in the above embodiment. However, in the present invention, in order to increase the performance of the fault detection algorithm, a signal processing processor capable of rapidly processing a multiplicative operation can be added. At this time, the storage device (100) is provided with a central processing unit (11).
0) and the signal processing processor, and the same data is called in the shared storage device so that the same data is processed in real time and the same data is not called at the same time.

In the present invention, the above-mentioned counters CNT1 to CN
T4 may be configured as hardware, but is preferably configured as software that allocates a certain area of the storage device (100) to a buffer so as to perform the function of the counter. That is, the signal processing processor must perform a multiplication operation requiring a large amount of calculation time a plurality of times in the accident detection calculation process, so that such a calculation process can be quickly performed and performed in real time. A ROM for storing a calculation program as a device for performing a multiplicative calculation network, a RAM for storing data for storing data for calculation, and a calculation result for temporarily storing data generated during calculation processing Includes storage RAM.

Signals for controlling the signal processing processor are provided by a central processing unit (110), and data for performing a multiplication operation is stored in a RAM of a storage device (100) in a data storage RAM of the signal processing processor. The data stored and stored in the data storage RAM is processed at high speed by the signal processing processor that executes the multiplication operation program. The result data calculated by the processor is stored in a RAM for storing the calculation results, and the central processing unit (110) stores the data in the RAM for storage.
With the above data provided, the operation for detecting the high-resistance ground fault is performed in real time to detect the occurrence of the ground fault.

As described above, the present invention is not limited to the three-phase four-wire system, but can be applied to the three-phase four-wire system by changing the number of input current signals of the input converter. It will be clear to those engaged in the art.

[0041]

As described above, according to the present invention, the arithmetic processing and data collection in the central processing unit can be performed simultaneously by transmitting the input data directly to the memory by the DMA controller. In addition, high-speed calculations can be performed by using a signal processing processor, so that not only the accident detection operation can be processed in real time, but also the protection line cannot be detected by any conventional protection relay. A resistance ground fault can be detected, and an accident due to a high resistance ground fault in the distribution line can be prevented.

In both cases, not only the detection of a ground fault but also a control signal through an input / output device is transmitted to a circuit breaker or a recloser.
Since the power is output from the system, there is an advantage that a comprehensive protection relay system for accidents and control can be implemented. Further, A, B, C, N provided from the distribution line
Since each phase current is analyzed to determine a high-resistance ground fault, not only can other feeders fail, but also which line of each phase has been accurately grounded be able to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a high-resistance ground fault detection device according to the present invention.

FIG. 2 is a flowchart showing a procedure in which the central processing unit in FIG. 1 controls overall functions.

FIG. 3 is a detailed flowchart of a failure detection calculation routine in FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Input conversion means 20 Band-pass filter 30 Multiplexer 40 Sampling holder 50 A / D conversion means 60 D
MA request signal generating means 70 timing pulse generator 80 buffer 90 DMA controller 100 storage device 110 central processing unit 120 input / output device

Claims (6)

(57) [Claims] 1. One or more distribution lines when an accident occurs
In the high-resistance ground fault detecting device for interrupting power to, to separate the harmonic signal representing the even harmonics of (a) the distribution line
Including bandpass filter means for at least one
Network means for monitoring the current in the three-phase distribution line; (b) an analog for converting the harmonic signal into a digital signal
-Digital conversion means; and (c) even harmonic power and odd harmonic from the digital signal.
Power and calculating the even and odd harmonic powers.
Between the selected parameter and the respective predetermined threshold
Calculating means for determining a change in the value of: (d) responding to the change determined by the calculating means
Counter that accumulates count values up to a predetermined count threshold
And DOO means, responsive to storage of the count value that satisfies (e) said count threshold
And a power interruption means for interrupting electric power to the distribution line . 2. The method according to claim 1, wherein the even harmonic power is a sampling frequency.
[Number 1] in the next number of harmonic determined in accordance with the wave number The odd harmonic power is proportional to Peven obtained by
For harmonics of full order : Is calculated as being proportional to Podd
The high-resistance ground fault detection device according to claim 1. 3. The method of claim 1, wherein one of said selected parameters is
Including the ratio of the even harmonic power to the odd harmonic power.
The high-resistance ground fault detector according to claim 2. 4. The method of claim 1, wherein one of the selected parameters is
3. The high resistance ground according to claim 2, wherein the amplitude is an even harmonic power.
Entanglement detection device. 5. The method of claim 1, wherein one of the selected parameters comprises a
Data point representing one cycle and cycle before distribution line
Increased change between corresponding data points representing
3. The high-resistance ground fault detector according to claim 2. 6. One or more distribution lines when an accident occurs.
In a high-resistance ground fault detector that shuts off power to (a) separating harmonic signals representing even harmonics of the distribution line
Including bandpass filter means for at least one
Network means for monitoring the current in the three-phase distribution line; (b) The harmonic signal is divided into a positive half cycle and a negative half cycle.
Analog-digital conversion to digital signal
Conversion means; (c) Negative half cycle data sampled sequentially
The sum of the positive half cycle data sampled sequentially
Even harmonics from the digital signal by squaring
Even harmonic power calculating means for calculating power, (d) Positive half cycle data sampled sequentially
The difference between the sequentially sampled negative half cycle data
Odd harmonics from the digital signal by squaring
Odd harmonic power calculating means for calculating power; (e) the selected parameters of the odd and even harmonic powers;
The judgment to determine the change between the meter and each predetermined threshold
Setting means, (f) responding to the change determined by the determination means;
Count to accumulate the count value up to the specified count threshold
Means, (g) Respond to accumulation of count values satisfying the count threshold
Power interruption means for interrupting power to the distribution line A high-resistance ground fault detection device characterized by including: