AU643792B2

AU643792B2 - Apparatus for detecting high impedance fault

Info

Publication number: AU643792B2
Application number: AU77382/91A
Authority: AU
Inventors: Myeong-Ho Yoo; Man-Chul Yoon
Original assignee: Korea Electric Power Corp
Current assignee: Korea Electric Power Corp; Korea Midland Power Co Ltd; Korea South East Power Co Ltd; Korea Southern Power Co Ltd; Korea Western Power Co Ltd
Priority date: 1991-04-18
Filing date: 1991-05-29
Publication date: 1993-11-25
Anticipated expiration: 2011-05-29
Also published as: KR920020220A; JP2584150B2; JPH06343224A; KR940010663B1; AU7738291A

Description

COMMONWEALTH OF AUSTRALIA 6 4?#3 792 PATENTS ACT 1952-69 COMPLETE SPECIFICATION

(ORIGINAL)

Class Int. Class Application Number Lodged: Go mplete Specif ication Lodged:

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0O Related Art Published: lame of Applicant Address of Applicant kk*ctual Inventor Address for Service KOREA ELECTPIC POWER CORPORATION 167, Samsung-dong, Gangnam-ku, Seoul 135-791, Korea MAN-CHUL YcflN and MYEONG-HO YOO WATERMARK PATENT TRADEMARK ATTORNEYS.

LOCKED BAG NO. 5, HAWTHORN, VICTORIA 3122, AUSTRALIA Complete Specification for the invention entitled: .APPARATUS FOR DETECTING HIGH IMPEDANCE FAULT The following statement is a full description of this invention, including the best method of performing it known to :-us APPARATUS FOR DETECTING HIGH IMPEDANCE FAULT BACKGROUND OF THE INVENTION The present invention relates to an apparatus for detecting a high impedance fault on distribution lines, and more particularly to an apparatus for distinguishing characteristics between zero-sequence current caused by load unbalance and fault current of a high impedance caused by incompletely fallen conductors on distribution lines in a multi-ground distribution system or a directly grounded distribution system aind supplying a control signal for a reclosing system so as to Scut off flow of load current.

Generallly, there are two power supply systems for providing currents to some load system through distribution lines, one is threephase, four-wire distribution system, the other is three-phase, threewire directly grounded system. A protective relay system utilizing these systems has used an over current relay for detecting ocicrrence of a fault caused by a short of distribution lines, and overcurrent ground Srelay for detecting occurrence of fault caused by fallen conductors on distribution lines. Since these relays can block power supply which is provided to power lines or power equipments, such relay has been commonly used so as to prevent person from occurrence of an electric shock and prevent damage to power equipment.

Such over current relay is provided for cutting off power supply under detection of short fault, in which an amount of fault current caused Ly fallen conductors during supplying power is compared with a set current value as being one and half times or two times of an amount of load current, and a short fault is detected only when an amount of the fault current is greater than said setting current value.

On the other hand, the overcurrent ground relay is provided for detecting a zero-sequence current caused by unbalance of fault current characteristic which is applied from fallen conductors, and thus distinguishing a fallen fault on distribution lines.

In a directly-grounded distribution system utilizing such a relay system, fluctuation of load power often occurs in normal times due to unbalance respective phase of currents in these current waveforms, so that remaining current appears in a zero-sequence line or a neutral Phase line. An amount of the remaining current IN can be obtained from the following relation, IN Ia Ib Ic 310 (1) whereas Ia,Ib,Ic and ID are A-phase, B-phase, C-phase and neutral-phase current signals, respectively. Accordingly, when an amount of a normal zero-sequence current IN is greater than setting value of over current ground relay for detecting fallen 3nductors on distribution lines, there raises maloperation in the relay system. Therefore, the relay system has to operate in excess of the I setting current value so as to prevent from maloperation of the system.

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On the other hand, the detection of faults in distribution lines is commonly done by devices which measure overcurrents caused by faults. Such devices include a reclosing system such as overcurrent relays, overcurrent ground relays, reclosures, or fuses. While these devices interrupt fault currents, they must not trip a normal emergency load currents such as transient overcurrents caused by inrush events or load pick upsurges. Because of t.his, the threshnid of the operation must be set at a relatively high current value to avoid tripping during normal operations. Practically, overcurrent relays in each phase are usually set to operate 125-ZO0% of maximum load. Therefore, overcurrent ground relays are usually set high to allow some large neutral currents due to this unbalance.

Although conventional overcurrent devices do detect many faults in the distribution line these devices still do not detect a large number of faults with very low fault currents in these case the magnitude of fault currents is nearly 0 to 100A These faults are frequently occurred when a fallen distribution conductor is in contact with a high impedance surface such as a asphalt road, macadam, gravel, sand, or tree. The fault currents of these high 6 impedance faults are below the threshold of the operation of the fault clearing device. Moreover, as the occurrences of high impedance faults are more increasing due to the frequent use of electrical insulated wire, an appropriate ground relaying system for readily detecting the fault is more required Such a conventional art is disclosed in "Detection of high impedance faults on multi-grounded primary distribution system" which is invented by J. Carr, IEEE *4 Transactions on Power Apparatus and Systems, Vol. PAS-100, pp. 2008-2016, April 1981.

t* o 4 SUMMARY OF THE INVENTIOn In order to solve said problems of the prior art ground relay system, an object of the present invention is to provide an apparatus for detecting a high impedance fault caused by fallen distribution conductors, in which comprises a digital protection relay device having a means for transducing input currents on distribution lines to digital signals, and a data processing means for computing an even order power and an odd order power, a rate of the even order power to the odd order power and an incremental variance of sequential even order power, comparing these computed values with respective setting values for detection of the fault, and readily detecting the fault when the respective computed values are greater than the respective setting values.

To achieve said object, the present invention is characterized in that an apparatus for detecting a high impedance fault caused by fallen distribution conductors comprises: input signal transducing means for transducing A,B,C and neutral phase current signals on distribution lines to predetermined level of respective voltage signals; filter means for filtering the respective voltage signals from said transducing means and producing only predetermined band of frequency signals so as to readily detect even order harmonics; S multiplexer means for sequentially selecting the respective frequency signals corresponding to all the phase current signals; sample and hold means for sampling 64 points to the output signal of said multiplexer means corresponding to each cycle of said respective current signals,holding temporarily and producing sampled signal; means for converting the sampled signal from said sample and hold means to digital data and producing a conversion end signal when converting operation of the converting means has been completed; -93 signal producing means for producing a direct memory access request signal in response to the conversion end signal; timing pulse generating means for providing timing pulses to the multiplexer means,sample and hold means and converting means, respective ly: S-buffer means for temporarily storing the digil.al diata: DMAfl -BA controller for producing a direct memory access acknowledge signal in response to the request signal and controlling data transmission between the buffer means and a storage device in order that the stored data of the buffer means is stored in the storage device; said storage device for storing the stored data of the buffer means, information as being result of data processing, a high impedance fault detection algorithm and programs for controlling all functions of the apparatus; central processing unit for controlling the functions by performing said programs and producing data necessary for detection of the high impedance fault by performing said algorithm;and said algorithm comprising the steps of: computing an even order power and odd order power by processing the data corresponding to a cycle signal which are stored in the storage device, a.

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S CS

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wherein the §I{f(i)+f(i+31) =o S respective 32 S sampled data computing computing a back-cycle S even order power is obtained from the following relation and the odd order power is obtained from the following relation h,whereas i is sequential number of sampled data corresponding to points of the positive half-cycle, and i+31 is sequential number of corresponding to respective 32 points of negative half-cycle, a rate of the even order power to the odd order power, an incremental variance between an even order power corresponding to and the even order power corresponding to the previous cycle, 8 GlO comparing the even order power with first setting value for detection of the high impedance fault and increasing one in the contents of first counter when the even order power is greater than said first, setting values, comparing the rate of the even order power with second setting value for detection of the high impedance fault and increasing one in the cont.cnts values of second counter when the rate is greater than t.he second setting value, comparing the incremenl.al variance with third setl ing valuie 'or d(l.fect.ior of the fault and increasinrg nnei in I.he coril.nts fl third coun ter when the variar, eis greater than the third setting value, one increasing 4 in the contents of fourth counter only when at least one of said counters is increased in the contents thereof and comparing the crntents of the fourth counter with fourth setting value relating to detection of the high impedance fault,and determining the high impedance fault when the contents of the fourth counter is greater than the fourth setting value and p.oviding a control signal to a reclosing system in order to cut off power supply of the load system, IV f/ufpfo+ /4 means comprising a common communication port,keyboard and display monitor, wherein the control signal and the stored data of the storage device is provided to a peripheral system through the communication port so that operator can check S* the operating condition of the apparatus and all the setting values and the function control signal is provided from the peripheral system through the communication port.

The" present invention will become more apparent from the following embodiment S described with reference to the accompanying drawings and adapted for use as apparatus for detecting a high impedance fault.

BRIEF DESCRIPTION OF THE DRAWINGS PFIG.l is a block diagram showing an apparatus for detecting a high impedance 44 fault according to the present invention; and FIG.2 is a detailed flow chart showing a fault detection routine performed by a central processing unit.

DETAILED DESCRIPTION OF THE PRESENT INVENT] ON FIG.l snows a circuit diagram of an apparatus for detertling a high i mpledance fault in accordance with the present invention. Referring now to FIG.l, the invention is embodied in an apparatus, which has a data acquisition part in which input current signals from distribution lines are transduced to digital data, and a fault detection part in which the acquired digital data are executed by a fault detecting algorithm and provided for detecting a high impedance fault caused by fallen distribution conductors.

An input signal transducing means 10 comprises a plurality of current transducers which are provided to receive three-phase current signals and neutralphase current signal la,Ib,Ic and In from distribution lines and transduce desired 0 level of voltage signals, respectively. The voltage signals are input to a filtering means 20 having band pass filters corresponding to the number of the voltage signals, ard are filtered so as to detect only even order harmonics in the S range of 360 Hz to 1S20 Hz. Output signals from the filtering means 20 are input to a multiplexer means 30 and thus are sequentially selected.

:1 The selected signal of the multiplexer means 30 is applied to a sample and hold means 40 in order to sample 64 points to one cycle. The selected signal contains a crrrent waveform of the even order harmonics. The sample and hold means 40 holds temporarily a sampled signal thereof until completion of a previous signal converting operation in a converting means 50 so as to prevent a converting error caused within the converting means 50 when a back signal of the sampled sequential signals is input to the means 50 before completion of a fore si'gal conversion. In this way, the sequential output signal of the sample and hold means 40 are provided to the means 50 for converting to digital data. In addition, output data of the converting means are stored in a buffer means The convertiing means has an analog-digi Lal cornveri.or for con'ert. ing anal og signals to digital signals and a digital f'iil.er such as a photl coipler for filtering the digital data and to eliminating noise.

On the other hand, as soon as the converting means 50 has completed the converting operation, a conversion end signal STS is provided from the converting means 50 and is applied to a DMA signal producing means 60. A DMA request signal DMAREQ then is provided from the signal producing means 60 and is applied to a DMA controller 90. A DMA acknowledge signal DMAACK then is provided from The DMA controller 90 and is applied to an enable terminal OB of the buffer means 80. On receiving the acknowledge signal, the digital data stored in the buffer means are output and are stored through a data bus in a storage device 100.

The data stored in the storage device 100 are digital data containing even order harmonics corresponding to A,B,C and neutral phase currents, respectively. The DMA term as described above means a direct memory access in computer systems.

The storage device 100 has a random access memory for saving the output data of the buffer means and a resulting data of a central processing unit 110, and a read only memory for saving all programs to control overall functions by means of the S central processing unit and a fault signal detecting algorithm for detecting a high impedance fault caused by fallen distribution conductors.

I S The operation of the central processing unit 110 of FIG.1 will now be described with reference to the flow chart of FIG.2. The flow chart of FIG.2 shows a fault signal detecting algorithm for processing the stored data of the storage device 100 by means of the processing unit and detecting a high impedance fault, due to fallen distribution conductors.

Turning to 'FG.1, the DMA controller 90 as previously described controls data transmission between the storage device 100 and the buffer means, or the storage device and a peripheral system. The fault signal detection part analyzes data of the storage device by means ol the fault signal detecting algorithm performed by the central processing unit 110, detects a fault impedance fault and transmits a trip signal to a reclosing system in order to block power supply of distribution lines.

The fault signal detecting algorithm is a means for analyzing the stored data of the device 100, computing an even order power and an odd order power, a rate of the even order power to the odd order power and an incremental variance between a fore even order power and a back even order power, comparing computed data with setting values necessary for detecting a high impedance fault, and detecting a fault signal caused by fallen distribution conductors.

First, respective phase current signals containing frequency of 60 Hz or 60 Hz are sequentially converted to digital data and thus is stored in the storage device 100. The data corresponding to one cycle of the frequency signal are fetched from the device 100 and are divided into two group of data of two halfcycles. One is data group of the positive half-cycle in one cycle of the input current signals, and the other is data group of the negative half-cycle.

If data corresponding to each sampling point of the positive half-cycle in one S cycle add to data corresponding to each sampling point of the negative half-cycle *p in the one cycle, an even order power can be obtained. On the other hand, if data corresponding to each sampling point of the positive half-cycle subtract from data corresponding to each sampling point of the negative half-cycle, an odd order power also can be obtained. For instance of 601 Hz frequency, the even order power is obtained in case that data existing 8.3 msec difference between the positive half-cycle and negative half-cycle are added each other. 1f the data are subtracted each otiher, the odd order power is obt.ained. expressions comput.ing these powers are as follows, 31 Peven 7X f(i+31)} (2) K=o 3/ Podd 21 (3) whereas Peven is even order power, Podd is odd order power, i. is sequential number of sampled data corresponding to respective 32 points of the positive half-cycle, and i+31 is sequential number of sampled data corresponding to respective 32 points of the negative half-cycle.

FIP.2 illustraves in flow chart form, the fault detecting procedure. In step 270a, initializing of the DMA controller is made to clear following counters and to fetch sequentially data stored in the storage device 100. Next, the data of the device 100 are fetched in step 271 and are provided to the data processing unit 110 and the control proceeds to step 272 to compute an even order power and an odd order power. The even order power and odd order power are computed by the above described expressions and the control proceeds to step 273 to compute rate of the even order power to the odd even order Dower.The rate can be obtained in case that the even order power Peven is divided by the odd order power Podd. Next, on computing the rate the control proceeds to step 274.. In step 274, an incremental variance between two sequential even order power corresponaing to sequential cyce is obtained ,and the control proceeds to step 275a.

In step 275a, it is determined whether the even order power Peven is larger than first setting value necessary for a fault detection on distribution lines. If so, the control proceeds to step 275b to increase one in the contents of first counter CNT1. If an amounL of the even order power is not greaLor than the first setting value. th.i the controi proceeds to step Z7ti to determine if the rate of the even order power to the odd order power is greater than second setting value necessary for the fault detection. If so, the control proceeds to step 276b to increase one in the contents of second counter CNTZ. If not, the control proceeds to step 277a to determine if the incremental variance is greater than third setting value for thi fault detection. In step 277a, if an amount of the incremental variance is Sgreater than third setting value, then the control proceeds to step 277b to increase one in the contents of third counter CNT3. If not, the control proceeds to step 278 to increase one in the contents of fourth counter CNT4.

Next, it is determined in step 279 whether the coi.ents of the fourth counter CNT4 is greater than fourth setting value for the fault detection. If so, then the control proceeds to step 279a to perform a trip routine. On the other hand if not, the control loops back to the beginning of step 270a.

The increment of the fourth counter CNT4 indicates that at least one of the said counters CNT1,CNT2 and CNT3 is actually counted and thus an even order harmonics relating to a high impedance fault caused by fallen conductors on distribution lines is detected. For example, the first increment of the counter CNT4 indicates that the even order harmonics is firstly detected from the input current signals on distribution lines.

g Accordingly, when at least one of the counters CNT1,CNTZ and CNT3 is operated, the fourth counter CNT4 continues to count not later than the fourth setting value. If predetermined cycles of the rPspective input current signa' expire, the counter CNT4 then is cleared. In addition, the counter CNT4 continues to count when every even order harmonic in next predetermined cycles is de.ected. For example, digital data. corresponding 1, the input current signals of one cycle are analyzed and thus information of even order harmonics relating to the high impedance fault are detected, so that the contents ol the counnt.r CN'i' is -12increased.

On the other hand, in step 279a, a control signal from the centra" processing unit 110 performing the fault signal detecting algorithm is provided to a reclosing system in order to cut off power supply of distribution lines.

In order to improve a performing capability of the fault signal algorithm, txe apparatus according to the present invention further comprises a signal processing processor 120 for performing in high speed a plurallity of multiplication. The processor 120 and the processing unit 110 can hold in common the storage device 100 and can fetch in real times the stored data of the device 100.

In addition, the apparatus of the present invention can have a configuration in which the counters CNT1, CNT, CNT3 and CNT4 is hardware, but a configuration in which the counters is software, using predetermined areas of the storage device 100 as four count buffers.

The signal processing processor have a read only memory for storing multiplication of program, and a random access memory for storing data for multiplication and the resulting data of the multiplication. The signal for controlling the processor 120 is provided from the processing 2 0 unit 110, the data for processing in the processor are provided from the random access memory of the storage device 100 and are stored in random access memory controlled by the processor 120. The processor thu can S fetch the data stored in the memory and can multiply in high speed.

The apparatus according to the present invention can *25 readily detect a high impedance fault caused by the incc-pletely fallen S conductors on distribution lines and thus can previously prevent many accidents due to the high impedance fault. In addition, the apparatus can transmit a control signal to a reclosing system in order to block power supply of distribution lines, so that a general protection relay system can be embodied for detecting a high impedance fault and transmitting a control signal to a reclosing system. Moreover, the apparatus can analyze A, B.C and neutral phase currents from distribution lines and can detect a high impedance fault due to the incompletely fallen conductors, and thus the fault can be distinguished from some fault in any feeder. Also, the -13apparatus can readily determine whet-her a certain line of distribution lines is fallen on ground.

While this invention has been particularly shown and described with respect to this preferred em'bodiment, it should be understood by thise skilled in the art that changes may be made in the fozm and detail without departing from the scope and spirit of the invfention.

00-0 000 0 S.

0 '9

Claims

1. An apparatus for detecting high impedance fault on distribut.ion. lines in which- comprises: input signal. transducing means for transducing A.BC anid neutral phase current signals on~ distribution lines to predetermined level of respective voltage signals; filter means for filtering the respective voltage signals from said Itransducing means and producing only predetermiiined band of f'requency signals so as to readi ly Soo del, eci. even order harmonics; mutl 1exni mons for sequenti. Ially selecin rg the respecti ve freinency signal s corresponding 1,0 all t-le phase current. signals, sampl e and ho]ld means fir sampliin~g 64 poinlts to0 the oitpul. gnal ofU said a. 1.mu tipIJU1 111er MaiS correspondinrg to each cycle 0l I sa id respect iVe ciriren t s igriaIs. ho Id] g Lemr-ar., ilyid roducinrg samlded s igolal' meanls for coriveri rg 1thw qairled si gnal 1'roin said( samiplIe anid hioId momas I.o -14- digital data and producing a conversion end signal whei, converting operation of the converting means has been completed; MAK ,isignal producing means for producing a direct memory access request signal in response to the conversion end signal; timing pulse generating means for providing timing pulses to the multiplexer means,sample and hold means and converting means, respectively; buffer means for temporarily storing the digital data; DMAA 4^controller for producing a direct memory access acknowledge signal in response to the request signal and controlling data transmission between the buffer means and a storage device in order that the stored data of the buffer means is stored in the storage device; said storage device for storing the stored data of the buffer means, information as being result of data processing, a high impedance fault detection algorithm and programs for controlling all functions of the apparatus; central processing unit for controlling the functions by performing said programs and producing data necessary for detection of the high impedance fault by performing said algorithm;and said algorithm comprising the steps of: computing an even order power and odd order power by processing the data corresponding to a cycle signal which are stored in the storage device, wherein 3/ the even order power is obtained from the following relation and the odd order power is obtained from the following relation if(i)- <=c F(i+31)},whereas i is sequential number of sampled data corresponding to respective 32 points of the positive half-cycle, and i+31 is sequential number of sampled data corresponding to respective 32 points of negative half-cycle, computing a rate of the even order power to the odd order power, computing an incremental variance between an even orcdr power corresponding to a back-cycle and the even order power correspond ing to the previous cycle, comparing the even order power with first sell.tti value for detection or the 4 1 t high impedance fault and increasing one in the contents of first counter when the even order power is greater than said first setting values, comparing the rate of the even order power with second setting value for detection of the high impedance fault and increasing one in the contents values of second counter when the rate is greater than the second setting value, comparing the incremental variance with third setting value for detection of the fault and inceeasing one in the contents of third counter when the variance is greater than the third setting value, oAe increasing in the contents of fourth counter only when at least one of said counters is increased in the contents thereof and comparing the contents of the fourth counter with. fourth setting value relating to detection of the high impedance fault,and determining the high impedance fault when the contents of the fourth counter is greater than the fourth setting value and providing a control signal to a reclosing system in order to cut off power supply of the load system, means comprising a common communication port,keybra.''d and display monitor, wherein the control signal and the stored data of the storage device is provided ee.0 to a peripheral system through the communication port so that operator can check the operating condition of the apparatus and all the setting values and the function control signal i.s provided frrou the peripheral system through the communication port. DATED this 27th day of May 1991. KOREA ELECTRIC POWER CORPORATION WATERMARK PATENT TRADEMARK ATTORNEYS "THE ATRIUM" 290 BURWOOD ROAD HAWTHORN. VIC. 3122. ABSTRACT An apparatus for detecting differences between zero-sequence current due to load unbalance and fault current due to fallen distribution conductors and making possible to readily check the fault comprises means for converting analog A,B,C and neutral phase current signals to digital data,respectively, and means for 0* computing even order power, rate of the even order to odd order power and CS incremental variance of even order power by analyzing the digital data and •determining the fault when the computed information are compared with respective etting values and is greater than the setting values. a. e ge a 1e -17-