JP2583020B2 - Method for manufacturing conductive wiring of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a conductive wiring of a highly integrated semiconductor device, and more particularly, to a method of forming a conductive wiring on a surface of a semiconductor substrate which is severely bent (Topology) so as to prevent an increase in contact resistance and poor contact. The present invention relates to a method for manufacturing a conductive wiring that can be formed.

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memor)
y), SRAM (Static Random Access Memory) and AS
A typical highly integrated semiconductor device such as an IC (Application Specified Integated Circuit) has a large number of semiconductor elements formed on a semiconductor substrate, and the semiconductor element is connected to an external circuit device or a semiconductor element or the like. A large number of conductive wirings are provided. The semiconductor substrate has a surface having severe bending due to the semiconductor element and the conductive wiring, and the conductive pattern is formed on the surface of the semiconductor substrate having severe bending.

Further, the conventional method of manufacturing a conductive wiring of a semiconductor device uses a flattening step and a photoetching step, or uses only a photoetching step, in order to pattern a conductive material applied on the surface of a semiconductor substrate having a sharp bend. Used. However, in the conventional method for manufacturing a conductive wiring of a semiconductor device using only the photoetching process, an incomplete conductive pattern is formed because the tolerance of the photoetching process is increased according to the step on the surface of the semiconductor substrate. On the other hand, a conventional method for manufacturing a conductive wiring of a semiconductor device including a planarizing step and a photo-etching step forms a conductive pattern that is not in contact with a semiconductor element and a conductive pattern that has a large contact resistance by a planarizing layer having a large thickness.

As a practical example, a conventional method for manufacturing a conductive wiring of a semiconductor device in which a bit line of a DRAM is formed using only the photo-etching process is a method of forming a large number of word lines on a silicon substrate and laminating an insulating film thereon. Forming a bit line contact hole, depositing a conductive layer on the entire structure, and patterning the conductive layer using a bit line mask. The bit line mask formed on the surface of the conductive layer has an uneven thickness due to the bending of the surface of the semiconductor substrate. The non-uniform thickness of the bit line mask increases the tolerance of the mask process. Accordingly, the conventional bit line manufacturing method forms a partially cut bit line pattern.

Further, in the conventional method of manufacturing a conductive wiring of a semiconductor device in which a bit line of a DRAM is formed by using the above-mentioned flattening step and photo-etching step, an insulating layer is formed flat on a semiconductor substrate on which a word line is formed. Forming a bit line contact hole in the insulating layer so that a semiconductor device formed on the semiconductor substrate is partially exposed; depositing a conductive layer on the entire structure of the semiconductor substrate to form a bit line mask; Was used to pattern the conductive layer. Since the bit line mask has a uniform and thin thickness, the conductive pattern is prevented from being cut.

[0006]

However, since the planarized insulating layer has a non-uniform thickness, the conductive pattern does not contact the semiconductor device or has a large contact resistance. Poor contact and large contact resistance of the conductive pattern are incomplete contact holes due to the thickness of the flattened insulating layer, or
This is because a contact hole having a large aspect ratio is formed.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a conductive wiring of a semiconductor device, wherein a conductive wiring can be formed on a surface of a semiconductor substrate having a sharp bend so that a contact failure does not occur and a contact resistance does not increase. It is in.

[0008]

In order to achieve the above object, a method for manufacturing a conductive wiring of a semiconductor device according to the present invention comprises the steps of providing a semiconductor substrate having at least a word line of a semiconductor element and a severely bent surface; Forming an insulating layer with a uniform thickness on the surface of the semiconductor substrate; forming a first conductive material layer by applying a first conductive material on the insulating layer so as to be electrically connected to the semiconductor device; Forming a second insulating layer having a flat surface on the first conductive material layer; and forming the second insulating layer such that the second insulating layer corresponding to a predetermined conductive wiring region is exposed. Forming a wiring photoresist pattern on the layer, etching the exposed portion of the second insulating layer to partially expose the first conductive material layer, and removing the first photoresist pattern And said Forming a second conductive material pattern made of a second conductive material on the exposed first conductive material layer; removing the planarizing second insulating layer and the first conductive material layer using the second conductive material pattern as a mask; And a step of patterning the first conductive material layer.

Another object of the present invention is to provide a semiconductor substrate having a field surface where a field-effect transistor and a word line are formed and having a sharp bend, and forming a first insulating layer on the surface of the semiconductor substrate. Forming a first photosensitive layer pattern for contact on the first insulating layer, removing the first insulating layer and exposing the first photosensitive layer pattern for contact. Forming a contact hole, removing the first photosensitive film pattern for contact, and forming a first contact hole on the contact hole and the first insulating layer so as to be electrically connected to the field effect transistor. A step of applying a conductive material; a step of forming a second insulating layer having a flat surface on the first conductive material layer; As a portion of the second insulating layer is exposed,
Forming a photoresist pattern for a bit line on the first insulating layer for planarization, and etching the exposed portion of the second insulating layer to partially expose the first conductive material layer; Removing the first photosensitive film pattern for the bit line and forming a second conductive pattern made of a second conductive material on the exposed first conductive material layer; and forming the second conductive pattern using the second conductive material pattern as a mask. Insulating layer and first
Removing the conductive material layer and patterning the first conductive material layer.

[0010]

According to the above structure, the method for manufacturing a conductive wiring of a semiconductor device according to the present invention can form a conductive wiring on the surface of a severely bent semiconductor substrate which does not cause contact failure with a semiconductor element and does not increase contact resistance. .

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. As shown in FIG. 1, a conventional DRAM having a number of word lines 10 arranged side by side from the left to the right is illustrated and described. The DRAM
Add an active region 12 arranged to overlap with two word lines 10 and a bit line 14 partially overlapped with the active region 12 and arranged to intersect with the multiple word lines 10. Prepare. The bit line 14 is electrically connected to the active region 12 by a bit line contact 16. Further, the bit line 14 is formed after the active region 12 and the word line 10 are formed as usual. As a preferred embodiment of the method for manufacturing a conductive wiring of a semiconductor device according to the present invention, a process for manufacturing the bit line 14 will be described below.

FIGS. 2 to 8 and FIGS. 9 to 12 are sectional views for explaining stepwise a bit line manufacturing process which is an embodiment of the method for manufacturing a conductive wiring of a semiconductor device according to the present invention. 2 to 8 are cross-sectional views of the DRAM shown in FIG. 1 taken along the line AA '. FIGS. 9 to 12 show the DRAM shown in FIG. It is sectional drawing cut | disconnected along the line of FIG.

FIG. 2 shows a DRAM having a semiconductor substrate 20 on which an element isolation oxide film 22 and word lines 24 are formed. The surface of the semiconductor substrate 20 has unevenness due to the element isolation oxide film 22 and the word lines 24. The device isolation oxide film 22 formed on the surface of the semiconductor substrate 20 divides the active region shown in FIG. In the active region, a source impurity diffusion region 21A and a drain impurity diffusion region 21B are formed. The word line 24 formed on the surface of the semiconductor substrate 20 is formed in a channel region located between the source impurity diffusion region 21A and the drain impurity diffusion region 21B. Further, a gate oxide film 26 is formed on the surface and the side wall of the word line 24 by coating. A first insulating layer 28 having a uniform thickness is applied on the entire structure of the semiconductor substrate 20.

Further, on the first insulating layer 28, FIG.
As shown in FIG. 2, a first photoresist pattern 30 is formed. The first photoresist pattern 30 is used as a bit line contact mask to expose the source impurity diffusion region 21A.

In the first insulating layer 28 partially exposed from the first photosensitive film pattern 30, the first insulating layer 28 in this portion is removed as shown in FIG. Etched so that The contact hole 33 is formed by exposing the surface of the semiconductor substrate 20 in the source impurity diffusion region 21A. The first photoresist pattern 30 is removed after the contact holes 33 are formed as shown in FIG.

Referring to FIGS. 5 and 9, the DRAM includes a first conductive layer 32 and a second insulating layer 34 sequentially stacked on the entire structure of the silicon substrate 20 shown in FIG. Is provided. The first conductive layer 32 is formed by depositing polysilicon and is used for a bit line.
Further, the second insulating layer 34 is made of BPSG (Boro-Phospho-Silicon).
cate Glass) and a planarized surface formed by depositing PSG (Phospho-Silicate Glass).
Separately, the second insulating layer 34 includes BPSG and PSG.
May be formed of any one of the following materials: A second photoresist pattern 36 used as a bit line mask is formed on the planarized second insulating layer 34. The second photoresist pattern 36 is partially etched in a region where the bit line 14 is formed to expose the planarized portion 34A of the second insulating layer 34. Further, the second photosensitive film pattern 36 is formed on the flattened surface of the second insulating layer 34 to have a uniform and thin thickness.

The portion 34A of the second insulating layer 34 exposed by the partial etching of the second photosensitive film pattern 36 is removed by an etching process as shown in FIGS.
A portion 32A of the first conductive layer 32 located in the bit line region in the first conductive layer 32 is exposed.
After the second insulating layer 34 is partially removed, the second photoresist pattern 36 is removed.

A second conductive layer pattern 38 is formed on the exposed first conductive layer 32, as shown in FIGS. The second conductive layer 38 has a higher etching selectivity than polysilicon, which is the first conductive layer 32. Further, the second conductive layer pattern 38 is formed by depositing tungsten on the exposed first conductive layer 32 and the second insulating layer 34 and etching the deposited tungsten until the second insulating layer 34 is completely exposed. It is formed by doing. The etching tolerance of the second insulating layer 34 and the error of the second conductive layer pattern 38 become very small as the thickness of the second photosensitive film pattern 36 becomes thin. Alternatively, the second conductive layer pattern 38 may be formed by selectively growing the exposed surface of the first conductive layer 32 using a CVD method.

8 and 12, the remaining second insulating layer 34 is removed and the first conductive layer 32 is patterned to form between the semiconductor substrate 20 and the second conductive layer pattern 38. The DRAM having the first conductive layer pattern 32A is formed. As shown in FIG. 8, the second insulating layer 34 is completely removed by a blanket etching method. The first conductive layer pattern 32A is formed by etching the first conductive layer 32 exposed by the second conductive layer pattern 38, and is stable in the source impurity diffusion region 21A formed on the surface of the semiconductor substrate 20. Formed in contact with each other. Further, when the first conductive layer 32 is etched, the second conductive layer pattern 38 having a higher etching selectivity than the first conductive layer 32 is hardly etched. As a result, the DRAM has a bit line formed by a lower conductive pattern made of polysilicon and an upper conductive pattern made of tungsten having a higher etching selectivity than the polysilicon. Further, as an embodiment, the manufacturing process of the bit line electrically connected to the source impurity diffusion region 21A has been described, but the drain impurity diffusion region is formed in a similar manner.
A bit line can be formed in 21B.

[0020]

As described above, the present invention relates to a method for manufacturing a conductive wiring of a semiconductor device, in which a first conductive material is formed so as to be connected to a semiconductor element before a planarizing material is applied to the surface of a severely bent semiconductor substrate. It is important to prevent poor contact and increase in contact resistance. Further, in the method for manufacturing a conductive wiring of a semiconductor device according to the present invention, after the flattening step, disconnection of the conductive wiring is prevented by patterning the first conductive material layer along with the second conductive pattern formed by photoetching. Can be. Due to the above advantages and the like, the method for manufacturing a conductive wiring of a semiconductor device according to the present invention can form a conductive wiring on the surface of a semiconductor substrate which is severely bent without causing a contact failure with a semiconductor element and increasing contact resistance.

[Brief description of the drawings]

FIG. 1 is a plan view showing a layout of a DRAM cell which is an object of the present invention.

2 to 8 are drawings for explaining a method of manufacturing a bit line of a DRAM step by step as an embodiment of a method of manufacturing a conductive wiring of a semiconductor device according to the present invention, and FIG. 2 is shown in FIG. FIG. 2 is a cross-sectional view of the semiconductor device in which the DRAM is cut along the line AA ′.

FIG. 3 is a circuit diagram of the DRAM shown in FIG.
FIG. 4 is a cross-sectional view of the semiconductor device taken along line A ′.

FIG. 4 is a cross-sectional view of the semiconductor device taken along the line AA 'of the DRAM shown in FIG. 1;

FIG. 5 is a cross-sectional view of the semiconductor device taken along the line AA 'of the DRAM shown in FIG. 1;

FIG. 6 is a cross-sectional view of the semiconductor device taken along the line AA 'of the DRAM shown in FIG. 1;

FIG. 7 is a cross-sectional view of the semiconductor device taken along the line AA 'of the DRAM shown in FIG. 1;

FIG. 8 is a cross-sectional view of the semiconductor device, taken along the line AA 'in FIG. 1;

FIGS. 9 to 12 show an example of a method of manufacturing a conductive wiring of a semiconductor device, in which the DRAM shown in FIG.
It is sectional drawing cut | disconnected along the B 'line.

FIG. 10 shows the DRAM shown in FIG.
It is sectional drawing cut | disconnected along the B 'line.

FIG. 11 shows the DRAM shown in FIG.
It is sectional drawing cut | disconnected along the B 'line.

FIG. 12 shows the DRAM shown in FIG.
It is sectional drawing cut | disconnected along the B 'line.

[Explanation of symbols]

 10, 24 word line 12 active region 14 bit line 16 bit line contact 20 semiconductor substrate 21A impurity diffusion region for source 21B impurity diffusion region for drain 22 element isolation oxide film 26 gate oxide film 28 first insulating layer 30 first photosensitive film Pattern 32 first conductive layer 34 second insulating layer 36 second photosensitive film pattern 38 second conductive material layer pattern

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Choi ▲ Kyun ▼ Root 136-1 Gami-ri, Gwangalup-eup, Icheon-gun, Gyeonggi-do, Republic of Korea Inside Hyundai Electronics Industry Co., Ltd. (56) References JP-A-3-174766 ( JP, A) JP-A-5-21758 (JP, A) JP-A-6-177130 (JP, A)

Claims (9)

(57) [Claims] 1. A method for manufacturing a semiconductor device in which a large number of semiconductor elements are integrated, a step of providing a semiconductor substrate having at least a surface on which word lines of the semiconductor elements are formed and severely bent; Forming a first insulating layer to have a uniform thickness; and applying a first conductive material on the first insulating layer so as to be electrically connected to the semiconductor device to form a first conductive material layer. Forming a second insulating layer having a flat surface on the first conductive material layer; and forming the second insulating layer on a predetermined conductive wiring region so that a portion of the second insulating layer is exposed. The first for wiring on the insulating layer
Forming a photosensitive film pattern; etching an exposed portion of the second insulating layer to partially expose the first conductive material layer; removing the first photosensitive film pattern for wiring and exposing the exposed portion; Forming a second conductive material pattern made of a second conductive material on the first conductive material layer thus formed; and removing the planarizing second insulating layer and the first conductive material layer using the second conductive material pattern as a mask. And a step of patterning the first conductive material layer. 2. The method according to claim 2, wherein the first conductive layer includes a step of forming a first photosensitive film pattern for contact on the first insulating layer; Forming a contact hole by exposing the contact hole; removing the first photosensitive film pattern for contact; and applying a first conductive material on the contact hole and the first insulating layer. 2. The method according to claim 1, wherein the conductive wiring is formed. 3. The method according to claim 2, wherein the second conductive material pattern is made of a conductive material having a higher etching selectivity than the first conductive material layer. 4. The method according to claim 3, wherein the first conductive layer is formed of polysilicon, and the second conductive material pattern is formed of tungsten. 5. A step of providing a semiconductor substrate having a field surface where a field-effect transistor and a word line are formed and having a severe bending, and a step of forming a first insulating layer with a uniform thickness on the surface of the semiconductor substrate. Forming a first photosensitive film pattern for a contact on the first insulating layer, removing the first insulating layer and forming a contact hole exposed by the first photosensitive film pattern for a contact; Removing the first photosensitive film pattern for contact; and electrically connecting the field-effect transistor to the field-effect transistor.
First contact holes are formed above the contact holes and the first insulating layer.
Applying a conductive material; forming a second insulating layer having a flat surface on the first conductive material layer; exposing a portion of the second insulating layer located in a predetermined conductive wiring region Forming a photoresist pattern for a bit line on the first insulating layer for planarization, and exposing an exposed portion of the second insulating layer to partially expose the first conductive material layer. Removing the first photoresist pattern for the bit line and forming a second conductive pattern made of a second conductive material on the exposed first conductive material layer; and using the second conductive material pattern as a mask. Removing the second insulating layer and the first conductive material layer, and patterning the first conductive material layer. 6. The second conductive material pattern may include the second conductive material pattern.
Forming a second conductive material layer on the insulating layer and the exposed first conductive material layer; and forming the second conductive material layer such that a surface of the second insulating layer is completely exposed.
6. The method as claimed in claim 5, wherein the conductive material layer is formed by an etching process. 7. The method according to claim 7, wherein the second conductive material pattern comprises the first conductive material pattern.
6. The method as claimed in claim 5, wherein the bit line is made of a conductive material having an etching selectivity as compared with the conductive layer. 8. The method as claimed in claim 7, wherein the first conductive layer is formed of polysilicon and the second conductive material pattern is formed of tungsten. 9. The semiconductor memory according to claim 8, wherein the second conductive material pattern is formed by selectively growing tungsten on an exposed portion of the polysilicon layer using a CVD method. Bit line manufacturing method for the device.