JP2582410B2 - Electrostatic chuck substrate - Google Patents

Electrostatic chuck substrate

Info

Publication number
JP2582410B2
JP2582410B2 JP63104843A JP10484388A JP2582410B2 JP 2582410 B2 JP2582410 B2 JP 2582410B2 JP 63104843 A JP63104843 A JP 63104843A JP 10484388 A JP10484388 A JP 10484388A JP 2582410 B2 JP2582410 B2 JP 2582410B2
Authority
JP
Japan
Prior art keywords
positive
conductor
substrate
electrostatic chuck
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63104843A
Other languages
Japanese (ja)
Other versions
JPH01274938A (en
Inventor
俊也 渡部
千秋 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toto Ltd
Original Assignee
Toto Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toto Ltd filed Critical Toto Ltd
Priority to JP63104843A priority Critical patent/JP2582410B2/en
Publication of JPH01274938A publication Critical patent/JPH01274938A/en
Application granted granted Critical
Publication of JP2582410B2 publication Critical patent/JP2582410B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Jigs For Machine Tools (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はシリコンウエハを加工する各種装置用のウエ
ハ固定,平面度矯正の他、ウエハの搬送用の用途に利用
できる静電チャック基板、更に詳しくは静電チャック基
板の電極構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an electrostatic chuck substrate which can be used for wafer transfer in addition to wafer fixing and flatness correction for various apparatuses for processing a silicon wafer, and further, More specifically, the present invention relates to an electrode structure of an electrostatic chuck substrate.

〔従来の技術〕[Conventional technology]

静電チャック基板の電極構造は第12図に示すように平
面形状で櫛歯状を呈する2つの電極群(100)(200)の
各櫛歯状の電極(100′)(200′)が夫々対向するよう
に2つの電極群(100)(200)を平面的に支持基板
(A)上に配設し、夫々の電極群(100)(200)に外部
端子(300)(400)を支持基板(A)側面から連絡した
構造である。
As shown in FIG. 12, the electrode structure of the electrostatic chuck substrate is such that each of the comb-shaped electrodes (100 ') and (200') of two electrode groups (100) and (200) exhibiting a comb shape in a plan view respectively. Two electrode groups (100) and (200) are disposed on the support substrate (A) so as to face each other, and the external terminals (300) and (400) are supported by the respective electrode groups (100) and (200). This is a structure contacted from the side of the substrate (A).

〔従来技術の問題点〕[Problems of the prior art]

各櫛歯状の電極(100′)(200′)が対向する部分
においては均一な電気力線が描かれ静電力が均一化する
ものの、外部端子(300)(400)との連結用として必要
とする周辺部分においては電極(100′)(200′)が
対向していない為、静電力が発生せず、結果として静電
力が均一化された部分が中央部位に限られ、吸着範囲が
狭い問題点がある。
Uniform lines of electric force are drawn where the comb-tooth-shaped electrodes (100 ') and (200') face each other to make the electrostatic force uniform, but it is necessary for connection with external terminals (300) and (400) Since the electrodes (100 ') and (200') do not face each other in the peripheral portion, no electrostatic force is generated. As a result, the portion where the electrostatic force is uniform is limited to the central portion, and the adsorption range is narrow. There is a problem.

〔技術的課題〕[Technical issues]

本発明の技術的課題は、支持基板全面上に均一化され
た静電力を発生させることであり、他の技術的課題は、
支持基板上の所望部位に発現する吸着力を可変可能にす
ることにある。
The technical problem of the present invention is to generate a uniform electrostatic force on the entire surface of a supporting substrate, and other technical problems are as follows.
An object of the present invention is to make it possible to change the attraction force developed at a desired portion on a support substrate.

〔技術的手段〕(Technical means)

上記技術的課題を達成する為に講じた技術的手段は支
持基板上に、縦,横に正,負の電極を交互に点在させ、
該正,負の電極を、支持基板内に充填されるビアホール
導体及びそのビアホール導体相互を接続する架橋用導体
で夫々個別に一体化し、且つ夫々の架橋用導体を外部端
子に連絡させたことであり、他の技術的手段は、架橋用
導体を、支持基板上の所望範囲内ごとに点在する正,負
の電極群別に一体化されたビアホール導体相互間を接続
せしめ且つ各架橋用導体を外部端子に夫々連絡させるこ
とである。
The technical means taken to achieve the above technical problem is to alternately scatter positive and negative electrodes vertically and horizontally on the supporting substrate,
The positive and negative electrodes are individually integrated with a via-hole conductor filled in the support substrate and a bridging conductor connecting the via-hole conductors to each other, and each bridging conductor is connected to an external terminal. Another technical means is to connect a bridging conductor between via hole conductors integrated for each of positive and negative electrode groups scattered within a desired range on a supporting substrate and to connect each bridging conductor. This is to contact the external terminals respectively.

〔作用〕[Action]

本発明の技術的手段による作用は次の通りである。 The operation according to the technical means of the present invention is as follows.

(請求項1) ビアホール導体,架橋用導体を介して支持基板下面か
ら外部端子に連絡しているから、支持基板全面上に縦,
横に正,負の電極を点在させ且つ交互に近接させて配置
できる。
(Claim 1) Since the lower surface of the support substrate is connected to the external terminal via the via-hole conductor and the bridging conductor, the vertical terminal is formed on the entire surface of the support substrate.
Positive and negative electrodes can be arranged side by side and interspersed alternately.

(請求項2) 支持基板の所望範囲内ごとに点在する正,負の電極群
別に一体化されたビアホール導体,架橋用導体を介して
連絡される外部端子別に任意な電圧を印加することによ
って支持基板上の所望部位に生じる静電力を可変させ
る。
(Claim 2) By applying an arbitrary voltage to each of the external terminals connected via the via-hole conductor and the bridging conductor integrated for each of the positive and negative electrode groups scattered within the desired range of the support substrate. The electrostatic force generated at a desired portion on the support substrate is varied.

〔実施例〕〔Example〕

次に、本発明の実施例を図面に基づいて説明する。 Next, an embodiment of the present invention will be described with reference to the drawings.

まず第1図乃至第5図に示す第1実施例について説明
する。
First, a first embodiment shown in FIGS. 1 to 5 will be described.

静電チャック基板は、支持基板(A)と、その支持基
板(A)上に正,負の電極(1)(2)を点在させて構
成された導体層(B)と、支持基板(A)内に充填され
たビアホール導体(3)と、そのビアホール導体(3)
を外部端子に連絡可能に結線した架橋用導体(4)と、
導体層(B)上に積層される絶縁膜(5)とからなって
いる。
The electrostatic chuck substrate includes a support substrate (A), a conductor layer (B) having positive and negative electrodes (1) and (2) interspersed on the support substrate (A), and a support substrate (A). A) Via-hole conductor (3) filled in and via-hole conductor (3)
A bridging conductor (4) that is connected to an external terminal so that
And an insulating film (5) laminated on the conductor layer (B).

支持基板(A)は絶縁材料であるアルミナ,コーディ
エライト,マグネシア,チタニア,フォルステライト等
のセラミックスを用いて所望厚に成形されている。
The support substrate (A) is formed to have a desired thickness using ceramics such as alumina, cordierite, magnesia, titania, and forsterite, which are insulating materials.

正,負の電極(1)(2)はW,PT,Pd,Cu,Ag等のペー
ストを所望の印刷法を用いて支持基板(A)上に、縦,
横に交互に点在させて配列してなり、その電極径を1mmQ
〜数mmQとし、支持基板(A)上のどの位置でも2mm径の
チップを吸着可能にすべく、正電極群,負電極群を夫々
ビアホール導体(3),架橋用導体(4)を介して支持
基板(A)下から外部端子として取出すようになってい
る。
The positive and negative electrodes (1) and (2) are formed by applying a paste of W, PT, Pd, Cu, Ag, etc. on the support substrate (A) using a desired printing method.
The electrode diameter is 1mm Q
And to several mm Q, to permit adsorption of the chips of 2mm diameter at any position on the support substrate (A), the positive electrodes, respectively via hole conductors negative electrode group (3), via a bridge conductor (4) Thus, it is taken out from under the support substrate (A) as an external terminal.

絶縁膜(5)は支持基板(A)と同様のアルミナ,コ
ーディエライト,マグネシア,チタニア,フォルステラ
イト等のセラミックスを用いて前記導体層(B)上に積
層することによって形成されている。
The insulating film (5) is formed by laminating on the conductor layer (B) using the same ceramics as alumina, cordierite, magnesia, titania, and forsterite as the supporting substrate (A).

次に、斬る第1実施例における静電チャック基板の製
造方法について説明すると、所望厚のアルミナグリーン
シート(6)4枚の内、最上層のグリーンシート(6)
(6−1)に表面に施こされる正,負の電極(1)
(2)に連通するビアホール(7)…を穿設すると共
に、2層目のアルミナグリーンシート(6)(6−2)
に上記正,負の電極(1)(2)に連通するビアホール
(7)…を穿設し、3層目のアルミナグリーンシート
(6)(6−3)に上記負の電極(2)に連通するビア
ホール(7)…を穿設する。
Next, a method of manufacturing the electrostatic chuck substrate according to the first embodiment will be described. Out of four alumina green sheets (6) having a desired thickness, the uppermost green sheet (6) is used.
Positive and negative electrodes (1) applied to the surface of (6-1)
Via holes (7) ... communicating with (2) are formed, and a second-layer alumina green sheet (6) (6-2)
Via holes (7) communicating with the positive and negative electrodes (1) and (2) are formed in the alumina green sheets (6) and (6-3) of the third layer. The communicating via holes (7) are formed.

ビアホール(7)…の穿設はパンチングマシンによっ
て行なう。
The via holes (7) are formed by a punching machine.

次に、最上層のグリーンシート(6)(6−1)にス
クリーン印刷法によって正,負の電極(1)(2)を印
刷すると共に、最上層,2層目,3層目のグリーンシート
(6)(6−1),(6)(6−2),(6)(6−
3)内のビアホール(7)…にビアホール導体(3)…
をスクリーン印刷法によって充填することと併行して、
2層目のグリーンシート(6)(6−2)下面に正電極
群に接続されるビアホール導体(3)…を一体化する架
橋用導体(4)を同様にスクリーン印刷法によって施こ
し、3層目のグリーンシート(6)(6−3)下面に負
電極群に接続されるビアホール導体(3)…を一体化す
る架橋用導体(4)を同様にスクリーン印刷法によって
施こす。
Next, positive and negative electrodes (1) and (2) are printed on the uppermost green sheets (6) and (6-1) by screen printing, and the uppermost, second and third green sheets are printed. (6) (6-1), (6) (6-2), (6) (6-
Via-hole conductor (3) in via-hole (7) in 3)
In parallel with filling by screen printing method,
Cross-linking conductors (4) for integrating via-hole conductors (3) to be connected to the positive electrode group are similarly applied to the lower surface of the second layer green sheet (6) (6-2) by screen printing. A cross-linking conductor (4) for integrating via-hole conductors (3) to be connected to the negative electrode group is similarly formed on the lower surface of the green sheet (6) (6-3) of the layer by screen printing.

最下層のグリーンシート(6)(6−4)には前記正
電極群に接続されるビアホール導体(3)…を一体化す
る架橋用導体(4),負電極群に接続されるビアホール
導体(3)…を一体化する架橋用導体(4)夫々の任意
箇所に接続する為の端子取出口(8)を開口している。
The lowermost green sheets (6) and (6-4) have via-hole conductors (4) integrating via-hole conductors (3) connected to the positive electrode group, and via-hole conductors (4) connected to the negative electrode group. 3) A terminal outlet (8) for connecting to an arbitrary position of each of the cross-linking conductors (4) for integrating...

次に、絶縁膜(5)となるグリーンシート(6)表面
に正,負の電極群が印刷されたグリーンシート(6)
(6−1),更にグリーンシート(6)(6−2),
(6)(6−3),(6)(6−4)を夫々第2図に示
すように積層し、焼成することによって製造する。
Next, a green sheet (6) in which positive and negative electrode groups are printed on the surface of the green sheet (6) serving as an insulating film (5)
(6-1), green sheet (6) (6-2),
(6) (6-3) and (6) (6-4) are manufactured by stacking and firing, respectively, as shown in FIG.

ちなみに、外部端子(9)はコバール金属材を用い、
銀ろう付によって端子取出口(8)に固着して、架橋用
導体(4),ビアホール導体(3)を介して間接的に
正,負電極群と結線することとする。
By the way, the external terminal (9) uses Kovar metal material,
It is fixed to the terminal outlet (8) by silver brazing and indirectly connected to the positive and negative electrode groups via the bridging conductor (4) and the via-hole conductor (3).

尚、2層目のグリーンシート(6)(6−2)の下面
に印刷される架橋用導体(4)と、最下層の外部端子
(9)との連絡は、その架橋用導体(4)と外部端子
(6)とを連絡するように3層目のグリーンシート
(6)(6−3)に充填された結線用ビアホール導体
(3′)で行なう。
The connection between the bridging conductor (4) printed on the lower surface of the second green sheet (6) and (6-2) and the lowermost external terminal (9) is made by the bridging conductor (4). The connection is made with the connection via-hole conductor (3 ') filled in the third-layer green sheets (6) and (6-3) so as to communicate with the external terminals (6).

而して、斯る第1実施例における静電チャック基板
は、外部端子(9)(9)を介して電圧を印加すると、
支持基板(A)全面上において交互に点在する正,負の
電極(1)(2)間に電気力線が均一に発生し、どの部
位においても一定した吸着力を働かせることができる。
Thus, when a voltage is applied through the external terminals (9) and (9) to the electrostatic chuck substrate in the first embodiment,
Lines of electric force are generated uniformly between the positive and negative electrodes (1) and (2) alternately scattered on the entire surface of the support substrate (A), and a constant suction force can be exerted at any part.

次に、第6図乃至第11図に示す第2実施例の静電チャ
ック基板について説明すると、この実施例は支持基板
(A)上の所望範囲に点在する正,負の電極(1)
(2)と、その範囲外に点在する正,負の電極(1)
(2)とに連絡する外部端子(9)(9),(9)
(9)を夫々個別に取出して任意の電圧を印加可能にす
ることによって所望部位と、それ以外の部位とに生じる
吸着力を変化制御可能にしたものである。
Next, the electrostatic chuck substrate of the second embodiment shown in FIGS. 6 to 11 will be described. In this embodiment, the positive and negative electrodes (1) scattered in a desired range on the support substrate (A) are described.
(2) and positive and negative electrodes scattered outside the range (1)
External terminal (9) to communicate with (2) (9), (9)
(9) is individually taken out, and an arbitrary voltage can be applied, thereby making it possible to change and control the attraction force generated between a desired portion and other portions.

この実施例は第6図に示すように中央部(a′)(薄
墨部分)と、周辺部分(a″)とに夫々個別な電圧を印
加できるようにしたものである。
In this embodiment, as shown in FIG. 6, individual voltages can be applied to a central portion (a ') (light black portion) and a peripheral portion (a ").

この実施例の場合には、下記に詳述するグリーンシー
ト(6)(6−1)(6−2)(6−3)(6−4)
(6−5)(6−6)を用いる。
In the case of this embodiment, green sheets (6) (6-1) (6-2) (6-3) (6-4) described in detail below
(6-5) Use (6-6).

最上層のグリーンシート(6)(6−1)(第6図) 表面に正,負の電極(1)(2)を設け且つ内部にそ
の正,負の電極(1)(2)に接続するビアホール導体
(図示せず)を充填している。
The uppermost green sheet (6) (6-1) (FIG. 6) The positive and negative electrodes (1) and (2) are provided on the surface and connected to the positive and negative electrodes (1) and (2) inside. Via hole conductor (not shown).

2層目のグリーンシート(6)(6−2)(第7図) 正,負の電極(1)(2)に接続するビアホール導体
(3)を内部に充填し、下面に中央部(a′)(薄墨部
分)内の負電極に接続したビアホール導体(3)…を一
体化する架橋用導体(4)を印刷している。
Second-layer green sheet (6) (6-2) (FIG. 7) Via-hole conductor (3) connected to positive and negative electrodes (1) and (2) is filled inside, and the lower surface has a central portion (a). ') A cross-linking conductor (4) that integrates the via-hole conductors (3)... Connected to the negative electrode in (light black portion) is printed.

3層目のグリーンシート(6)(6−3)(第8図) 中央部(a′)(薄墨部分)内の正電極群及び周辺部
(a″)内の正,負電極群に接続するビアホール導体
(3)…を内部に充填し、下面に中央部(a′)(薄墨
部)内の正電極群に接続されるビアホール導体(3)…
を一体化する架橋用導体(4)を印刷している。
Third green sheet (6) (6-3) (Fig. 8) Connected to the positive electrode group in the central part (a ') (light black part) and the positive and negative electrode groups in the peripheral part (a ") Via hole conductors (3) to be filled in the inside, and the via hole conductors (3) to be connected to the positive electrode group in the central portion (a ') (light black portion) on the lower surface
Are printed with a cross-linking conductor (4) that integrates them.

4層目のグリーンシート(6)(6−4)(第9図) 周辺部(a″)内の正,負電極群に接続するビアホー
ル導体(3)…を内部に充填し、下面に周辺部(a″)
における正電極群に接続されるビアホール導体(3)…
を一体化する架橋用導体(4)を印刷している。
Fourth-layer green sheet (6) (6-4) (FIG. 9) Via-hole conductors (3) connected to the positive and negative electrode groups in the peripheral portion (a ″) are filled inside, and the lower surface is surrounded by Part (a ")
Via-hole conductors (3) connected to the positive electrode group
Are printed with a cross-linking conductor (4) that integrates them.

5層目のグリーンシート(6)(6−5)(第10図) 周辺部(a″)内の負電極群に接続するビアホール導
体(3)…を内部に充填し、下面に周辺部(a″)内の
負電極群に接続したビアホール導体(3)…を一体化す
る架橋用導体(4)を印刷している。
Fifth layer green sheet (6) (6-5) (FIG. 10) Via-hole conductors (3)... Connected to the negative electrode group in the peripheral portion (a ″) are filled inside, and the lower surface has a peripheral portion ( The bridge conductor (4) for integrating the via-hole conductors (3)... connected to the group of negative electrodes in a ″) is printed.

6層目のグリーンシート(6)(6−6)(第11図) 4個の端子取出口(8)を開口している。Sixth layer green sheet (6) (6-6) (FIG. 11) Four terminal outlets (8) are opened.

ちなみに端子取出口(8)の内1つは、5層目のグリ
ーンシート(6)(6−5)下面に印刷した架橋用導体
(4)に連通状に開口され、他の3つは、2層目,3層
目,4層目のグリーンシート(6)(6−2),(6)
(6−3),(6)(6−4)の各架橋用導体(4)
(4)(4)と接続するように3層目,4層目,5層目のグ
リーンシート(6)(6−3),(6)(6−4),
(6)(6−5)を貫通して充填された結線用ビアホー
ル導体(3′)(3′)(3′)に連通状に開口してい
る。
By the way, one of the terminal outlets (8) is opened to communicate with the bridging conductor (4) printed on the lower surface of the fifth layer green sheet (6) (6-5), and the other three are: Green sheets of the second, third and fourth layers (6) (6-2), (6)
(6-3), (6) Each of the cross-linking conductors (4) of (6-4)
(4) The third, fourth, and fifth green sheets (6) (6-3), (6) (6-4),
(6) The connection via hole conductors (3 ') (3') (3 '), which are filled through the (6-5), are open in communication.

この実施例においても絶縁膜(5)となるグリーンシ
ート(6)と、上記6層からなるグリーンシート(6)
(6−1),(6)(6−2),(6)(6−3),
(6)(6−4),(6)(6−5),(6)(6−
6)を積層し、焼成することによって製造する。
Also in this embodiment, the green sheet (6) serving as the insulating film (5) and the green sheet (6) including the six layers described above.
(6-1), (6) (6-2), (6) (6-3),
(6) (6-4), (6) (6-5), (6) (6-
6) is manufactured by stacking and firing.

尚、(9)は外部端子である。 Note that (9) is an external terminal.

斯る本実施例の静電チャック基板は、中央部(a′)
(薄墨部分)の正電極群,負電極群に接続した外部端子
(9)(9)に高電圧又は低電圧を印加することと併行
して周辺部の正電極群,負電極群に接続した外部端子
(9)(9)に低電力又は高電圧を印加することによっ
て、ウエハの平面度矯正等を効率的に且つ局部的に行な
うことができる。
The electrostatic chuck substrate of this embodiment has a central portion (a ').
At the same time as applying a high voltage or a low voltage to the external terminals (9) and (9) connected to the positive electrode group and the negative electrode group (light black portion), they were connected to the peripheral positive electrode group and the negative electrode group. By applying a low power or a high voltage to the external terminals (9) and (9), the flatness of the wafer can be corrected efficiently and locally.

この第2実施例については、支持基板(A)の中央部
(a′)と、それを除く周辺部(a″)の正,負電極群
に夫々個別な電圧を印加できるように構成したが、これ
はあくまでも一例であり、支持基板(A)を、更に多層
化して支持基板(A)上の正,負電極(1)(2)に対
するビアホール導体(3),架橋用導体(4)の配線系
路を変更すれば更に吸着力分布を細かく分割することも
できる。
The second embodiment is configured such that individual voltages can be applied to the positive and negative electrode groups in the central portion (a ') of the supporting substrate (A) and the peripheral portion (a ") other than the central portion (a'). This is merely an example, and the supporting substrate (A) is further multi-layered to form a via-hole conductor (3) and a bridging conductor (4) for the positive and negative electrodes (1) and (2) on the supporting substrate (A). By changing the wiring system, the suction force distribution can be further finely divided.

〔発明の効果〕〔The invention's effect〕

本発明は以上のように構成したので下記の効果があ
る。
The present invention has the following effects because it is configured as described above.

請求項1の静電チャック基板は、支持基板に、縦,横
に正,負の電極を交互に点在させているので、支持基板
全域に亘って均一な静電力が発生し、均一な吸着力が発
現する領域を、支持基板全域迄拡大できる。
In the electrostatic chuck substrate according to the first aspect of the present invention, positive and negative electrodes are alternately scattered vertically and horizontally on the support substrate, so that a uniform electrostatic force is generated over the entire support substrate and uniform suction is performed. The region where the force appears can be expanded to the entire support substrate.

請求項2の静電チャック基板は、支持基板上に所望範
囲内ごとに点在する正,負の電極群別に一体化されたビ
アホール導体相互間を架橋用導体で接続し、その架橋用
導体を夫々外部端子に連絡しているから、支持基板上の
所望部位と、他の部位内に点在する正,負の電極群別に
印加する電圧を任意設定して、発現する吸着力を各部位
において選定可能であり、ウエハの局部的な平面度矯正
等の用途に有効に利用でき、利用用途,利用範囲を更に
拡張できる。
In the electrostatic chuck substrate according to the second aspect, via-hole conductors integrated for each of positive and negative electrode groups scattered within a desired range on the supporting substrate are connected to each other by a bridging conductor, and the bridging conductor is connected to the via-hole conductor. Since each is connected to the external terminal, the voltage applied to each of the positive and negative electrode groups scattered in the desired portion on the supporting substrate and the other portions is arbitrarily set, and the developed attraction force is applied to each portion. It can be selected and can be effectively used for applications such as local flatness correction of the wafer, and the use application and use range can be further expanded.

依って、所期の目的を達成できる。 Therefore, the intended purpose can be achieved.

【図面の簡単な説明】[Brief description of the drawings]

図面は本発明静電チャック基板の実施例を示し、第1図
乃至第5図は第1実施例の静電チャック基板を示し、第
6図乃至第11図は第2実施例の静電チャック基板を示
し、第1図は平面図、第2図は(2)−(2)断面図、
第3図,第4図,第5図は(3)−(3),(4)−
(4),(5)−(5)断面図、第6図は平面図、第7
図は支持基板をグリーンシート積層法で製造した際の2
層目のグリーンシートの横断平面図、第8図は3層目の
グリーンシートの横断平面図、第9図は4層目のグリー
ンシートの横断平面図、第10図は5層目のグリーンシー
トの横断平面図、第11図は6層目のグリーンシートの横
断平面図、第12図は従来例の静電チャック基板の横断平
面図である。 尚図中 (A):支持基板 (1)(2):正,負の電極 (3):ビアホール導体 (4):架橋用導体 (6):外部端子 (7):ビアホール (9):外部端子
The drawings show an embodiment of the electrostatic chuck substrate of the present invention, FIGS. 1 to 5 show the electrostatic chuck substrate of the first embodiment, and FIGS. 6 to 11 show the electrostatic chuck substrate of the second embodiment. 1 shows a plan view, FIG. 2 shows a cross-sectional view of (2)-(2),
FIGS. 3, 4, and 5 show (3)-(3), (4)-
(4), (5)-(5) sectional view, FIG. 6 is a plan view, FIG.
The figure shows the support substrate manufactured by the green sheet lamination method.
FIG. 8 is a cross-sectional plan view of a third-layer green sheet, FIG. 9 is a cross-sectional plan view of a fourth-layer green sheet, and FIG. 10 is a fifth-layer green sheet. 11 is a cross-sectional plan view of a sixth-layer green sheet, and FIG. 12 is a cross-sectional plan view of a conventional electrostatic chuck substrate. (A): Support substrate (1) (2): Positive and negative electrodes (3): Via-hole conductor (4): Cross-linking conductor (6): External terminal (7): Via-hole (9): External Terminal

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】支持基板上に、縦,横に正,負の電極を交
互に点在させ、該正,負の電極を、支持基板内に充填さ
れるビアホール導体及びそのビアホール導体相互を接続
する架橋用導体で夫々個別に一体化し、且つ夫々の架橋
用導体を外部端子に連絡させたことを特徴とする静電チ
ャック基板。
A positive electrode and a negative electrode are alternately scattered vertically and horizontally on a supporting substrate, and the positive and negative electrodes are connected to a via-hole conductor filled in the supporting substrate and the via-hole conductor. An electrostatic chuck substrate characterized in that the bridging conductors are individually integrated with each other, and each bridging conductor is connected to an external terminal.
【請求項2】架橋用導体が、支持基板上の所望範囲内ご
とに点在する正,負の電極群別に一体化されたビアホー
ル導体相互間を接続せしめており且つ各架橋用導体を外
部端子に夫々連絡させたことを特徴とする請求項第1項
記載の静電チャック基板。
2. A cross-connecting conductor connects via-hole conductors integrated for each of positive and negative electrode groups scattered within a desired range on a support substrate, and each cross-linking conductor is connected to an external terminal. 2. The electrostatic chuck substrate according to claim 1, wherein the electrostatic chuck substrate is contacted with each other.
JP63104843A 1988-04-26 1988-04-26 Electrostatic chuck substrate Expired - Fee Related JP2582410B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63104843A JP2582410B2 (en) 1988-04-26 1988-04-26 Electrostatic chuck substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63104843A JP2582410B2 (en) 1988-04-26 1988-04-26 Electrostatic chuck substrate

Publications (2)

Publication Number Publication Date
JPH01274938A JPH01274938A (en) 1989-11-02
JP2582410B2 true JP2582410B2 (en) 1997-02-19

Family

ID=14391618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63104843A Expired - Fee Related JP2582410B2 (en) 1988-04-26 1988-04-26 Electrostatic chuck substrate

Country Status (1)

Country Link
JP (1) JP2582410B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3699349B2 (en) * 1990-12-25 2005-09-28 日本碍子株式会社 Wafer adsorption heating device
JP3662909B2 (en) * 1990-12-25 2005-06-22 日本碍子株式会社 Wafer adsorption heating device and wafer adsorption device
JPH09237826A (en) * 1996-02-29 1997-09-09 Kyocera Corp Electrostatic chuck
JPH09223729A (en) * 1996-02-19 1997-08-26 Kyocera Corp Electrostatic chuck
US5858099A (en) * 1996-04-09 1999-01-12 Sarnoff Corporation Electrostatic chucks and a particle deposition apparatus therefor
KR101403328B1 (en) * 2007-02-16 2014-06-05 엘아이지에이디피 주식회사 Electro-Static Chuck Having Embossing Electrode Pattern and Method for Processing Substrate Using The Same
JP5283699B2 (en) * 2008-07-08 2013-09-04 株式会社クリエイティブ テクノロジー Bipolar electrostatic chuck
JP5740939B2 (en) * 2010-11-29 2015-07-01 住友電気工業株式会社 Manufacturing method of semiconductor device
KR20180110213A (en) * 2013-08-06 2018-10-08 어플라이드 머티어리얼스, 인코포레이티드 Locally heated multi-zone substrate support

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5764950A (en) * 1980-10-08 1982-04-20 Fujitsu Ltd Electrostatically attracting device and method therefor
JPH0760849B2 (en) * 1986-06-05 1995-06-28 東陶機器株式会社 Electrostatic chuck plate
JPS63299137A (en) * 1987-05-29 1988-12-06 Canon Inc Sample holding device

Also Published As

Publication number Publication date
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