JP2581420B2 - Decoding device in video encoding transmission - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding apparatus for coded video transmission and, more particularly, to a decoding apparatus for decoding coded data in a video transmission which performs one-way transmission using inter-frame coding.

In the coded transmission of a moving image using orthogonal transform, the differential image data between fields or between motion adaptive frames is usually coded by the discrete cosine transform (DCT) method in block units. A first mode for transmitting data and a second mode for transmitting coded data coded for the input image itself are adaptively switched according to a certain rule according to the content of the input image.

However, there is a case where the decoding device cannot perform a decoding operation properly due to a problem on a line such as a data error. In order to return to the normal operation from such a state, a method of returning to the normal operation by forcibly transmitting the image of one frame once in a predetermined cycle in the second mode is adopted. In this case, a method of intermittently transmitting image data of one frame by dividing the image data into a plurality of frames is adopted in order to prevent an unexpected amount of information from occurring.

When this method is adopted, the divided image data transmitted by this method after returning to the normal operation is destroyed by the destroyed data of the previous frame stored when the normal operation cannot be performed due to a problem on the line. It is necessary to prevent

[0005]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional decoding apparatus. In FIG. 1, the decoding device includes a decoding unit 1, an inverse quantization unit 2, an inverse orthogonal transformation unit 3, a selector 4, an addition unit 5, field memories 6 and 7, and an address control unit 8. The decoding unit 1 receives, as an input signal, the encoded data D1 sent from the transmitting device via the transmission path, and restores the original data before encoding. Inverse quantization unit 2
Performs inverse quantization of the image index data D2 decoded by the decoding unit 1 according to the quantization parameter S1 from the decoding unit 1. The inverse orthogonal transform unit 3 performs an inverse orthogonal transform on the image index data dequantized by the dequantization unit 2.

The selector 4 receives, as a select signal, the block type information S3 decoded by the decoding unit 1, thereby receiving one of the three types of data of the previous frame data, the previous field data, and the digital zero data. Selectively output one data. The adding unit 5 adds the output image data of the inverse orthogonal transform unit 3 and the output data of the selector 4 respectively. The field memory 6 includes an adder 5
Are stored for one field. The field memory 7 further stores the output image data of the field memory 6 for one field. Further, the address control unit 8 calculates, from the vector data S2 decoded by the decoding unit 1,
The address for the field memory 7 is controlled.

Next, the operation of the conventional decoding device will be described. The encoded data D1 sent from the transmitting device (not shown) via the transmission path is input to the decoding unit 1. The coded data D1 is usually variable-length coded data composed of image data coded in block units of M lines × N pixels and other header-related data associated therewith. The encoded data D1 is supplied to the decoding unit 1
, Image index data D2, quantization parameter S1, vector data S2, block type information S
3 respectively.

The image index data D2 is input to the inverse quantization unit 2 together with the quantization parameter S1, where it is converted into data before being quantized in accordance with the quantization parameter S1, and then the original data is inverted by the inverse orthogonal transformation unit 3. Converted to image data. This image data is added to the output data of the selector 4 by the adder 5 to form image data, which is then output to a subsequent circuit (not shown) while the field memory 6
And stored for one field. Further, the output image data of the field memory 6 is input to the field memory 7 and accumulated for one field.

As a result, the image data one field before the output image data of the adding unit 5 is fetched from the field memory 6 and the image data one frame before is fetched from the field memory 7. The selector 4 determines whether the block type information S3 from the decoding unit 1 is
Indicates that the output image data is the inter-field difference image data, the output image data of the field memory 6 is selected and output to the adder 5 to indicate that the output image data is the inter-frame difference image data. In this case, the output image data of the field memory 7 whose address has been corrected by the address control unit 8 according to the vector data S2 is selected and output to the adder 5. Thereby, the final image data is output from the adder 5.

In such a one-way video transmission system decoding apparatus, as an error recovery process when an error (data error or the like) occurs on a line (transmission path), one frame is transmitted once every predetermined time. It is conventionally known that the field memories 6 and 7 in the decoding device are updated by forcibly transmitting the image data in the in-field mode on the encoding side (sending side) (for example,
JP-A-63-236489).

This is usually called refreshing, and a commonly used method is to divide one frame into several blocks and divide them into a plurality of frames for transmission. This will be described with reference to FIG. FIG.
As shown in (A) to (D), one screen is divided into four areas A to D.
A case in which the data is divided into two and refreshed once every 30 frames (about 1 second) at equal intervals will be described.

First, in the N-th frame, FIG.
, The image data of the uppermost area A is transmitted in the intra-field mode as indicated by the diagonal lines, and in the (N + 7) th frame, as shown by the diagonal lines in FIG. The image data of the area B is transmitted in the intra-field mode, and the image data of the areas C and D is similarly transferred to the (N + 14) th frame and the (N + 21) th as shown in FIGS. Transmitted in the frame, the N + 3
One frame of image data for refreshing is divided and transmitted within 30 frames, such as transmitting the image data of the area A again in 0 frame.

Here, since the image data for refreshing is used for error recovery, it is not differential image data utilizing inter-frame correlation or inter-field correlation but normal image data.
Therefore, in the conventional decoding device shown in FIG. 3, when the output image data of the inverse orthogonal transform unit 3 is image data for refreshing based on the block type information S3,
The selector 4 selects digital zero data and outputs it to the adder 5, thereby substantially inhibiting the addition operation. As a result, the image data for refresh input to the adder 5 is output from the adder 5 as it is, and updates the field memories 6 and 7.

[0014]

However, in the above-mentioned conventional compounding apparatus, data destroyed at the time of error recovery may be displayed on a monitor. That is, to explain this, at the time when an error occurs, completely unknown data is used as the encoded data D1 in FIG.
Is input and output, the data in the field memories 6 and 7 is destroyed. After that, it is assumed that the process returns and correct coded data D1 is input to the decoding unit 1 and normal processing starts from the Nth frame. Then, as shown in FIG. 4E, in the (N + 1) th frame, it is assumed that the block X at the boundary between the area A and the area B has downward vertical vector information and the block type is between frames. As a result of the address correction by the address control unit 8, the data of the block X is read from the area B according to the size of the vector from the field memory 7.

That is, at this point, the data in the area B stored in the field memory 7 is the data of the Nth frame, and the data in the area B is not refreshed until the N + 7th frame is reached. It remains in the state. The data in the area B of the destroyed Nth frame is read from the field memory 7, added to the data of the block X in the area A by the adder 5 through the selector 4, and then passed through the field memory 6. Is written again as data of the block X in the area A of the (N + 1) th frame. Therefore, the correct data in the area A refreshed in the Nth frame at this time is destroyed in the block X.

In this way, in order to return the data of the block X to the normal state thereafter, the block type remains in the field, or the data in the area A is destroyed until the data in the area A is refreshed again in the (N + 30) th frame. Will be. Therefore, there is a problem that when the decrypted data is viewed on the monitor screen, the destroyed data is visible on the screen.

The present invention has been made in view of the above points,
When returning, the refreshed data part will not be destroyed again by other corrupted data,
It is an object of the present invention to provide a decoding device for video encoding transmission.

[0018]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a first encoding method comprising orthogonally transforming and encoding at least difference image data between frames in block units and data accompanying the data. A decoding unit to which data is input and intermittently input so that second encoded data obtained by dividing data obtained by encoding one frame of the input image itself is input for one frame within a predetermined period; A conversion unit for converting the data extracted and decoded into original image data by inverse quantization and inverse orthogonal transform;
An adder for outputting final image data;
Decoding a memory circuit, and an address control unit that controls the address based-out memory circuits to the vector data retrieved from the decoding unit, the output image data or digitally zero data in the memory circuit to output image data of the previous frame A decoding device comprising a first selector for selecting according to block type information extracted from a decoding unit, inputting the selected data to an addition unit, and adding the output image data to the conversion unit, and including a determination unit and a selection circuit. is there.

Here, the above-mentioned judging section performs the second encoding from the decoding section after error recovery based on the block type information, vector data, position information on the screen and the error recovery timing information extracted from the decoding section. The first coded data input to the decoding unit during a period until data is extracted for one frame is the screen position rewritten by the second coded data, and the second coded data is It is determined whether or not it is specific difference image data to be added to the image data at the screen position that has not been rewritten.

Further, when the specific difference image data input is determined, the selection circuit converts the image data output from the conversion unit to the addition unit into digital zero data, and
The converted image data of the second encoded data one frame before the same screen position as the specific differential image data is input from the memory circuit to the adding unit.

The selection circuit comprises second and third selectors each performing a selection operation based on a judgment output of a judgment unit. The second selector selects one of the output image data of the converter and the digital zero data and outputs the selected data to the adder. A third selector selects one of the vector data and digital zero data from the decoding unit and supplies the selected data to the address control unit.

[0022]

According to the present invention, the first encoded data input to the decoding unit within a period from the recovery of the error by the determination unit to the extraction of the second encoded data from the decoding unit for one frame is represented by: When it is determined that the image data is the specific difference image data to be added to the image data at the screen position rewritten by the second encoded data and not rewritten by the second encoded data, Since the digital zero data is supplied from the conversion unit to the addition unit by the circuit and is added to the output data of the memory circuit, the output data of the memory circuit is directly extracted from the addition unit.

Here, the image data stored in the memory circuit to be added to the specific differential image data is the image position of the screen position not rewritten by the second encoded data before the error recovery. Although the data is destroyed, in the present invention, in this case, the output data of the memory circuit is converted image data of the second encoded data one frame before the same screen position as the specific differential image data,
The destroyed data is not used, and only refreshed correct image data is taken out from the adder circuit and stored again in the memory circuit. Therefore, in the present invention, it is possible to prevent the data refreshed by the second encoded data from being destroyed in the memory circuit by other destroyed data.

[0024]

Next, an embodiment of the present invention will be described.
FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a schematic time chart for explaining the operation of FIG. In FIG. 1, FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, the conventional decoding device includes a decoding unit 10, an inverse quantization unit 2, an inverse orthogonal transformation unit 3, a first selector 4, an addition unit 5, field memories 6 and 7, and an address control unit 8. In this configuration, a determination unit 11, a second selector 12, and a third selector 13 are added to the configuration of FIG.

The decoding unit 10 encodes the coded data D1 sent from the transmitting device via a transmission path (both not shown).
Is received as an input signal, and is restored to the original data before encoding. However, unlike the conventional case, the position information S4 on the screen and the error recovery timing information S5 are also decoded and output. Here, the position information S4 on the screen is the decoding unit 1
0 is the information for identifying that the input coded data D1 of 0 is the lowest block of the area A, B, C or D like the block X in FIG. 4, and the error return timing information S5 is A signal that is active for a period of time from when correct decoding data is output from the decoding unit 10 after restoration to when data for one screen is refreshed (time until input of refresh image data for one frame is completed). It is.

The determining unit 11 determines whether the vector data S2, the block type information S3, the position information S4 on the screen, and the error recovery timing information S5 decoded by the decoding unit 10 satisfy a predetermined condition. A control signal for outputting the previous frame image is output. The second selector 12 selects one of the image data and the digital zero data output from the inverse orthogonal transform unit 3 by the output control signal of the determination unit 11 and outputs the selected data to the addition unit 5. Furthermore,
The third selector 13 switches between the vector data S2 decoded by the decoding unit 10 and the digital zero data according to the control signal output from the determination unit 11, and outputs the switched data to the address control unit 8.

Next, the operation of this embodiment will be described.
The encoded data D1 sent from the transmitting device (not shown) via the transmission path is input to the decoding unit 10, where it is encoded and encoded, the image index data D2, the quantization parameter S1, the vector data S2, Block type information S
3. The information is decoded into position information S4 on the screen and error recovery timing information S5.

The above-mentioned coded data D1 includes first coded data consisting of data obtained by orthogonally transforming and coding difference image data between fields or between frames of a motion adaptive type in units of blocks, and data associated therewith. The data is obtained by dividing the data obtained by encoding the input image of the frame itself and transmitting the data for one frame within a predetermined period.

The image index data D2 is input to the inverse quantization unit 2 together with the quantization parameter S1, where it is converted into data before being quantized in accordance with the quantization parameter S1. It is converted to the original image data shown in FIG. The image data is added to the output data of the selector 4 by the adder 5 through an after-mentioned selector 12 to form image data, which is then output to a subsequent circuit (not shown) and input to the field memory 6. One field is accumulated. Further, the output image data of the field memory 6 is input to the field memory 7 and accumulated for one field.

The vector data S2 (FIG. 2D) extracted from the decoding unit 10 and the block type information S
3 (FIG. 2B), position information S4 on the screen (FIG.
(E)) and error recovery timing information S5 (FIG. 2)
(C)) are input to the determination unit 11, where the second coded data is 1
The first encoded data input to the decoding unit 10 during the period until the frame is extracted is at the screen position rewritten by the second encoded data and rewritten by the second encoded data. It is determined whether or not the image data is specific difference image data to be added to the image data at the screen position that is not present.

That is, as shown in FIGS. 4A to 4D, when one frame of image data for refreshing is divided into four areas A to D and transmitted within 30 frames. When the error recovery is performed in the Nth frame, the error recovery timing information S5 is active during the period from the Nth frame to the (N + 21) th frame. Also,
As shown in FIG. 4 (E), the block X at the boundary between the area A and the area B of the (N + 1) th frame having the downward vertical vector information and having the block type between frames.
Is located at the position of the area A of the N-th frame rewritten by the first encoded data for refreshing, and the image of the area B of the N-th frame not rewritten by the first encoded data. Specific difference image data to be added to the data.

Therefore, when the block X is output from the decoding unit 10 as the image index data D2, the determination unit 11 determines that the input is a specific difference image data input, and the selectors 12 and 13 respectively show the data as shown in FIG. Thus, for example, a low-level control signal is output. As a result, the selector 12 replaces the output image data of the inverse orthogonal
2 (G), the selector 13 outputs digital zero data to the adder 5, and at the same time, the selector 13 selects digital zero data instead of vector data as shown in FIG. Supply.

Thus, according to the address control of the address control unit 8, the data from the field memory 7 is not the data of the area B of the Nth frame, but the area of the Nth frame as schematically shown by h1 in FIG. The refreshed data of the block X portion of A is read and supplied to the adder 5 through the selector 4. Since the digital zero data is input to the adder 5 from the selector 1,
The addition operation is not substantially performed, and the refreshed data of the block X portion of the area A of the N-th frame from the selector 4 is schematically shown by i1 in FIG. 2 (I). Same) is output as it is.

The refreshed data of the block X portion of the area A of the Nth frame extracted by the adder 5 is schematically shown by k1 in FIG. 2 (K).
1) is written again to the field memory 7 through the field memory 6 as data of the (N + 1) th frame. Therefore, according to the present embodiment, the data of the block X in the area A of the refreshed Nth frame is not destroyed by the other destroyed data, and the decoded data is displayed on the monitor screen. If you see
In the block X part of the (N + 1) th frame, the refreshed normal image of the (N) th frame is displayed again without being seen as being greatly broken like a misblock.

When the determination unit 11 determines that the specific difference image data is not input, the selector 12 causes the selector 12 to select the output image data of the inverse orthogonal transform unit 3 and
To select the output vector data S2 of the decoding unit 10,
An operation similar to the conventional operation is performed.

The present invention is not limited to the above embodiment, but can be applied to, for example, a moving picture coded transmission system that does not transmit inter-field difference data.

[0037]

As described above, according to the present invention,
Since the data refreshed by the second encoded data is prevented from being destroyed in the memory circuit by other corrupted data, the corrupted image data is displayed on the monitor screen immediately after the error recovery. Can be prevented from being displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG. 1;

FIG. 3 is a block diagram of an example of the related art.

FIG. 4 is an explanatory diagram of an image in which a refresh operation and data destruction pose a problem.

[Explanation of symbols]

 2 Inverse quantization unit 3 Inverse orthogonal transformation unit 4 First selector 5 Addition unit 6, 7 Field memory 8 Address control unit 10 Decoding unit 11 Judgment unit 12 Second selector 13 Third selector

Claims (2)

(57) [Claims] 1. A first coded data comprising at least orthogonally transformed and coded data of at least difference image data between frames and data associated therewith is inputted, and one frame of the input image itself is coded. A decoding unit for intermittently inputting the second coded data obtained by dividing the coded data so as to be input for one frame within a predetermined period, and reversing the data decoded and taken out by the decoding unit. A conversion unit for converting the original image data by quantization and inverse orthogonal transform; an addition unit for outputting final image data; and image data of at least one frame before storing the output image data of the addition unit a memory circuit for outputting an address control unit that controls the address of the memory circuit on the basis of the vector data retrieved from該復Goka unit, the output of the memory circuit A first selector that selects image data or digital zero data according to block type information extracted from the decoding unit, inputs the selected data to the adding unit, and adds the image data or the output image data of the conversion unit; From the extracted block type information, vector data, position information on the screen, and error recovery timing information, the decoding is performed within a period until the second coded data is extracted from the decoding unit for one frame after the error recovery. The first coded data input to the encoding unit is the image data at the screen position rewritten by the second coded data and at the screen position not rewritten by the second coded data; A determining unit for determining whether or not the specific differential image data to be added; and when the specific differential image data input is determined by the determining unit The image data output from the conversion unit to the addition unit is digital zero data, and the second coded data of one frame before the same screen position as the specific difference image data from the memory circuit. And a selection circuit for inputting the converted image data to the addition unit. 2. The second selection circuit selects one of output image data and digital zero data of the conversion unit based on a determination output of the determination unit and outputs the selected data to the addition unit.
And a third selector for selecting one of the vector data and digital zero data from the decoding unit based on the judgment output of the judgment unit and supplying the selected data to the address control unit. Claim 1
A decoding device in video encoding transmission.