JP2580674B2 - High frequency mold package - Google Patents
High frequency mold packageInfo
- Publication number
- JP2580674B2 JP2580674B2 JP63026905A JP2690588A JP2580674B2 JP 2580674 B2 JP2580674 B2 JP 2580674B2 JP 63026905 A JP63026905 A JP 63026905A JP 2690588 A JP2690588 A JP 2690588A JP 2580674 B2 JP2580674 B2 JP 2580674B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- exposed
- signal
- leads
- characteristic impedance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、信号用リードの両側に接地用リードを備え
たリードフレームと、前記信号用リードと接地用リード
それぞれの先端部（露出リード部）を除く前記リードフ
レームの部分（非露出リード部）をパッケージングする
樹脂モールド部とを有する高周波用モールド型パッケー
ジに関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a lead frame having a grounding lead on both sides of a signal lead, and a tip end (an exposed lead portion) of each of the signal lead and the grounding lead. ), And a resin mold part for packaging a part of the lead frame (non-exposed lead part).
（従来の技術） 第２図は従来例の高周波用モールド型パッケージの平
面から見た断面図である。第２図において、符号２は複
数の信号用リード４とその信号用リード４の両側に配置
された複数の接地用リード６とを備えたリードフレーム
である。８は半導体チップであり、この半導体チップ８
は樹脂モールド部10で樹脂モールドされている。また、
リードフレーム２の信号用リード４それぞれの各先端部
（露出リード部4a）を除く部分（非露出リード部4b）と
接地用リード６の各先端部（露出リード部6a）を除く部
分（非露出リード部6b）とはそれぞれ樹脂モールド部10
でそれぞれ樹脂モールドされている。なお、信号用リー
ド４と接地用リード６それぞれの非露出リード部4b,6b
は、ワイヤ12でそれぞれ半導体チップ８の所要箇所に接
続されている。(Prior Art) FIG. 2 is a cross-sectional view of a conventional high-frequency mold package as viewed from the top. In FIG. 2, reference numeral 2 denotes a lead frame including a plurality of signal leads 4 and a plurality of ground leads 6 arranged on both sides of the signal leads 4. Reference numeral 8 denotes a semiconductor chip.
Is resin-molded in the resin mold portion 10. Also,
A portion (non-exposed lead portion 4b) excluding each tip portion (exposed lead portion 4a) of each signal lead 4 of the lead frame 2 and a portion (non-exposed portion) excluding each tip portion (exposed lead portion 6a) of the grounding lead 6. The lead part 6b) is the resin mold part 10
, Respectively. The unexposed leads 4b and 6b of the signal lead 4 and the ground lead 6 respectively.
Are connected to required portions of the semiconductor chip 8 by wires 12, respectively.
（発明が解決しようとする課題） 上記の構成を有する従来例の高周波用モールド型パッ
ケージにあっては、信号用リード４とそれに対向してい
る接地用リード６それぞれの幅と相互間隔とがその露出
リード部4a,6bにおいても、非露出リード部4b,6におい
ても一様に等しく構成されていることから、マイクロ波
帯等の高周波信号が信号用リード４に与えられると、両
リード4,6が分布定数線路として作用するために、次に
述べるような問題点が指摘されていた。(Problem to be Solved by the Invention) In the conventional high-frequency molded package having the above configuration, the width and the interval between the signal lead 4 and the ground lead 6 facing the signal lead 4 are the same. Since the exposed leads 4a, 6b and the non-exposed leads 4b, 6 are also configured equally uniformly, when a high-frequency signal such as a microwave band is applied to the signal lead 4, both leads 4, The following problems were pointed out because 6 functions as a distributed constant line.
すなわち、信号用リード４の幅寸法をａ、信号用リー
ド４と接地用リード６との相互間隔をＷ、露出リード部
4a,6aの周囲の比誘電率をεｒ、非露出リード部4b,6bの
周囲の比誘電率をεｒ′とそれぞれ定めた場合、露出リ
ード部4a,6aで構成される分布定数線路の特性インピー
ダンスZoは幅ａ、相互間隔Ｗおよび比誘電率εｒの関数
となり、また、非露出リード部4b,6bで構成される分布
定数線路の特性インピーダンスZo′も幅ａ、相互間隔
Ｗ、非誘電率εｒ′の関数となる。That is, the width dimension of the signal lead 4 is a, the mutual distance between the signal lead 4 and the grounding lead 6 is W,
When the relative permittivity around 4a, 6a is defined as εr, and the relative permittivity around non-exposed leads 4b, 6b as εr ′, respectively, the characteristic impedance of the distributed constant line composed of exposed leads 4a, 6a Zo is a function of the width a, the mutual distance W and the relative permittivity εr, and the characteristic impedance Zo ′ of the distributed constant line composed of the non-exposed leads 4b and 6b is also the width a, the mutual distance W and the non-dielectric constant εr. '.
しかるに、露出リード部4a,6aの周囲が空気であるの
に対して露出リード部4a,6aの周囲が樹脂モールド部10
であるために、それぞれの比誘電率εｒとεｒ′とが異
なることになる結果、上記の両特性インピーダンスZo,Z
o′が一致しないことになる。However, while the area around the exposed leads 4a, 6a is air, the area around the exposed leads 4a, 6a is
As a result, the relative dielectric constants εr and εr ′ are different from each other, and as a result, the two characteristic impedances Zo, Z
o 'will not match.
ところが、露出リード部4a,6aと非露出リード部4b,6b
との境界部分でこのような特性インピーダンスZo,Zo′
の不一致があると、その境界部分で高周波信号の反射が
起こるため、半導体チップ８に対する所望の動作特性を
得ることができなくなるという問題があった。However, the exposed leads 4a, 6a and the non-exposed leads 4b, 6b
Characteristic impedance Zo, Zo '
When there is a mismatch, high-frequency signals are reflected at the boundary, and there is a problem that desired operating characteristics for the semiconductor chip 8 cannot be obtained.
本発明は、上記問題点に鑑みてなされたものであっ
て、露出リード部間で構成された分布定数線路の特性イ
ンピーダンスと非露出リード部間で構成された分布定数
線路の特性インピーダンスとを一致させることで両リー
ド部の境界部分での高周波信号の不要な反射が起こらな
いようにして半導体チップに対する所望の動作特性が得
られるようにすることを目的としている。The present invention has been made in view of the above problems, and has a characteristic impedance of a distributed constant line formed between exposed leads and a characteristic impedance of a distributed constant line formed between non-exposed leads. By doing so, it is an object of the present invention to prevent unnecessary reflection of a high-frequency signal from occurring at a boundary portion between the two lead portions and to obtain desired operation characteristics for the semiconductor chip.
（課題を解決するための手段） このような目的を達成するために、本発明は信号用リ
ードの両側に接地用リードを備えたリードフレームと、
前記信号用リードと接地用リードそれぞれの先端部（露
出リード部）を除く前記リードフレームの部分（非露出
リード部）をパッケージングする樹脂モールド部とを有
する高周波用モールド型パッケージにおいて、 前記信号用リードと接地用リードそれぞれの露出リー
ド部で構成される分布定数線路の特性インピーダンス
と、前記信号用リードと接地用リードそれぞれの非露出
リード部で構成される分布定数線路の特性インピーダン
スとが一致するように、前記信号用リードの幅と、その
信号用リードと接地用リードとの相互間隔との少なくと
も一方が設定されていることを特徴としている。(Means for Solving the Problems) In order to achieve such an object, the present invention provides a lead frame having a ground lead on both sides of a signal lead,
A high-frequency mold package having a resin mold portion for packaging a portion (non-exposed lead portion) of the lead frame except for a tip portion (exposed lead portion) of each of the signal lead and the grounding lead; The characteristic impedance of the distributed constant line constituted by the exposed leads of the lead and the grounding lead is equal to the characteristic impedance of the distributed constant line constituted by the non-exposed leads of the signal lead and the grounding lead. As described above, at least one of the width of the signal lead and the mutual interval between the signal lead and the ground lead is set.
（作用） この構成によれば、信号用リードと接地用リードそれ
ぞれの露出リード部周囲を囲む媒体の比誘電率と、非露
出リード部周囲を囲む媒体の比誘電率とが同じでなくて
も、信号用リードの幅と、その信号用リードと接地用リ
ードとの相互間隔との少なくとも一方が両露出リード部
で構成される分布定数線路の特性インピーダンスと、両
非露出リード部で構成される分布定数線路の特性インピ
ーダンスとが一致するように設定されていることから、
露出リード部と非露出リード部との境界部分での高周波
信号の不要な反射が起こらなくなり、その結果、樹脂モ
ールド部内にパッケージングされている半導体チップ
は、その高周波信号に対して所望の高周波特性を得るこ
とができる。(Operation) According to this configuration, even if the relative permittivity of the medium surrounding the exposed lead portion of each of the signal lead and the grounding lead and the relative permittivity of the medium surrounding the non-exposed lead portion are not the same. , At least one of the width of the signal lead and the mutual interval between the signal lead and the ground lead is constituted by the characteristic impedance of the distributed constant line constituted by both exposed leads, and constituted by both non-exposed leads. Since the characteristic impedance of the distributed constant line is set to match,
Unnecessary reflection of the high-frequency signal at the boundary between the exposed lead portion and the non-exposed lead portion does not occur. As a result, the semiconductor chip packaged in the resin mold portion has a desired high-frequency characteristic for the high-frequency signal. Can be obtained.
（実施例） 以下、本発明の実施例を図面を参照して詳細に説明す
る。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例に係る高周波用モールド型パ
ッケージの平面から見た断面図である。第１図におい
て、従来例に係る第２図に示した符号と同一の符号は、
その符号が示す部分、部分等と同様のものを示す。すな
わち、第１図において、符号２は信号用リード４（露出
リード部4aと非露出リード部4bとからなる。）と接地用
リード６（露出リード部6aと非露出リード部6bとからな
る。）とを有するリードフレーム、８は半導体チップ、
10は樹脂モールド部、12はワイヤである。上記の構成は
従来例と同様であるからその説明は省略する。FIG. 1 is a cross-sectional view of a high-frequency mold package according to an embodiment of the present invention as viewed from the top. In FIG. 1, the same reference numerals as those shown in FIG.
The same parts as those indicated by the reference numerals are shown. That is, in FIG. 1, reference numeral 2 denotes a signal lead 4 (consisting of an exposed lead 4a and a non-exposed lead 4b) and a grounding lead 6 (consisting of an exposed lead 6a and a non-exposed lead 6b). ), 8 is a semiconductor chip,
Reference numeral 10 denotes a resin mold portion, and reference numeral 12 denotes a wire. The configuration described above is the same as that of the conventional example, and the description thereof is omitted.
本実施例は次の構成に特徴を有している。すなわち、
信号用リード４の露出リード部4aの幅をa1、同じく信号
用リード４の非露出リード部4bの幅をa2とし、信号用リ
ード４の露出リード部6aと接地用リード６の露出リード
部6aとの相互間隔をW1、信号用リード４の非露出リード
部4bと接地用リード６の非露出リード部6bとの相互間隔
をW2とする。そして、両露出リード部4a,6aで構成され
る分布定数線路の特性インピーダンス（露出側特性イン
ピーダンス）をZo、両非露出リード部4b,6bで構成され
る分布定数線路の特性インピーダンス（非露出側特性イ
ンピーダンス）をZo′とすると、露出側特性インピーダ
ンスZoはa1とW1とその周囲の媒体（この例では空気）の
比誘電率εｒとの関数、つまりZo＝Zo（a1,W1,εｒ）と
なり、非露出側特性インピーダンスZo′はa2とW2とその
周囲の媒体（この例では樹脂モールド部10）の比誘電率
εｒ′との関数、つまりZo′＝Zo′（a2,W2,εｒ′）と
なる。そして、本実施例では、露出側特性インピーダン
スZoと非露出側特性インピーダンスZo′とが等しくなる
ように、信号用リード４の露出リード部4aの幅a1と、非
露出リード部4bの幅a2と、露出側と非露出側とにおける
両リード部4,6の相互間隔W1,W2とを、設定している。This embodiment is characterized by the following configuration. That is,
The width of the exposed lead portion 4a of the signal lead 4 is a1, the width of the non-exposed lead portion 4b of the signal lead 4 is a2, and the exposed lead portion 6a of the signal lead 4 and the exposed lead portion 6a of the grounding lead 6 are formed. And W2, and the mutual interval between the non-exposed lead portion 4b of the signal lead 4 and the non-exposed lead portion 6b of the grounding lead 6 is W2. The characteristic impedance (exposed side characteristic impedance) of the distributed constant line composed of both exposed leads 4a and 6a is Zo, and the characteristic impedance of the distributed constant line composed of both unexposed leads 4b and 6b (unexposed side). If the characteristic impedance) is Zo ', the exposed side characteristic impedance Zo is a function of a1 and W1 and the relative permittivity εr of the surrounding medium (air in this example), that is, Zo = Zo (a1, W1, εr). The non-exposed side characteristic impedance Zo 'is a function of a2 and W2 and the relative dielectric constant εr' of the surrounding medium (the resin molded portion 10 in this example), that is, Zo '= Zo' (a2, W2, εr '). Becomes In this embodiment, the width a1 of the exposed lead 4a and the width a2 of the non-exposed lead 4b of the signal lead 4 are set such that the exposed-side characteristic impedance Zo and the non-exposed-side characteristic impedance Zo 'are equal. The distances W1, W2 between the lead portions 4, 6 on the exposed side and the non-exposed side are set.
したがって、本実施例によれば、露出リード部4a,6a
と非露出リード部4b,6bそれぞれの周囲の媒体の比誘電
率が異なっていても、上記両特性インピーダンスZo,Z
o′が一致するように上記の幅の寸法と相互間隔とが設
定されているから信号用リード４に高周波信号が与えら
れた場合は、両リード4,6の前記境界部分での不要な高
周波信号の反射がなくなり、その結果、半導体チップ８
は所望の高周波特性でもって動作することができる。Therefore, according to the present embodiment, the exposed lead portions 4a, 6a
And the non-exposed leads 4b and 6b have different relative dielectric constants of the media around them.
When the high-frequency signal is given to the signal lead 4, unnecessary high-frequency signals at the boundary between the two leads 4 and 6 are set because the width dimension and the mutual interval are set so that o ′ coincides. There is no signal reflection, and as a result, the semiconductor chip 8
Can operate with desired high-frequency characteristics.
なお、本実施例では、信号用リード４の幅の寸法と両
リード4,6の相互間隔の両方の設定で両特性インピーダ
ンスZo,Zo′を一致させたが、信号用リード４の幅寸法
または両リード部4,6の相互間隔のいずれか一方のみの
設定で、上記の一致を行わせるようにしてもよい。In the present embodiment, both the characteristic impedances Zo and Zo 'are matched by setting both the width of the signal lead 4 and the interval between the leads 4 and 6, but the width of the signal lead 4 or The above-mentioned matching may be performed by setting only one of the mutual intervals between the two lead portions 4 and 6.
（効果） 以上説明したことから明らかなように本発明によれ
ば、信号用リードの幅の寸法または信号用リードと接地
用リードとの相互間隔の少なくとも一方の設定でもって
露出リード部間で構成された分布定数線路の特性インピ
ーダンスと非露出リード部間で構成された分布定数線路
の特性インピーダンスとを一致させるように構成したか
ら、露出リード部周囲の媒体の比誘電率と非露出リード
部周囲の媒体のそれとが一致していなくとも両リード部
の境界部分での高周波信号の不要な反射が起こらなくな
り、その結果、半導体チップを所望の高周波動作特性で
駆動させることができる。(Effects) As is apparent from the above description, according to the present invention, the configuration is made between the exposed lead portions by setting at least one of the width of the signal lead or the mutual interval between the signal lead and the ground lead. The characteristic impedance of the distributed constant line and the characteristic impedance of the distributed constant line formed between the non-exposed leads are configured to match, so that the relative dielectric constant of the medium around the exposed lead and the non-exposed leads Unnecessary reflection of the high-frequency signal at the boundary between the two lead portions does not occur even if it does not match that of the medium, and as a result, the semiconductor chip can be driven with desired high-frequency operation characteristics.
第１図は本発明の一実施例に係る高周波用モールド型パ
ッケージの平面から見た断面図、第２図は第１図に対応
する従来例の断面図である。 ２……リードフレーム、４……信号用リード、６……接
地用リード、８……半導体チップ、10……樹脂モールド
部、12……ワイヤ、4a,6a……露出リード部、4b,6b……
非露出リード部。 なお、図中同一符号は同一ないしは相当部分を示してい
る。FIG. 1 is a cross-sectional view of a high-frequency mold package according to one embodiment of the present invention as viewed from the top, and FIG. 2 is a cross-sectional view of a conventional example corresponding to FIG. 2 ... lead frame, 4 ... signal lead, 6 ... grounding lead, 8 ... semiconductor chip, 10 ... resin molded part, 12 ... wire, 4a, 6a ... exposed lead part, 4b, 6b ......
Non-exposed lead. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
たリードフレームと、前記信号用リードと接地用リード
それぞれの先端部（露出リード部）を除く前記リードフ
レームの部分（非露出リード部）をパッケージングする
樹脂モールド部とを有する高周波用モールド型パッケー
ジにおいて、 前記信号用リードと接地用リードそれぞれの露出リード
部で構成される分布定数線路の特性インピーダンスと、
前記信号用リードと接地用リードそれぞれの非露出リー
ド部で構成される分布定数線路の特性インピーダンスと
が一致するように、前記信号用リードの幅、およびその
信号用リードと前記接地用リードとの相互間隔の少なく
とも一方が設定されていることを特徴とする高周波用モ
ールド型パッケージ。A lead frame provided with grounding leads on both sides of a signal lead; and a portion of the lead frame (exposed lead portion) excluding a tip end (exposed lead portion) of each of the signal lead and the ground lead. A) a high-frequency mold type package having a resin mold part for packaging, wherein a characteristic impedance of a distributed constant line constituted by each exposed lead part of the signal lead and the ground lead;
The width of the signal lead and the width of the signal lead and the grounding lead are adjusted so that the characteristic impedance of the distributed constant line constituted by the non-exposed lead portions of the signal lead and the grounding lead respectively match. A high-frequency mold package, wherein at least one of the mutual intervals is set.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026905A JP2580674B2 (en) | 1988-02-08 | 1988-02-08 | High frequency mold package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026905A JP2580674B2 (en) | 1988-02-08 | 1988-02-08 | High frequency mold package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01202853A JPH01202853A (en) | 1989-08-15 |
| JP2580674B2 true JP2580674B2 (en) | 1997-02-12 |
Family
ID=12206242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63026905A Expired - Lifetime JP2580674B2 (en) | 1988-02-08 | 1988-02-08 | High frequency mold package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2580674B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766949B2 (en) * | 1990-09-28 | 1995-07-19 | 富士通株式会社 | IC package |
| JP4054188B2 (en) | 2001-11-30 | 2008-02-27 | 富士通株式会社 | Semiconductor device |
| JP2008218776A (en) | 2007-03-06 | 2008-09-18 | Renesas Technology Corp | Semiconductor device |
| US8829685B2 (en) * | 2009-03-31 | 2014-09-09 | Semiconductor Components Industries, Llc | Circuit device having funnel shaped lead and method for manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0812887B2 (en) * | 1985-04-13 | 1996-02-07 | 富士通株式会社 | High-speed integrated circuit package |
-
1988
- 1988-02-08 JP JP63026905A patent/JP2580674B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01202853A (en) | 1989-08-15 |
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