JP2578044Y2 - Discharge lamp power supply - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discharge lamp power supply having an inverter configuration for supplying lighting power to various discharge lamps such as a xenon discharge lamp of a dry copying machine.

[0002]

2. Description of the Related Art Conventionally, a discharge lamp power supply device having an inverter configuration of this kind is generally configured as shown in FIG. 5, and an AC input power supply 1 such as a commercial AC power supply is a full-wave type of a bridge rectifier circuit 2 of diodes D1 to D4. The DC power is converted to DC power by the rectification and smoothing of the smoothing capacitor C 1, and the DC power is supplied to the inverter circuit unit 3. The inverter circuit section 3 is formed by a switching circuit 4 and a transformer 5 for inverter output. The switching circuit 4 is a full-bridge circuit of high-frequency switching field effect transistors (hereinafter referred to as FETs) Q1 to Q4 as semiconductor switching elements. Formed by

Then, the FE is controlled by the drive control of the control circuit 6.
In the TQ1 to Q4, the FETs Q1 and Q4 and the FETs Q2 and Q3 perform high-frequency switching in opposite directions to each other, and energize the primary side of the transformer 5 with high frequency. By this high-frequency current, the transformer 5
A boosted high-frequency output is generated on the secondary side, and the high-frequency output is supplied to a capacitor C via a circuit current limiting reactor L.
2. Voltage rectification is performed by the diodes D5 and D6, and the discharge capacitor C3 is charged by the voltage rectified output.

[0004] That is, the black circles on the primary and secondary windings of the transformer 5 indicate the end of the winding start, and when the end of the winding is positive due to the voltage generated on the secondary side, a diode is used. The capacitor C2 is charged by the loop of D5, the capacitor C2, and the reactor L. When the end of the winding start is negative, the discharge capacitor C3 is charged by the loop of the reactor L, the capacitor C2, the diode D6, and the capacitor C3. At this time, the reactor L limits the peak value of the charging current.

By the way, in order to control the charging of the discharge capacitor C 3, a voltage (inter-terminal voltage) Vi at both ends p and n is detected by a control circuit 6. The control circuit 6 is configured as shown in FIG. 6 to charge the discharge capacitor C3 at a constant voltage. The control circuit 6 calculates an inter-terminal voltage Vi and a voltage Vr of a voltage reference signal of a reference power supply 7 corresponding to a specified voltage for charging by an operational amplifier. 8 to amplify the error.

Due to this error amplification, the output signal S1 of the operational amplifier 8 becomes a predetermined low level Lo as shown in FIG. 7A during the charging period of the discharge capacitor C3 where Vi <Vr.
w, and when charging progresses and becomes Vi ≧ Vr, the voltage rises from a low level Low according to the difference (Vi−Vr).

Then, the output signal S1 and the sawtooth signal S2 for the reference wave shown in FIG. 7A of the sawtooth wave generating circuit 9 are supplied to a comparator 10, and the comparator 10 generates the sawtooth signal S2. A signal S3 shown in FIG. 3B having a period and a pulse width of S1 ≧ S2 is formed. Further, the output signal S of the comparator 10
3 is supplied to the trigger terminal t of the flip-flop 11 and the AND gates 12, 13, and the flip-flop 11 is triggered every time the output signal S3 rises.

With this trigger, the output signal S4 of the non-inverted output terminal q of the flip-flop 11 changes to a binary value as shown in FIG. 7C, and the output signal of the inverted output terminal q ^* is inverted to the output signal S4. It changes by two values. Then, the output signals of the output terminals q and q ^* of the flip-flop 11 are
2 and 13, and the output signal S3 is divided by the two gates 12 and 13 as shown in FIGS.
Phase switching control signals S5, S6 are formed.

The driving auxiliary transistors Q5 and Q6 are switched by the two control signals S5 and S6, and the transformers 14 and 15 having a pulse transformer configuration are based on the switching.
Pulse power is supplied to the gate drive circuits 16 and 17 via the power supply terminal + B, and the pulse power supply supplies the gate signals of the FETs Q1 and Q4 having the waveform of the control signal S5 and the gate signals of the FETs Q2 and Q3 having the waveform of the control signal S6. Is formed.

Then, a discharge capacitor C3 of Vi <Vr
In the charging period, the pulse widths of the control signals S5 and S6 are fixed to the maximum, the energizing period on the primary side of the transformer 5 is kept longest, and when the charging is completed and Vi ≧ Vr, the control signal S
The pulse widths of e and Sf decrease and follow the difference (Vi-Vr), and the current application period is automatically controlled so that the inter-terminal voltage Vi is maintained at a specified voltage (rated voltage). FIG.
R1 and R2 are input and feedback resistors of the operational amplifier 8.

When the discharge capacitor C3 is charged to a specified voltage by the driving control of the control circuit 6, the electrode of the discharge lamp 18 composed of, for example, a xenon discharge lamp and the transformer for trigger wound around the discharge lamp 18 The discharge lamp 18 is turned on by a gap discharge between the discharge lamp 18 and the non-connection end of the vessel 19, and at this time, the discharge energy stored in the discharge capacitor C3 is released. After discharging the energy, the discharge capacitor C3 is charged again by the current obtained by rectifying the output of the secondary side of the transformer 5 by double voltage in the same manner as described above.

[0012]

In the conventional discharge lamp power supply device, during the charging period of the discharge capacitor C3, the FETs Q1 to Q4 of the switching circuit 4 are driven by the gate signal having the maximum pulse width, and the primary voltage of the transformer 5 is reduced. 8 is maintained at the maximum, but a reactor L is provided on the secondary side of the transformer 5, and the charging current injected into the discharge capacitor C3 due to the current limitation of the reactor L becomes as shown in FIG. As shown in the figure, the charge decreases with the progress of the charge, and thus there is a problem that the charge completion of Vi = Vr is not quickly reached.

The voltage V between terminals of the discharge capacitor C3 is
i changes as shown in FIG. 8B and reaches the specified voltage indicated by the one-dot chain line.

Further, in order to perform charging quickly, it is conceivable to increase the charging current by reducing the capacity of the reactor L. However, simply reducing the capacity of the reactor L causes an extremely large charging current especially at the initial stage of charging. Become larger, F
There is a problem that the current duty of each semiconductor element such as ETQ1 to Q4 increases. SUMMARY OF THE INVENTION It is an object of the present invention to provide a discharge lamp power supply device capable of quickly charging a discharge capacitor without increasing the current duty of each semiconductor element in the device.

[0015]

In order to achieve the above object, in a discharge lamp power supply device according to the present invention, a DC power supply is switched at a high frequency by drive control of a control circuit, and a primary voltage of a transformer for inverter output is increased. A switching circuit having a semiconductor switch configuration for supplying pulse power to a side, a discharge capacitor charged to a specified voltage by a rectified current of a secondary side output of the transformer and storing lighting energy of a discharge lamp, and a primary side of the transformer. And a current transformer for detecting a current flow,

The control circuit amplifies the error of the detection signal of the voltage between the terminals of the discharge capacitor and the voltage reference signal corresponding to the prescribed voltage, and fixes the voltage to a constant level during the charging period until the voltage between the terminals reaches the prescribed voltage. An output voltage detection unit that forms a charge limit signal that decreases and changes from the constant level in accordance with a voltage difference when the inter-terminal voltage becomes equal to or higher than the specified voltage;
A drive command section having a latch circuit configuration, which is periodically set to an ON command state by a clock signal to form a switching command signal of a switching circuit, and a detection signal of the current transformer and a charge limit signal are compared. And a comparator for resetting the drive command section to the off command state each time the current detection signal of the current transformer reaches the charge limit signal due to the setting of the current supply. Charge the capacitor with constant current.

[0017]

In the case of the discharge lamp power supply of the present invention configured as described above, the discharge capacitor is not limited in current by the reactor as in the conventional device, and the secondary output of the inverter output transformer is rectified. It is charged by current. Further, the current flowing through the primary side of the transformer based on the high-frequency switching of the switching circuit is detected by the current transformer.

Further, the switching command signal of the drive command section provided in the control circuit is periodically turned on by the setting of the clock signal, and the switching circuit is driven on by this signal, and the inverter output transformer is turned on. Current starts to flow on the primary side of. Then, the detection signal of the current transformer increases in proportion to the current flowing through the primary side of the inverter output transformer, and when this detection signal becomes equal to the charging limit signal of the output voltage detection unit, the drive command is issued by the comparison unit. The section is reset to the off command state, and the primary-side conducting current is turned off.

Thereafter, the setting by the clock signal and the reset by the comparing section are alternately repeated, and the current flowing through the primary side of the inverter output transformer is controlled to the current value specified by the charge limit signal. . During the charging period of the discharging capacitor, the charging limit signal of the output voltage detecting section is fixed at a constant level based on the detection of the voltage between the terminals of the capacitor, so that the current flowing through the primary side of the inverter output transformer is maintained. Is maintained at a constant current value determined by the charge limit signal, and the charge current of the discharge capacitor obtained by rectifying the secondary output of the transformer is controlled by the constant current.

At this time, the charging current does not decrease even if the voltage between the terminals of the discharge capacitor increases with the progress of charging, and the charging is completed quickly and efficiently with a sufficient charging current. In addition, since the upper limit of the charging current is regulated by the charging limit signal, the current duty of the semiconductor element or the like of the switching circuit does not increase at the beginning of charging.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described with reference to FIGS. FIG. 1 shows a case in which the transformer for inverter output has a flyback transformer configuration to greatly reduce the number of components. In FIG. 1, the same reference numerals as those in FIG. 5 denote the same components, and are different from the conventional device in FIG. The following (A)-(E)
Is the point. (A) Instead of the inverter circuit section 3 of FIG. 5, an inverter circuit section 22 formed by a switching circuit 20 and a transformer 21 for inverter output in a flyback transformer configuration is provided. (A) A current transformer 23 for detecting a current flow is provided on the primary side of the transformer 21. (C) A diode Dx for half-wave rectification is provided on the secondary side of the transformer 21 in place of the conventional current limiting reactor L and capacitor C2, diodes D5 and D6 of the voltage doubler rectifier circuit of FIG.
Only. (D) In order to control the driving of the switching circuit 20, a control circuit 24 of FIG. 2 is provided instead of the control circuit 6 of FIG.

The switching circuit 20 is formed by a mixed bridge circuit of two FETs Qa and Qb as semiconductor switching elements and two flywheel diodes Da and Db. The transformer 21 is formed by an insulated flyback transformer having a reactance having a gap in the core and having a large reactance so that a large amount of energy is released when the power supply to the primary side is turned off.

Further, the control circuit 24 includes an output voltage detecting section 25 formed by the reference power supply 7, the operational amplifier 24 and the input and feedback resistors Ra and Rb, a diode Dc and a resistor R.
c / Rd, a current / voltage converter 26 and a comparator 2
7, a driving command unit 30 formed by a clock generator 28 and a latch circuit 29, and a set of driving auxiliary transistors Qc,
Transformer 31 of pulse transformer configuration, gate drive circuit 32
And The mark ● of the transformer 21 indicates the end of the winding start.

The AC input power source 1 is converted into a DC power source by a bridge rectifier circuit 2 and a smoothing capacitor C1, and this DC power source is supplied to a switching circuit 20,
The high-frequency switching of the FETs Qa and Qb in the same phase by the control circuit 24 controls the energization of the primary side of the transformer 21 to perform high-frequency switching of the DC power supply.

At this time, the transformer 21 having the flyback transformer structure stores magnetic energy based on the current supplied to the primary side when the FETs Qa and Qb are turned on, and discharges the stored energy to the secondary side circuit when the FETs Qa and Qb are turned off. The energy stored in the leakage inductance of the transformer 21 is regenerated by the diodes Da and Db when the FETs Qa and Qb are turned off.

Since a sufficiently high-frequency high-frequency output is generated on the secondary side of the transformer 21, this high-frequency output is not half-wave rectified by the diode Dx but is subjected to half-wave rectification by a diode Dx, unlike a conventional device. The discharge capacitor C3 is charged to the specified voltage as in the related art. By the way, on the secondary side of the transformer 21, FIG.
No current limiting reactor such as the reactor L is provided, and the charging current of the discharge capacitor C3 during the charging period is controlled by the drive control of the control circuit 24, which will be described later.

Since the charging current does not decrease even if the charging proceeds and the inter-terminal voltage increases, the discharging capacitor C3
Is charged to the specified voltage more quickly than before. Further, when the discharge capacitor C3 is charged to the specified voltage, the electrodes of the discharge lamp 18 and the trigger transformer 1 are then charged, as in the case of the conventional device.
The discharge lamp 18 is turned on by triggering the gap discharge with the non-connection end of No. 9 to discharge the energy stored in the discharge capacitor C3.

Next, the drive control of the control circuit 24 will be described. First, the voltage Vi between the terminals of the discharge capacitor C3
The error of the voltage Vr of the voltage reference signal of the reference power supply 7 is amplified by the operational amplifier 24 of the output voltage detection unit 25.

At this time, the operational amplifier 24 computes the difference (Vr−Vi), unlike the operational amplifier 8 of FIG. 6, and the output of the charge limiting signal Sa is the discharge capacitor C that satisfies Vr> Vi.
3 during a predetermined high level H shown in FIG.
is held saturated at high, charging proceeds and Vr ≦ Vi
Becomes high level Hig according to the difference (Vr-Vi).
h. Further, a current flowing through the primary side of the transformer 21 is detected by the current transformer 23, and a current signal of the current transformer 23 is converted into a voltage signal by the converter 26.

Then, the high-frequency switching of the switching circuit 20 causes a pulse change in the current flowing through the primary side of the transformer 21, so that the output signal Sb of the converter 26 changes in pulse as shown in FIG. The peak value increases to the upper right in proportion to the energization time. Further, the charge limit signal Sa of the detection unit 25 and the output signal S of the conversion unit 26
b is supplied to the comparison unit 27, and the comparison unit 27 is supplied to the reset terminal r of the latch circuit 29 only when Sb ≧ Sa.
Becomes the high level of the reset command.

On the other hand, the clock generator 28 that determines the operating frequency of the switching circuit 20 supplies a clock pulse signal Sd having a constant period shown in FIG. Then, the latch circuit 29 is set to the ON command state each time the clock pulse signal Sd rises, and is reset to the OFF command state by the rise of the output signal Sc. By repeating this setting and resetting, the non-inverting input terminal q of FIG. The switching command signal Se shown in (c) is output.

The driving auxiliary transistor Qc is switched by the command signal Se, and a DC power supply of the power supply terminal + B is pulse-fed to the gate drive circuit 32 via the transformer 31. The pulsed power supply causes the FET having the waveform of the command signal Se to be fed.
Gate signals of Qa and Qb are formed, and the gate signals switch the FETs Qa and Qb.

When the latch circuit 29 is set to the ON command state, the FETs Qa and Qb are turned on and the transformer 2 is turned on.
1, a current starts to flow to the primary side of Sb1 and this current increases to Sb
= Sa, the latch circuit 29 is reset to the OFF command state by the output signal Sc of the comparison unit 27, and at this time, a charging current corresponding to the immediately preceding primary-side current is supplied to the discharge capacitor C3.

Further, when 1 is reached when Sb = Sa,
Since the charge limiting signal Sa is fixed at the high level during the charging period of the discharge capacitor C3, the current flowing on the next side does not change even if the charging of the discharge capacitor C3 proceeds.
After the charging, the charge limiting signal Sa changes in reverse to the inter-terminal voltage Vi, so that the inter-terminal voltage Vi changes to be pulled to the specified voltage.

Therefore, during the charging period of the discharging capacitor C3, the charging current of the discharging capacitor C3 is changed as shown in FIG.
The constant current control is performed as shown in (1), and the charging does not decrease even if the charging proceeds as in the conventional device, and the charging is completed quickly and efficiently.

In addition, due to the regulation of the charge limit signal Sa,
The initial current immediately after the start of charging does not become excessive, and the FET Qa,
The duty of current such as Qb does not increase.

When the charging is completed, the voltage Vi between the terminals of the discharge capacitor C3 is maintained at the specified voltage thereafter by the PWM control based on the charge limiting signal Sa in the same manner as in the conventional device. It should be noted that the terminal-to-terminal voltage Vi changes during the charging period as shown in FIG.
(B), the voltage rises linearly and reaches the specified voltage indicated by the one-dot chain line.

In the above embodiment, in order to reduce the number of components and simplify the configuration, a switching circuit 20 having a mixed bridge configuration is provided, and the driving auxiliary transistor and the gate driving circuit of the control circuit 24 are combined into one set. Although the voltage transformer for the inverter output is omitted as a transformer having a flyback transformer configuration, the voltage doubler rectifier circuit is omitted. However, the present invention can also be applied to a case where a switching circuit 4 of a conventional device and a transformer 5 for inverter output are used.

[0039]

The present invention is configured as described above and has the following effects. An output voltage detection unit 25, a comparison unit 27, and a drive command unit 30 are provided in a control circuit 24 that controls the drive of the switching circuit 20, and the drive command unit 30 is periodically turned on during the charging period of the discharge capacitor C3. The voltage is set and the primary side of the inverter output transformer 21 is energized, and based on the detection of the voltage Vi between the terminals of the discharge capacitor C3, the detection unit 25 forms the charge limiting signal Sa of a certain level, and the transformer 21 Since the drive command unit 30 is reset to the off command state each time the signal Sb of the current transformer 23 that detects the primary-side conducting current reaches the charging limit signal Sa, the primary-side conduction of the transformer 21 is stopped. The discharge capacitor C3 can be charged by the constant current control. At this time, even if the charging progresses, the charging current does not decrease and is insufficient. It can be.

In addition, the charging current is regulated by the charging limit signal Sa, the charging current does not become excessive even at the initial stage of charging, the current duty of the semiconductor element and the like of the switching circuit 20 does not increase, and the current value is not supplied to the semiconductor element and the like. The device can be formed without using a large expensive device. Therefore, it is possible to provide a discharge lamp power supply device that efficiently and quickly charges the discharge capacitor C3 with an inexpensive configuration.

[Brief description of the drawings]

FIG. 1 is a connection diagram of one embodiment of a discharge lamp power supply device of the present invention.

FIG. 2 is a detailed connection diagram of a part of FIG. 1;

FIGS. 3A, 3B, and 3C are timing charts for explaining the operation of FIG. 2;

FIGS. 4A and 4B are characteristic diagrams of a charging current and a terminal voltage of the discharge capacitor of FIG. 1;

FIG. 5 is a connection diagram of a conventional device.

FIG. 6 is a detailed connection diagram of a part of FIG. 5;

FIGS. 7A to 7E are timing charts for explaining the operation of FIG. 5;

8 (a) and 8 (b) are characteristic diagrams of charging current and inter-terminal voltage of the discharge capacitor of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 18 Discharge lamp 20 Switching circuit 21 Inverter output transformer 23 Current transformer 24 Control circuit 25 Output voltage detection unit 27 Comparison unit 30 Drive command unit C3 Discharge capacitor

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-123797 (JP, A) JP-A-64-56429 (JP, A) JP-A-63-187598 (JP, A) JP-A-56-187 134493 (JP, A) Japanese Utility Model 63-128,986 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H05B 41/30-41/34 H02M 9/06 H05B 41/29

Claims (1)

(57) [Scope of request for utility model registration] 1. A switching circuit having a semiconductor switch configuration for performing high-frequency switching of a DC power supply under driving control of a control circuit to supply a pulse to a primary side of a transformer for inverter output, and rectification of a secondary side output of the transformer. A discharge capacitor that is charged to a specified voltage by a current and stores lighting energy of the discharge lamp; and a current transformer that detects an energizing current on a primary side of the transformer, wherein the control circuit includes: A voltage detection signal and a voltage reference signal corresponding to the specified voltage are error-amplified and fixed at a constant level during a charging period until the inter-terminal voltage reaches the specified voltage, and the inter-terminal voltage is higher than the specified voltage. An output voltage detector that forms a charge limit signal that decreases and decreases from the constant level in accordance with the voltage difference, and periodically enters an ON command state by a clock signal. Comparing the driving command of the latch circuit configuration Tsu is bets to form a switching control signal of the switching circuit, the detection signal of the current transformer and the said charging restriction signal,
A comparison unit that resets the drive command unit to an off command state each time the conduction current increases due to the setting of the on command state and the detection signal of the current transformer reaches the charging limit signal; A discharge lamp power supply device configured to charge the discharge capacitor at a constant current during the charging period due to the limitation of the above.