JP2575520B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2575520B2 JP2575520B2 JP2135374A JP13537490A JP2575520B2 JP 2575520 B2 JP2575520 B2 JP 2575520B2 JP 2135374 A JP2135374 A JP 2135374A JP 13537490 A JP13537490 A JP 13537490A JP 2575520 B2 JP2575520 B2 JP 2575520B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- oxide film
- semiconductor substrate
- forming
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、半導体装置の製造方法に関し、特に半導体
装置の素子分離溝に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an element isolation groove of a semiconductor device.
（従来の技術） 以下、従来の半導体装置の製造方法を第１図および第
３図を参照して説明する。第１図は従来技術および本発
明の実施例に係わる半導体装置の製造方法を工程順に示
した断面図、第４図は従来技術の問題点を説明するため
の図である。(Prior Art) A conventional method of manufacturing a semiconductor device will be described below with reference to FIGS. 1 and 3. FIG. FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art and the embodiment of the present invention in the order of steps, and FIG. 4 is a diagram for explaining problems of the prior art.
半導体基板10の表面に第１の酸化膜１を形成する。次
に、その上に第２の酸化膜２を形成する。そして、レジ
ストを塗布しRIEにより素子領域４を分離するための素
子分離溝５を形成する（第１図（ａ））。A first oxide film 1 is formed on a surface of a semiconductor substrate 10. Next, a second oxide film 2 is formed thereon. Then, a resist is applied, and an element isolation groove 5 for isolating the element region 4 is formed by RIE (FIG. 1A).
その後レジストおよび第１の酸化膜1,第２の酸化膜２
を除去する。そして、素子領域４の表面および溝５内面
に第３の酸化膜６を形成する。次に、素子領域４上面の
一部に非酸化性膜７を形成する（第１図（ｂ））。After that, the resist and the first oxide film 1 and the second oxide film 2
Is removed. Then, a third oxide film 6 is formed on the surface of the element region 4 and the inner surface of the groove 5. Next, a non-oxidizing film 7 is formed on a part of the upper surface of the element region 4 (FIG. 1B).
そして、この非酸化性膜７を耐酸化マスクとして、素
子領域４の表面の一部および溝５内面に第４の酸化膜８
を形成する（第１図（ｃ））。Using the non-oxidizing film 7 as an oxidation resistant mask, a fourth oxide film 8 is formed on a part of the surface of the
Is formed (FIG. 1 (c)).
次に、第４の酸化膜８を形成した溝５にポリシリコン
９を埋め込みポリシリコンを平坦化した後、薄いキャッ
プ酸化膜12を形成する。そしてこの素子領域４には周知
の方法により、例えば、Ｎ型エミッタ領域Ｅ、Ｐ型ベー
ス領域Ｂ、Ｎ型コレクタ領域Ｃが形成される（第１図
（ｄ））。Next, after the polysilicon 9 is buried in the trench 5 in which the fourth oxide film 8 is formed and the polysilicon is planarized, a thin cap oxide film 12 is formed. In the element region 4, for example, an N-type emitter region E, a P-type base region B, and an N-type collector region C are formed by a known method (FIG. 1D).
この製造方法では第３図に示すように、素子分離溝５
の上部のコーナー部31はほぼ直角になっている。そのた
め、素子領域４の表面の一部および溝５内面に第４酸化
膜８を形成する際、溝５の上部のコーナー31に酸化時の
熱応力集中、体積膨張等による応力の集中が起こり、そ
のコーナー部31に転位欠陥32が発生することがあった。In this manufacturing method, as shown in FIG.
The upper corner portion 31 is substantially right-angled. Therefore, when the fourth oxide film 8 is formed on a part of the surface of the element region 4 and the inner surface of the groove 5, stress concentration due to thermal stress concentration, volume expansion, and the like at the time of oxidation occurs at the upper corner 31 of the groove 5, In some cases, dislocation defects 32 were generated in the corner portions 31.
転位欠陥は、素子領域間の分離特性や素子領域に形成
される素子特性を劣化させる。例えば、素子領域にバイ
ポーラトランジスタでアレーを形成した場合、転位欠陥
はコレクタ間のリーク電流を増加し、あるいはIc−hfe
特性等のトランジスタ特性を劣化させる。つまり転位欠
陥がある密度で存在すると、欠陥を中心とする再結合電
流が増加するために素子特性や素子間分離特性を劣化さ
せるという欠点があった。Dislocation defects deteriorate the isolation characteristics between element regions and the characteristics of elements formed in the element regions. For example, when an array is formed with a bipolar transistor in the element region, the dislocation defect increases the leak current between the collectors or increases the Ic- hfe
Deterioration of transistor characteristics such as characteristics. In other words, if dislocation defects exist at a certain density, recombination current centering on the defects increases, and thus there is a disadvantage that device characteristics and device isolation characteristics are deteriorated.
（発明が解決しようとする課題） このように、従来の半導体装置の製造方法を用いた場
合、素子分離溝の上部のコーナー部に転位欠陥が発生
し、素子領域間の分離特性や素子領域に形成される素子
特性を劣化させるという問題があった。(Problems to be Solved by the Invention) As described above, when the conventional method of manufacturing a semiconductor device is used, dislocation defects are generated at the upper corners of the element isolation trenches, and the isolation characteristics between the element regions and the element regions are deteriorated. There is a problem that the characteristics of the formed element are deteriorated.
本発明は、以上の点に鑑み、素子分離溝の上部のコー
ナー部に発生する転位欠陥を抑制し、素子領域間の分離
特性や素子領域に形成される素子特性を向上する半導体
装置の製造方法を提供する。In view of the above, the present invention is directed to a method of manufacturing a semiconductor device, which suppresses dislocation defects generated in a corner portion above an element isolation groove and improves isolation characteristics between element regions and element characteristics formed in the element regions. I will provide a.
［発明の構成］ （課題を解決するための手段） 本発明による半導体装置の製造方法は、半導体基板上
に絶縁膜を形成する工程と、前記絶縁膜下の半導体基板
表面を含めて前記絶縁膜をRIEによる等方性エッチング
により除去し浅い素子分離溝形成用溝を形成する工程
と、前記素子分離形成用溝の側面の半導体基板表面を異
方性エッチングし傾斜をつける工程と、前記素子分離形
成用溝底面の半導体基板を異方性エッチング除去し深い
素子分離溝を形成する工程とを備えたことを特徴とす
る。[Constitution of the Invention] (Means for Solving the Problems) In a method of manufacturing a semiconductor device according to the present invention, a step of forming an insulating film on a semiconductor substrate and the insulating film including a surface of the semiconductor substrate under the insulating film Forming a shallow device isolation groove forming groove by isotropic etching by RIE, anisotropically etching the semiconductor substrate surface on the side surface of the device isolation forming groove to form a slope, Forming a deep device isolation groove by anisotropically removing the semiconductor substrate on the bottom surface of the formation groove.
（作用） 製造工程中、半導体基板上に形成された絶縁膜をその
絶縁膜下の半導体基板表面を含めて等方性エッチング除
去し素子分離溝形成用溝を形成した後、この素子分離溝
形成用溝の半導体基板表面を異方性エッチングし傾斜を
つけることにより、素子分離溝表面および基板に酸化膜
を形成する際、コーナー部の転位欠陥が抑制できる。(Operation) During the manufacturing process, the insulating film formed on the semiconductor substrate is isotropically etched including the surface of the semiconductor substrate under the insulating film to form a groove for forming an element isolation groove. By disposing anisotropically etching the surface of the semiconductor substrate of the trench for forming an oxide film on the surface of the isolation trench and the substrate, dislocation defects at corners can be suppressed.
（実施例） 以下、本発明の実施例を第１図および第２図を参照し
て説明する。第１図は本発明の実施例を工程順に示した
断面図、第２図は本発明の実施例の要部を示した断面図
である。(Example) Hereinafter, an example of the present invention will be described with reference to FIG. 1 and FIG. FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps, and FIG. 2 is a sectional view showing a main part of the embodiment of the present invention.
まず、半導体基板10の表面に熱酸化によりシリコン酸
化膜１を形成し、その上からシリコンナイトライド２を
形成する。次にCVD法によりシリコン酸化膜３を形成
後、レジストを塗布してRIEによってシリコン酸化膜１
下の数千Åの半導体基板10を含めてシリコン酸化膜１、
シリコンナイトライド２およびシリコン酸化膜３を除去
し素子分離溝形成用溝５′を形成する（第２図
（ａ））。First, a silicon oxide film 1 is formed on the surface of a semiconductor substrate 10 by thermal oxidation, and a silicon nitride 2 is formed thereon. Next, after forming a silicon oxide film 3 by the CVD method, a resist is applied, and the silicon oxide film 1 is formed by RIE.
The silicon oxide film 1, including the lower thousands of semiconductor substrates 10,
The silicon nitride 2 and the silicon oxide film 3 are removed to form an element isolation groove forming groove 5 '(FIG. 2A).
次に、異方性エッチングにより溝５′の半導体基板10
の側面傾斜13をつける（第２図（ｂ））。Next, the semiconductor substrate 10 in the groove 5 'is anisotropically etched.
(FIG. 2 (b)).
そして、RIEにより溝５′をさらに深く掘り５〜７μ
の深さの素子分離溝５を形成する。これにより溝５で分
離された素子領域４が形成される（第１図（ａ）および
第２図（ｃ））。Then, the groove 5 'is dug deeper by RIE to 5-7μ.
Is formed. Thus, the element regions 4 separated by the grooves 5 are formed (FIGS. 1A and 2C).
次に、レジストおよびシリコン酸化膜１、シリコンナ
イトライド２、シリコン酸化膜３を除去する。そしてH2
およびO2ガス中で950℃の熱酸化を行い半導体基板１上
および溝５内面に500Åのシリコン酸化膜６を形成し、
さらに減圧CVD法により780℃で厚さ500〜1,500Åのシリ
コンナイトライド膜を形成し、この膜をプラズマエッチ
ングして、素子領域４上の一部に非酸化膜７を形成する
（第１図（ｂ））。Next, the resist and the silicon oxide film 1, the silicon nitride 2, and the silicon oxide film 3 are removed. And H 2
Thermal oxidation at 950 ° C. in O 2 and O 2 gas to form a 500 ° silicon oxide film 6 on the semiconductor substrate 1 and on the inner surface of the groove 5,
Further, a silicon nitride film having a thickness of 500 to 1,500 ° is formed at 780 ° C. by a low pressure CVD method, and this film is plasma-etched to form a non-oxide film 7 on a part of the element region 4 (FIG. 1). (B)).
その後、この非酸化性膜７を耐酸化マスクとして、素
子領域４の表面の一部および溝５内面に1000Åのウェッ
ト酸化を行い、膜厚8000Åの酸化膜８を形成する（第１
図（ｃ）および第２図（ｄ））。Thereafter, using the non-oxidizing film 7 as an oxidation-resistant mask, a part of the surface of the element region 4 and the inner surface of the groove 5 are subjected to wet oxidation of 1000 ° to form an oxide film 8 having a thickness of 8000 °.
Figure (c) and Figure 2 (d).
そして、溝５にポリシリコン９を埋め込み、ポリシリ
コン９を平坦化した後、薄いキャップ酸化膜12を形成す
る。この素子領域４には、周知の製法により例えば、Ｎ
型エミッタ領域Ｅ、ベース領域Ｂ、コレクター領域Ｃの
トランジスタが形成される（第１図（ｄ）および第２図
（ｅ））。Then, a polysilicon 9 is buried in the trench 5, and after the polysilicon 9 is planarized, a thin cap oxide film 12 is formed. The element region 4 is formed with, for example, N
Transistors of a type emitter region E, a base region B, and a collector region C are formed (FIGS. 1 (d) and 2 (e)).
本発明の実施例に示した工程にしたがい、バイポーラ
アレイを試作した結果、素子分離溝５を酸化した後の溝
の上部コーナー部11は第２図（ｄ）に示すようにまるめ
られる。As a result of trial production of a bipolar array according to the steps shown in the embodiment of the present invention, the upper corner portion 11 of the groove after oxidizing the element isolation groove 5 is rounded as shown in FIG. 2 (d).
そのため、酸化時の熱応力集中、体積膨張等による応
力の集中が緩和され、従来技術で問題となった溝の上部
コーナー部11から発生する転位欠陥の発生を抑制するこ
とができる。よって、素子領域間の分離特性や素子領域
に形成される素子特性を向上する。Therefore, concentration of stress due to thermal stress concentration, volume expansion, and the like during oxidation is reduced, and the occurrence of dislocation defects generated from the upper corner portion 11 of the groove, which has been a problem in the related art, can be suppressed. Therefore, the isolation characteristics between the element regions and the characteristics of the elements formed in the element regions are improved.
［発明の効果］ 以上の結果から明らかなように、本発明では、素子分
離溝上部コーナー部に発生する転位欠陥が抑制でき、素
子領域間の分離特性や素子領域に形成される素子特性が
向上する。[Effects of the Invention] As is clear from the above results, in the present invention, dislocation defects generated in the upper corner portion of the element isolation groove can be suppressed, and the isolation characteristics between the element regions and the element characteristics formed in the element regions are improved. I do.
【図面の簡単な説明】 第１図は本発明の実施例および従来に係わる半導体装置
の製造方法を工程順に示した断面図、 第２図は本発明の実施例に係わる半導体装置の製造方法
の要部を工程順に示した断面図、 第３図は従来の半導体装置の製造方法の問題点を説明す
るための図である。 １……シリコン酸化膜、２……シリコンナイトライド、 ３……シリコン酸化膜、４……素子領域、 ５……素子分離溝、６……シリコン酸化膜、 ８……酸化膜、９……ポリシリコン、10……半導体基
板、 11……コーナー部、12……キャップ酸化膜、13……傾
斜。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing an embodiment of the present invention and a conventional method for manufacturing a semiconductor device in the order of steps, and FIG. 2 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing a main part in the order of steps, and FIG. DESCRIPTION OF SYMBOLS 1 ... Silicon oxide film, 2 ... Silicon nitride, 3 ... Silicon oxide film, 4 ... Element region, 5 ... Element isolation groove, 6 ... Silicon oxide film, 8 ... Oxide film, 9 ... Polysilicon, 10: Semiconductor substrate, 11: Corner, 12: Cap oxide film, 13: Inclined.
Claims (1)
前記絶縁膜下の半導体基板表面を含めて前記絶縁膜をRI
Eによる等方性エッチングにより除去し、浅い素子分離
溝形成用溝を形成する工程と、前記素子分離形成用溝の
側面の半導体基板表面を異方性エッチングし傾斜をつけ
る工程と、前記素子分離形成用溝底面の半導体基板を異
方性エッチング除去し深い素子分離溝を形成する工程と
を備えたことを特徴とする半導体装置の製造方法。A step of forming an insulating film on a semiconductor substrate;
The insulating film including the surface of the semiconductor substrate under the insulating film is subjected to RI
Removing by isotropic etching with E to form a shallow device isolation groove forming groove, anisotropically etching the semiconductor substrate surface on the side surface of the device isolation forming groove to form a slope, Forming a deep device isolation groove by anisotropically removing the semiconductor substrate on the bottom surface of the formation groove.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2135374A JP2575520B2 (en) | 1990-05-28 | 1990-05-28 | Method for manufacturing semiconductor device |
| KR1019910008656A KR960006714B1 (en) | 1990-05-28 | 1991-05-27 | Manufacturing Method of Semiconductor Device |
| EP91108691A EP0459397B1 (en) | 1990-05-28 | 1991-05-28 | Method of fabricating a semiconductor device having a trench for device isolation |
| DE69132676T DE69132676T2 (en) | 1990-05-28 | 1991-05-28 | Method for producing a semiconductor device with a trench for the insulation components |
| US08/250,110 US5434447A (en) | 1990-05-28 | 1994-05-26 | Semiconductor device having a trench for device isolation and method of fabricating the same |
| US08/705,705 US5683908A (en) | 1990-05-28 | 1996-08-30 | Method of fabricating trench isolation structure having tapered opening |
| US08/874,317 US5858859A (en) | 1990-05-28 | 1997-06-13 | Semiconductor device having a trench for device isolation fabrication method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2135374A JP2575520B2 (en) | 1990-05-28 | 1990-05-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0430556A JPH0430556A (en) | 1992-02-03 |
| JP2575520B2 true JP2575520B2 (en) | 1997-01-29 |
Family
ID=15150224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2135374A Expired - Lifetime JP2575520B2 (en) | 1990-05-28 | 1990-05-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2575520B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100230384B1 (en) * | 1996-11-18 | 1999-11-15 | 윤종용 | Method for Forming Trench of Semiconductor Device |
| KR100415096B1 (en) * | 1997-12-19 | 2004-03-22 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
| JP2000114400A (en) | 1998-10-08 | 2000-04-21 | Nec Corp | Semiconductor memory device and its manufacture |
| KR20030049201A (en) * | 2001-12-14 | 2003-06-25 | 주식회사 하이닉스반도체 | Method for forming a isolation film of semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS582030A (en) * | 1981-06-29 | 1983-01-07 | Nec Corp | Processing method for semiconductor crystal |
| JPS60126847A (en) * | 1983-12-14 | 1985-07-06 | Hitachi Micro Comput Eng Ltd | Manufacture of semiconductor device |
| JPS60160125A (en) * | 1984-01-30 | 1985-08-21 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1990
- 1990-05-28 JP JP2135374A patent/JP2575520B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0430556A (en) | 1992-02-03 |
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