JP2571576B2 - Machine check holt processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention provides a machine check and halt processing system configured to halt a CPU based on an error signal detected when data is read from a memory. To solve the problem that the CPU is stopped before executing the error recovery processing by software due to consecutive errors when reading data from memory, the vector request signal or vector By stopping the CPU only when an error occurs again between the time the response signal is output and the error flag is cleared by the error recovery process,
Error recovery processing by software can be executed at the time of divisional reading or the like.

[Industrial applications]

The present invention relates to a machine check-halt processing device configured to be able to execute recovery processing by software even if errors occur consecutively when a plurality of data are read by one instruction.

[Problems to be solved by conventional technology and invention]

If an error such as a parity error is detected when the CPU (central processing unit) reads data from the memory, the erroneous read data (or instruction, etc.)
Since U may run away and destroy resources, it is necessary to forcibly stop the CPU (machine check halt).
At this time, if incorrect data does not lead to runaway,
It is desirable to recover this error by software and continue processing.

To determine whether to stop the CPU, for example, as shown in FIG. 7A, when a memory read error occurs, hardware sets an error flag and simultaneously causes an interrupt to the CPU. Next, when the software succeeds in the error recovery processing in the generated interrupt processing, the error flag is cleared, and the processing returns to the original processing upon return from the interrupt. On the other hand, as shown in FIG. 7 (b), the software is executing the error recovery processing in the generated interrupt processing, and two more steps are performed before the error flag is cleared.
If a second error occurs, the hardware determines that error recovery processing is not possible and forcibly stops the CPU.

However, in recent years, the width of data handled by executing one instruction has tended to increase due to an increase in the speed of the CPU. In some cases, the data is read by executing a memory read instruction, and the CPU continuously reads data from the memory while executing one instruction. For example, when reading 16-bit data from an 8-bit memory, the CPU reads 8-bit data from the memory twice consecutively. Therefore, for example, if there is any abnormality in the data bus, as shown in FIG. 7 (c), a continuous error occurs during execution of one instruction, and even if the error does not cause the CPU to run away,
There is a problem that the CPU is stopped before the interrupt is accepted by the CPU and the error recovery processing is executed.

[Means for solving the problem]

In order to solve the above problem, the present invention relates to a case where an error occurs again after an error has occurred and before an error flag is cleared by an error recovery process after a vector request signal or a vector response signal is output. To stop the CPU.

 The configuration of the present invention will be described with reference to FIG.

In FIG. 1, an error flag 1 is set, for example, by an illustrated parity error signal when an error is detected, and is reset by an illustrated error clear signal when the error is recovered by an error recovery process.

The machine check enable flag 2 is set when the vector request signal or the vector response signal is output while the error flag 1 is set, and is reset when the error flag 1 is reset.

The machine check halt flag 3 is for generating a machine check halt signal.

[Action]

 Next, the operation will be described.

In FIG. 1, it is detected that an error has occurred in the data read from the memory, and the error flag 1 notified of the error signal (parity error signal) is set and the interrupt request signal is transmitted to the CPU. Notice. Upon receiving the interrupt request signal, the CPU outputs a vector (a value indicating the head address of the interrupt processing) request signal. The interrupt source returns a vector number and a vector response signal to the CPU. At this time, the machine check enable flag 2 is set by the vector request signal or the vector response signal.
Then, after the machine check enable flag 2 is set, before the CPU receiving the notification of the vector response signal terminates the execution of the predetermined recovery processing and notifies the error flag 1 to the error flag 1 and resets it. When the error signal (parity error signal) is notified again, the machine check halt flag 3 is set and the CPU is stopped.

As described above, after an error occurs and the vector request signal or vector response signal is output, if the error occurs again before the error recovery processing is executed, the machine check halt signal is notified to the CPU and stopped. By doing so, a plurality of memory reads are executed by one instruction, and even if errors occur consecutively, an opportunity for error recovery processing is provided.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be described in detail with reference to FIGS. This embodiment shows a specific example in which a parity bit is added to data to be written to a memory and a parity check is performed at the time of memory reading. In the figure, a parity error signal represents an error signal output from a parity check circuit (not shown), and the error check signal represents a strobe signal for giving a parity check timing. The interrupt request signal indicates a signal for requesting an interrupt to the CPU, the machine check halt signal indicates a signal for stopping the CPU, and the error clear signal indicates a signal for resetting the error flag 1 when the error recovery processing is successful. The vector request signal represents a signal transmitted from the CPU to the interrupt request source in response to the interrupt request signal, and the vector response signal is a signal responded to the CPU from the interrupt request source in response to the vector request signal. Represents

The error flag 1 is set by an error check signal notified from the memory (parity check circuit) when an error occurs during a memory read, and an error clear signal notified from the CPU when the error is recovered by the error recovery processing. This is the FF (flip-flop) that is reset by.

The machine check enable flag 2 is an FF that is set when the vector request signal or the vector response signal is notified after the error flag 1 is set, and is reset when the error flag 1 is reset.

The machine check halt flag 3 is for notifying the CPU of a machine check halt signal to stop the CPU (halt) when the machine check enable flag 2 is set and a parity error signal is notified.

Next, the operation of the configuration of FIG. 1 will be described in detail with reference to FIG. 2 and FIG.

FIG. 2A shows a state in which the CPU executes a 16-bit read instruction.

In the figure, (a-1) shows the upper 8 bits read from the memory in response to the 16-bit read instruction shown in (a), a parity error signal is notified to the error flag 1 in FIG. FIG. 3 shows a state in which a request signal is notified to the CPU (FIGS. 3A and 3B).

In the figure, (a-2) successively reads the lower 8 bits from the memory, and outputs a parity error signal to the AND circuit 6 in FIG.
However, since the machine check enable flag 2 is not set, the machine check halt signal is not transmitted (FIGS. 3A and 3B).

(B) in the figure shows a state in which the CPU accepts an interrupt. This represents this state because the CPU normally accepts an interrupt at a break in instruction execution. When accepting the interrupt, the CPU notifies the interrupt request source of the vector request signal.
In response to this, the request source notifies the CPU of the vector response signal and the vector number. When a vector request signal is sent from this CPU to the request source, or a vector response signal is sent from the request source.
When sent to the CPU, the machine check enable flag 2 in FIG. 1 is set (FIGS. 3A and 3B).

(C) in the figure shows a state in which the CPU executes interrupt processing.

(D) in the figure shows a state in which a parity error has occurred while data is being read from the memory or the like for error recovery.

(E) in the figure shows a state where the CPU is stopped because the error recovery is no longer possible. This is because the parity error signal is notified again while the machine check enable flag 2 in FIG. 1 is set, and the machine check halt flag 3 is notified via the AND circuit 6 to this effect. Means a state sent to the CPU (FIG. 3 (b) in the figure). If no error occurs during the error recovery processing, the error is corrected by the error recovery processing, and an error clear signal is notified to the error flag 1 in FIG. I)
As shown in the drawing, the machine check enable flag 2 is also reset. Then, a series of error recovery processing ends, and the processing returns from the interrupt processing to the original processing.

As described above, even if errors occur consecutively when reading data from memory multiple times with one instruction, a vector request signal or vector response signal is output instead of immediately stopping the CPU. After that,
By stopping the CPU when an error occurs again before the error flag is reset, it is possible to provide an opportunity for error recovery by software.

FIG. 4 shows a configuration diagram of another embodiment of the present invention. this is,
When the parity error signal is notified and the error flag 1 is set, A is given to the CPU (means a predetermined level).
In addition to providing a level interrupt request signal, a decoder 4 and an AND circuit 5 are newly provided to decode the interrupt recognition level signal notified from the CPU and perform a machine check only when the self-notified A-level interrupt signal is received. The enable flag 2 is set. By adopting this configuration, it is possible to transmit a minimum necessary machine check halt signal. This will be described below with reference to FIGS. 4 to 6.

In FIG. 5, (A) shows a state in which the CPU executes a 16-bit read instruction.

(A-1) in the figure reads the upper 8 bits from the memory in response to the (A) 16-bit read instruction in the figure, and sets a parity error signal by notifying the error flag 1 in FIG. The state in which the level interrupt request signal is notified to the CPU is shown (FIGS. 6A and 6B).

In the figure, (A-2) successively reads the lower 8 bits from the memory, and outputs a parity error signal to the AND circuit 6 in FIG.
However, since the machine check enable flag 2 is not set, the machine check halt signal is not transmitted (FIGS. 6A and 6B).

In the figure (B-1), even if a level B vector request signal is notified from the CPU, this is not the A level for which the interrupt request was made in the figure (A-1). This shows a state in which another request source responds to the CPU with the level B vector response signal and vector number without performing the setting, executes the level B interrupt processing, and then returns.

In (B-2) of the figure, since the level A vector request signal was sent from the CPU, the request source returns the response signal of level A and the vector number to the CPU, and the decoder 4 and the AND circuit 5 in FIG. Indicates a state in which the machine check enable flag 2 is set via the. (FIGS. 6A and 6B).

(C) in the figure shows a state in which the CPU executes the level A interrupt processing.

(D) in the figure shows a state in which a parity error further occurs while data is being read from a memory or the like for error recovery.

(E) in the figure shows a state where the CPU is stopped because the error is no longer recoverable. This is because the parity error signal is notified again with the machine check enable flag 2 set in FIG. 4, and the machine check halt flag 3 is set via the AND circuit 6, and the machine check halt signal is sent to the CPU. FIG. 6 shows a state of being notified and stopped (FIG. 6 (b) in FIG. 6). If no error occurs during the error recovery processing, the error is corrected by the error recovery processing, and an error clear signal is notified to the error flag 1 in FIG. B) The reset is performed as shown in the figure, and the machine check enable flag 2 is also reset. Then, a series of error recovery processing ends, and the processing returns from the level A interrupt processing to the original processing.

As described above, even if errors occur consecutively when reading data from memory multiple times in a single instruction, instead of immediately stopping the CPU, the level A vector transmitted by itself is transmitted. If an error occurs again before the error flag is reset after recognizing that the request signal or vector response signal has been output, the CPU
In this way, it is possible to provide an opportunity for error recovery by software.

〔The invention's effect〕

As described above, according to the present invention, if an error occurs again after an error occurs and before the error flag is cleared by the error recovery processing after the vector request signal or the vector response signal is output Only CPU
In this case, the error recovery process can be executed by software, such as when reading multiple pieces of data consecutively with one instruction. It can be stopped to prevent resource destruction.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the present invention, FIG. 3 is a time chart of the present invention, FIG. FIG. 4 is an operation explanatory diagram of the configuration of FIG. 4, FIG. 6 is a time chart of the configuration of FIG. 4, and FIG. In the figure, 1 is an error flag, 2 is a machine check enable flag, 3 is a machine check halt flag, 4 is a decoder, and 5 and 6 are AND circuits.

Claims (2)

(57) [Claims] 1. A means for sending an interrupt request signal to a CPU based on a first error signal detected at the time of a memory access executed by one memory access instruction, and the one memory access instruction Means for invalidating the second and subsequent error signals detected during the period before the end of the execution and after the detection of the first error signal, based on the interrupt request signal, Means for instructing a halt of CPU operation in response to a third error signal detected during an interrupt processing for error recovery, which is started after execution of the access instruction is completed, a machine check comprising: Holt processing equipment. 2. An interrupt request of a predetermined level different for each type of interrupt request is sent to the CPU as the interrupt request signal, and the interrupt recognition level signal notified from the CPU is set to the predetermined level of the sent out. The machine check halt processing apparatus according to claim 1, wherein a halt of CPU operation is instructed in accordance with the third error signal only when the interrupt request signal is satisfied.