JP2568393B2 - Game system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game system. More specifically, the present invention relates to a game system capable of playing game software stored in a memory cartridge, for example.

[0002]

2. Description of the Related Art Conventionally, there has been no game system in which a CPU executes two programs that cannot remain in the same address space. For example, there has been no game system that executes a control program stored in an arbitrary address space and then executes a game program in another bank which is also stored in the same address space.

[0003]

Therefore, according to the prior art, the control program and the game program are stored in different address spaces different from each other.
The address space accessible by the PU must be expanded, or the game program must be reduced by the capacity of the control program.

[0004] Therefore, a main object of the present invention is to allocate a control program and a game program which are not executed after the start of a game to different banks in the same address space but different banks.
Switching between the banks to which the control program and the game program are assigned, and executing both the control program and the game program without expanding the address space accessible by the processing means and without reducing the game program. That is.

[0005]

SUMMARY OF THE INVENTION The present invention is a game system used to be connected to a monitor and for displaying a game image on the monitor, having at least a first address space and a second address space. Processing means (60) for displaying an image for a game and controlling the start of the game, arranged in the first address space, and executed by the processing means to display an image for the game on a monitor. Game program storage means (BK1 to BK14) storing a game program to be read, a read / write memory (86) comprising a memory readable and writable arranged in a second address space, and allocated to a first address space. Control program (BK0, FIG. 11) for controlling the start of the game by being executed by the processing means and being executed by the processing means System program storage means (BK0, S19, S10) storing a copy program for copying at least a part of the control program to a readable / writable memory arranged in the second address space.
9, S207), first operating means (20a, 20b) for playing a game by an operation of the player, and second operating means (20a, 20b) for receiving an instruction to start a game program by an operation of the player Processing means copies at least a part of the control program to a readable / writable memory based on a copy program, executes the copied control program, and executes a game based on an operation of a second operation means by a player. A game system characterized by controlling start of a program, displaying a game image on a monitor based on execution of the game program, and changing a display state thereof in response to a first operation means.

[0006]

A processing means such as a CPU copies at least a part of a control program of the system program storage means to a readable / writable memory such as a RAM based on a copy program of the system program storage means. Then, the CPU executes the copied control program, starts execution of the game program based on the operation of the second operation means by the player, and displays a game image on the monitor based on the execution of the game program. The display state is changed in response to the first operation means.

[0007]

According to the present invention, a control program is temporarily copied to a readable / writable memory such as a work RAM which is always provided in a game system. Both the control program and the game program can be executed without increasing the address space accessible by the PPU and without reducing the game program. As a result, when the control program is not copied to the work RAM, the CPU cannot simultaneously access both the control program and the game program allocated to the same address space of different banks, so that the CPU
When the user starts executing the game program, the control program instructing to start the execution of the game program becomes inaccessible and runaway can be prevented.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0009]

FIG. 1 is an external view showing an embodiment of the present invention. The game system 10 includes a cubic body 12,
A front panel 14 is formed on a front portion of the main body 12. The front panel 14 has a plurality of (in this embodiment, fifteen) slots 16 formed therein.
A multi-pin connector connected to the pins of the game cartridge 18 is provided. Therefore, these slots 1
6, the multi-pin connector allows the game cartridge 18 to be detachably mounted. In the vicinity of each slot, a light emitting diode (LED) for indicating that the game cartridge 18 is mounted in the slot 16 or whether the mounted game cartridge 18 is used or not is displayed.
20 are provided.

The front panel 14 is connected to controllers 20a and 20b used for playing a game and selecting a game cartridge 18 mounted in each slot 16, and for playing a shooting game. Are connected. The front panel 14 is further provided with a key switch 24 for selecting whether to enable or disable the game. The key switch 24 can be operated by inserting a key 26. Therefore,
When such a game system 10 is installed in a guest room such as a hotel, for example, the key 26 will be lent to the user at the hotel front desk in exchange for a usage fee.

On the front panel 14, a reset switch 28 and a TV /
A game switch 30 is provided. When the user is playing the game, the reset switch 28
Used to reset the game. The TV / game changeover switch 30 determines whether the TV receiver 32 used as a monitor receives a normal television broadcast or displays a game screen or a CATV screen using the TV receiver 32. This is a switch for switching.

The front panel 14 is further provided with an extension connector 34. The extension connector 34
It has the same function as the present family computer (trade name) expansion connector related to the manufacture and sale of the applicant,
For example, it is used to connect a joystick controller. Another slot 16a is provided inside the main body 12, and a monitor memory pack 18a having a system program or a control program is stored in this slot 16a. The memory pack 18a may have the same shape as the game cartridge 18 mounted in the other slots 16, and controls the entire system, for example, displays a demonstration screen or a menu screen, selects game software,
It controls connection to the CATV line and charging from the coin box.

A dip switch 38 is further provided in the main body 12. The dip switch 38 is constituted by 8 bits, and can be used for switching a billing method, setting a unit timer time according to a unit amount of inserted coins, and the like. As shown in FIG. 2, a power supply unit 42 is provided on a rear panel 40 of the game system 10.
The power supply unit 42 is provided on the rear panel 4.
0, so that it is detachably attached to the main body 12.

The power supply unit 42 is provided with an AC input connector 42a for connecting an AC power supply, and an AC output connector 42b for supplying power to other devices such as the monitor TV receiver 32 (FIG. 1). . Further, an extension I / O connector 43 is provided on the rear panel 40. The expansion I / O connector 43 is used as an input / output port when a modem or the like is connected.

The rear panel 40 is further connected to a monitor or a video output terminal 44 connectable to a video input terminal (not shown) of the TV receiver 32 and to an audio input terminal (not shown) of the TV receiver 32. A possible audio output terminal 46 is provided. If such a TV receiver 32 does not have a video input terminal or an audio input terminal, an RF output terminal 48 connected to its antenna terminal (not shown) is provided.
Further, an antenna input terminal 50 for connecting an antenna cable to the system 10 is provided on the rear panel 40. Both these terminals 48 and 50
An F-type plug is used.

Returning to FIG. 1, the system 10 is provided with a coin box 52 which is one of the billing methods, and a coin insertion slot 54 for inserting coins is formed in the coin box 52. . Therefore, the system of this embodiment can also be configured as a coin-timer control system that can play a game for a time corresponding to the amount of coins inserted into the coin box 52.

FIG. 3 is a block diagram showing the configuration of this embodiment. FIG. 3 is composed of the respective units of FIGS. 4 to 7.
Referring to FIG. 4, game system 10 includes one microprocessor or CPU 60. As the CPU 60, for example, an integrated circuit “2A03” manufactured by Nintendo can be used. The CPU 60 has a PPU (Picture Pr
The PPU 62 is an integrated circuit “2C02” manufactured by Nintendo, similar to the family computer (trade name). Details of the CPU 60 and the PPU 62 are described in
No. 118184. This CPU 60 and PP
U62 receives a signal from a common oscillator 64, for example, 21.4.
An 8 MHz clock is provided.

An 8-bit data bus 68 is connected to a data port of the CPU 60 through a bidirectional buffer 66, and 1-bit is connected to an address port through a one-way buffer 70.
A 6-bit address bus 72 is connected. Similarly, the data port of PPU 62 is
The address port is connected to a 6-bit address bus 80 through a one-way buffer 78. In addition, PPU
An address latch circuit 79 is provided in the data port of the PPU 62. The address latch circuit 79 latches address data output from the data port of the PPU 62 in a time-division manner, and together with 6 bits from the address port of the PPU 62, It is supplied to the one-way buffer 78 as 14-bit address data.

CP output through the address bus 72
The address data from U60 is supplied to address decoder 82.
Given to. This system is constituted by a so-called memory map system, and therefore, this address decoder 8 is used.
2 decodes a 5-bit address from the CPU 60 and outputs necessary chip enable signals CE0 to CE0, respectively.
CE8 is output. Further, the system clock φ2 from the CPU 60 is supplied to this address decoder 82 and also to another address decoder 84.
Similarly, the address decoder 84 converts necessary 4-bit address data into necessary chip enable signals CE9 to CE9.
CE11 is output.

Referring to FIGS. 4 and 5, a working RAM 86 is provided in association with CPU 60, and
A video RAM 88 is provided in association with the PU 62.
The working RAM 86 is enabled by a chip enable signal CE1 from the address decoder 82,
Address data is supplied from the CPU 60 through the address bus 72 and C
Data from the PU 60 is provided. Video RAM88
To the PPU 62 through the data bus 76 of the PPU 62
, And also the address data from PPU 62 through address bus 80. The most significant bit of the address bus 80 of the PPU 62 is provided through an inverter 90 as a chip enable signal of the video RAM 88. That is, when the most significant bit of the address bus 80 is "1",
Video RAM 88 is enabled.

Referring to FIGS. 4 and 5, both controllers 20a and 20b connected to main body 12
It is connected to a controller switching circuit 94 through I / O interfaces 92a and 92b. The controller switching circuit 94 is a circuit for switching which of the controllers 20a and 20b can be used as a main controller. In the embodiment, the controller 20a or 20b used to select the game cartridge 18 is used for the controller 20a or 20b. Is set as such a main controller. The I / O interfaces 92a and 92b for the controllers 20a and 20b
b are respectively enabled by a chip enable signal from a decoder built in the CPU 60. The controller switching circuit 94 is enabled by the chip enable signal CE4 from the address decoder 82. And the controller 20a
And 20b from the working R through a controller switching circuit 94 and a reset control circuit 96 via a data bus 100.
Stored in AM86 and used for game control.

The reset switch 28 provided on the front panel 14 is connected to a reset control circuit 96.
The reset control circuit 96 includes the controller switching circuit 9
4 is connected. The reset control circuit 96 turns on the key switch 24, turns on the reset switch 28, presses the reset switches (not shown) of the controllers 20a and 20b, or times out the preset timer 98. A reset signal is output to CPU 60 in response to one of the signals. Specifically, the reset control circuit 9
Reference numeral 6 includes a reset switch 28, a controller switching circuit 94, a circuit for selecting one of various reset signals from a preset timer 98 described later, and a flag for determining which reset signal has arrived and storing it. , Are enabled by a chip enable signal CE3 from the address decoder 82.

The preset timer 98 is used as a timer for presetting a time during which a game can be played in accordance with the amount of coins inserted into the coin box 52. Therefore, the preset timer 98 is
The working RA is provided by the 8-bit data bus 100.
It is connected to the coin selector interface 102 connected to the M86 and the coin box 52. The coin selector interface 102 is connected to the coin slot 54.
The type of coins inserted from FIG. 1 and the total number of coins for each type are provided to the working RAM 86 through the data bus 100.

The CPU 60 outputs an audio signal such as a necessary sound effect according to the progress of the game, and the audio signal is given to the AV / RF controller 104. The AV / RF controller 104 further includes:
The video signal from the PPU 62 is provided, and the AV / RF controller 104 turns on or off the audio signal and the video signal thus provided, and
The signal is given to the modulator 106. The RF modulator 106 has an AV / R
The combined audio signal and video signal from the F controller 104 are output, for example, as an NTSC television signal, that is, an RF signal. However, the audio signal and the video signal can be individually output as baseband signals from the RF modulator 106. The video signal from the RF modulator 106 is output from the video output terminal 44 shown in FIG. 2 and the audio signal is output from the audio output terminal 46. Similarly, the RF from the RF modulator 106
The signal, that is, the television signal, is output from the RF output terminal 48.

As shown in FIG. 1, a plurality of slots 16
(16 slots including the built-in slots 16a) are provided, and a game cartridge 18 is mounted in each of the slots 16. A plurality of game cartridges 18 and monitor memory pack 1 mounted in this manner
8a constitute one block by a predetermined number (four in this embodiment), and in this embodiment, 16 slots 1
6 (16a), four blocks B
LK0 to BLK3 are formed. Each block BLK0
BLK3 is composed of four banks BK0 to BK3, respectively, but has the same configuration. Therefore, in FIG. 6, only the block BLK0 is illustrated in detail as a representative of the others. However, it should be pointed out in advance that the blocks BLK1 to BLK3 have the same configuration.

The banks BK0 to BK3 of the blocks BLK0 to BLK3 are connected to the CPU 60 and the PPU 6
2 are connected in parallel so as to overlap in the same address space, but a bank (game cartridge 1) corresponding to one game software selected in the menu mode.
Only 8) is selectively activated. The program memory pack 18a mounted in one slot 16a included in the block BLK0 serves as a bank BK0, and the game cartridge 18 mounted in three slots 16
Are assigned as banks BK1 to BK3, and the respective game cartridges, ie, banks BK1 to BK3
Includes a program memory and a character memory. The blocks BLK0 to BLK3 are selected by the demultiplexer 108 for block selection, the program memory is selected by the demultiplexer 110, and the character memory is selected by the demultiplexer 112.

More specifically, 8-bit data is supplied from the CPU 60 to the output port 114 via the data bus 68. The output port 114 connects the blocks BLK0 to BLK3 and the banks BK0 to BK3 in accordance with the 8-bit data. And outputs 4-bit data. The demultiplexers 108 to 112 decode the 4-bit data supplied from the output port 114 in this way, and output a signal for selecting one of the blocks BLK0 to BLK3 and one of the banks BK0 to BK3. I do. For example, banks BK0 to BK3 of block BLK0 are enabled by select signals from demultiplexers 110 and 112.

Demultiplexer 108 for designating blocks
Are provided to a bus buffer 116 associated with each block. The bus buffer 116 includes a bidirectional buffer 118 for a program memory, an address one-way buffer 120 for a program memory, a bidirectional buffer 122 for a character memory, and an address one-way buffer 12 for a character memory.
4 inclusive. Of the 4-bit select signal from the demultiplexer 108, two bits are supplied to the bus buffer 116, one bit of which enables the bidirectional buffer 118, and the other bit enables the bidirectional buffer 122, respectively.

The bidirectional buffer 118 for the program memory is connected to the data bus 68 of the CPU 60.
The bidirectional buffer 122 for character memory is PPU6
2 data buses. Similarly, address one-way buffers 120 and 124 are connected to address bus 72 of CPU 60 and address bus 80 of PPU 62, respectively.

An expansion box interface 126 is connected to the expansion multi-pin connector 34 shown in FIG. 1. In this embodiment, a CATV interface 128 is provided to enable connection with a CATV system. Extended Box Interface 126 and CAT
V interface 128 receives chip enable signals CE10 and CE from address decoder 84, respectively.
11 enabled.

The I / O provided on the rear panel 40
The expansion I / O port 130 is connected to the connector 42c, and the expansion I / O port 130 is enabled by a chip enable signal CE8 from the address decoder 82. Next, the operation or operation of this embodiment will be described with reference to FIGS. 1 to 3 and FIGS. 4 to 7 based on FIGS.

The flowcharts shown in FIGS. 8 and 9 are started each time a reset signal is supplied from the reset control circuit 96 to the CPU 60. That is, the key switch 24
(FIG. 1) is turned on by the key 26 or a reset switch (not shown) of the controller 20a or 20b.
Is operated, the reset switch 28 of the main body is turned on, or the time-up signal from the preset timer 98 is given, and the reset control circuit 9
6 gives a reset signal to the CPU 60. Accordingly, C
The PU 60 outputs a signal to the address decoder 82 in the first step S1, and this address decoder 82
The reset control circuit 96 is disabled by setting the chip enable signal CE1 from “0” to “0”. Therefore, at this point, the reset signal from the reset control circuit 96 is prohibited.

In the next step S3, CPU 60 and PPU 62 are set to the initial state. That is,
The registers and ports related to the CPU 60 and the PPU 62 are set from an undefined state to a cleared state. In the next step S5, the CPU 60 determines the type of the triggered reset signal. The reset signals from the controllers 20a and 20b, the reset switch 28 and the preset timer 98 are determined as "Hot" reset, and the reset signal by turning on the key switch 24 is determined as "Cold" reset. In order to determine the type of the signal in step S5, the reset control circuit 96 may output a flag indicating the type of the reset signal together with the reset signal in accordance with the type of the signal that has been triggered.

In step S5, when it is detected that the "Cold" reset, that is, the reset by turning on the key switch 24, in the next step S7,
The CPU 60 disables the preset timer 98 through the address decoder 84. That is, in this step S7, the CPU 60 prohibits the reset from the preset timer 98.

Thereafter, in step S9, the CPU 6
0 gives a signal to the address decoder 82 and sets the chip enable signal CE1 to “1” to make the working RAM 86
And outputs “0” to the data bus 68 through the bidirectional buffer 66 to
86, a predetermined area “0000H to 1FFFH” is cleared. In the next step S11, the CPU 60
Initializes related registers and input / output ports.

In step S 13, the PPU 62 enables the video RAM 88 by supplying data to the address bus 80 through the one-way buffer 78, and the data bus 7 through the bidirectional buffer 74.
6 outputs "0" to this video RAM.
Clear 88. In step S15, the CPU 6
0 initializes each memory. Then, in step S17, the CPU 60 sets the working RAM 86
And an area in which a control code is stored, that is, an S-RAM control area. Specifically, the CPU 60 sets the chip enable signal CE1 to “1” through the address decoder 82 to enable the working RAM 86, and the address bus 72 through the one-way buffer 70.
And outputs the address for the corresponding area. Thereby, the S-RAM control area of the working RAM 86 is enabled.

In the following step S19, the CPU 60
Transfers the control program stored in the monitor memory pack 18a (FIG. 1), that is, the program of the bank BK0, to another address space. That is, the banks BK0 to BK15 shown in FIGS.
Since all of them are allocated to the same address space, the control program cannot be kept in the same address space as the game cartridge 18, so that the S-
The control program of the monitor memory pack 18a of the bank BK0 is transferred to the RAM control area.

In step S21, the CPU 60
“Check-Sum” is checked according to the control program transferred to the S-RAM control area. That is, all the data of the game cartridges of the banks BK1 to BK15 are totaled, and the totaled result is checked, whereby the banks BK1 to BK1 are checked.
It is determined whether the game cartridge assigned to No. 5 is mounted or removed, or whether the game cartridge is genuine or unauthorized. Specifically, the CPU 60 controls the address decoder 8
2 to enable the output port 114 by setting the chip enable signal CE5 to “1”, and by sequentially setting numerical values from “0001” to “0FFF” through the bidirectional buffer 66 and the data bus 68, The game cartridges 18 mounted on the cartridges 16, that is, the banks BK1 to BK15 are sequentially selected. Then, the program data and character data from these banks BK1 to BK15 are stored in the working RAM 86 through the bidirectional buffer 118 and the data bus 68, and the CPU 60 accesses all the game cartridges by accessing the area of the working RAM 86. 18 or bank BK
1 to BK15 are added. This step S21
In this embodiment, it is possible to determine whether a proper game cartridge is mounted in each slot 16 or the like.

Further, "Check-Su" in step S21 is executed.
m ", the game title of the game cartridge 18 installed in each slot can be checked in step S23. That is, if the game cartridge is a pre-registered game cartridge, it can be used as a result of this" Check-Sum ". The name of the game is known, and in the case of an unregistered game cartridge, the name of the game can be determined by checking a specific code in the game cartridge.

Thereafter, in step S25, the CPU
60 sets a "Hot" start flag formed in a predetermined area of the working RAM 86, and
Attraction mode shown in FIG. In the attraction mode, the TV receiver 32 (FIG. 1) is used to display, for example, information on hotels and inns where the TV receiver 32 is installed, and to repeat demonstrations of game contents set in the system. This is the mode to be performed.

On the other hand, in the previous step S5, "Ho
If it is determined that the t "is reset, steps S29 and S31 are executed to clear the predetermined area of the working RAM 86 and the video RAM 88 in the same manner as in the previous steps S9 and S13. , The CPU 60
By looking at the flag input from the reset control circuit 96, whether the "Hot" reset is from the reset switch 28 of the front panel 14, from the preset timer 98, or the controller 20a or 20b To determine if they are from. Then, the reset switch 2 on the front panel 14
If it is determined that the reset signal is from 8,
The process proceeds to the attraction mode shown in step S27. That is, the CPU 60 sets the reset switch 28
Alternatively, when a hardware reset signal is given from the preset timer 98, the bank BK0 of the block BLK0 is always selected and the program of the monitor memory pack 18a is executed. Is selected, one of the banks other than the bank BK0 of the block BLK0 is selected, the program of the corresponding game cartridge 18 is executed, and the controller 20a
Alternatively, when the reset switch 20b is operated, the program execution is started again from the head address of the previously selected game cartridge 18.

The reset switch 2 on the front panel 14
If it is determined that the reset signal is not the reset signal from
In the next step S35, the PU 60 checks the state or mode of the controller 20a or 20b. That is, the controller 20a or 20b may be pressed even during the execution of a normal game, and is also used to select the game cartridge 18 mounted in each slot 16, so that the CPU 60 executes this step S35. , The controller 20a or 20b
Is determined in which mode is operated, and which corresponding program is executed is determined.

If it is determined in step S35 that the controllers 20a and 20b have been pressed in the reset mode, the process proceeds to a menu mode for selecting a game cartridge in the next step S37. Conversely, if the controller 20a or 20b has been operated during the normal game play, in step S39, the CPU 60 determines whether the game was being demonstrated or the game was being played. This can be easily determined by checking the flags set in the working RAM 86. Then, if the reset signal from the preset timer 98 is given during the demonstration of the game, the process proceeds to step S27, and the attraction mode is executed. Further, if the reset signal from the preset timer 98 is given during the game play, in the next step S43, the time-up by the preset timer 98 is displayed, and step S43 is executed.
Proceed to 27.

Referring to FIG. 10, in first step S101 of the attraction mode, CPU 60 displays the attraction mode. That is, this step S
In 101, information on a hotel in which the system is installed is displayed on a monitor or a screen of the TV receiver 32. This is executed by cooperation between the CPU 60 and the PPU 62. Specifically, like the family computer (product name), the monitor memory pack 18a
An audio signal is output from the CPU 60 and a video signal is output from the PPU 62 based on the data from FIG. These two signals are the AV / RF controller 104
To the RF modulator 106. Then, such a guidance display can be performed by supplying the signal from the RF modulator 106 to the monitor, that is, the television receiver 32.

Then, in the next step S103,
The CPU 60 supplies a black screen display command signal to the PPU 62 to turn off the screen of the monitor 32. Next step S1
05, as in step S15 of FIG.
The PU 60 enables the S-RAM control area of the working RAM 86.

Then, in the next step S107,
The CPU 60 checks the next bank number, that is, the number of the current game, based on the data from the game cartridge 18 supplied from the data bus 68. In the next step S109, the program of the monitor memory pack 18a is transferred to the S-RAM control area of the working RAM 86 in the same manner as in step S17 of FIG.

Thereafter, the CPU 60 executes steps S111 and S11 for the S-RAM control area.
3. In S115 and S117, respective flags or data are set. More specifically, in step S111, the next bank number checked in step S107 is set in the S-RAM control area. In step S113, C
The PU 60 gives data to the S-RAM control area, and in the reset control circuit 96, the controller 2
Set 0a and 20b to reset mode. In step S115, the CPU 60 sets a flag indicating that the game is being demonstrated, that is, a game demonstration flag in a predetermined area of the S-RAM control area. Then, in step S117, the CPU 60 presets time data in the preset timer 98 according to the amount of coins inserted into the coin box 52, and then enters a game demonstration mode. In other words, the state is reset by software, the program jumps to the reset area of the game cartridge of the bank number set in step S111, and the game using the game cartridge is started.

The menu display mode will be described with reference to FIG. First step S201 in this mode
At the same time, the menu is displayed on the screen of the monitor 32 by the cooperation of the CPU 60 and the PPU 62, and the next bank number, that is, the number of the current game is checked in the same manner as in the previous step S107 (FIG. 10).

Steps S203, S205 and S20
7 correspond to steps S103 and S105 in FIG. 10, respectively.
And S109, and a duplicate description is omitted here. Then, the S-RAM of the working RAM 86
In step S209, the number of the game cartridge to be set next, that is, the bank number is set in the control area in the same manner as in step S111. In step S211, the CPU 60 sets the controllers 20a and 20b to the control mode, that is, the program mode. In step S213, the CPU 60 sets a flag indicating that the game is being played, that is, a game play flag, in a predetermined area of the working RAM 86. Thereafter, in step S215, the reset control circuit 96
, And the CPU 60 allows a reset input from the reset switch 28 of the front panel 14.
Then, a time corresponding to the amount of coins inserted into the coin box 52 is preset in the preset timer 98, and the mode shifts to the game play mode.

It should be noted that there are three charging methods in this system: a CATV method, a key method, and a coin method. In the CATV system, the CPU 60 supplies a signal to the address decoder 80 and outputs a chip enable signal C
The CATV interface 128 is enabled by setting E11 to “1”. A CATV provided in a hotel or the like is provided through the interface 128.
The line and the system 10 are connected. And TV
By operating the / game changeover switch 30, the game mode is set. Next, the monitor, that is, the TV receiver 32
To an appropriate empty channel. In that state,
A game demonstration screen and an operation procedure screen are displayed in the attraction mode shown in FIG. When any key of the controller 20a or 20b is operated, the first mode is performed. In this state, by operating a select button (not shown) provided on the controller 20a or 20b, the first mode is set. A game cartridge, that is, a game program assigned to one of the banks BK1 to BK15 is selected. Then, the game is started by pressing the start button of the controller 20a or 20b. At this point, a charge may be made. Thereafter, when the game is over, the TV / game switch 30 is operated to set the TV reception mode.

In the key system, a key switch 26 is lent to a user at the front of a hotel where the system 10 is installed. In this case, a fixed fee may be charged at this time. Thereafter, the TV / game changeover switch 30 is operated to switch to the game mode, and the monitor, that is, the TV receiver 32 is set to an appropriate empty channel. Then, the demo screen and the operation procedure are displayed, and in this state, if the key lent from the front is turned after being inserted into the key switch 24, the game is enabled. And the controllers 20a and 20
b, the game is selected and started in the same manner as in the previous CATV system, and when the game is over,
The user operates the TV / game changeover switch 30 to set the TV reception mode.

In the coin system, the game mode is switched by operating the TV / game changeover switch 30, and the TV receiver 32 is set to an empty channel. In this state, the user inserts certain coins into the coin insertion slot 54 of the coin box 52. Then, the coin selector interface 102 connected to the coin box 52
Preset timer 98 according to the input amount data from
Is set to the game time. And controller 2
The game cartridge is selected by 0a or 20b, and the game is started. When a time corresponding to the coin insertion amount has elapsed, the preset timer 98
The game is terminated by the time-up signal from. Thereafter, the TV / game changeover switch 30 is used to set the TV reception mode.

When the coin mode as described above is used, the coin box 52 may be configured to be shared as a coin timer of a TV receiver provided in a current hotel room. Further, a remote control function can be configured using this system. For example, CATV interface 1
28, through a CATV line such as a hotel,
The charge calculation could be performed in the working area of the PU 60, or the system could be turned on or off, including the TV receiver 32 as a monitor.

It is also possible to exchange arbitrary game software data between the front and the room, for example, using the AC power supply line. If the history data using this system is left in the working RAM 86 of this system so that it can be accessed from the front, the amount of coins inserted can also be confirmed.

In the above-described embodiment, the memory cartridge 18 is mounted from the outside of the main body 12 in order to facilitate the exchange of the game software. Although the menu is selected by the controller 20a or 20b, another selection switch may be provided.

[Brief description of the drawings]

FIG. 1 is a front external view showing an embodiment of the present invention.

FIG. 2 is a rear external view of the embodiment.

FIG. 3 is a block diagram showing the configuration of this embodiment.

FIG. 4 is a block diagram showing a detail of FIG. 4 in FIG. 3;

FIG. 5 is a block diagram showing a detail of FIG. 5 in FIG. 3;

FIG. 6 is a block diagram showing a detail of FIG. 6 in FIG. 3;

FIG. 7 is a block diagram showing a detail of FIG. 7 in FIG. 3;

FIG. 8 is a flowchart showing the operation of the embodiment.

FIG. 9 is a flowchart showing an operation following the flowchart in FIG. 8;

FIG. 10 is a flowchart showing an operation in an attraction mode.

FIG. 11 is a flowchart showing an operation in a menu display mode.

[Explanation of symbols]

 10 Game System 16, 16a Slot 18a Monitor Memory Pack 18 Game Cartridge 20a, 20b Game Controller 24 Key Switch 26 Key 28 Reset Switch 32 TV Receiver 60 CPU 62 PPU 82, 84 Address decoder 96 Reset control circuit 98 Preset timer 108, 110, 112 Demultiplexer

Claims (1)

(57) [Claims] 1. A game system connected to a monitor for displaying a game image on the monitor, the game system having at least a first address space and a second address space, and displaying an image for a game. And a processing means for controlling game start, a game program storing a game program arranged in the first address space and displayed by the processing means to display an image for a game on the monitor. Storage means; a read / write readable memory comprising a memory readable and writable arranged in the second address space; and a game provided by being arranged in the first address space and executed by the processing means. A control program for controlling start and execution of the control program by the processing means. System program storage means for storing a copy program for copying at least a part of the roll program to the readable / writable memory arranged in the second address space, a first program for playing a game by an operation of a player
Operating means, and second operating means to which an instruction to start the game program is inputted by an operation of a player, wherein the processing means is capable of reading and writing at least a part of the control program based on the copying program. The control program is copied to a memory, the copied control program is executed, the start control of the game program is performed based on an operation of the second operation means by a player, and the game image is displayed on the monitor based on the execution of the game program. And changing the display state in response to the first operation means.