JP2568340B2 - Writing method of MOS PROM - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device capable of obtaining a high operation speed and a method of manufacturing the same.

(Prior Art) As a conventional writable read-only memory element having a MOS type structure, there is a transistor composed of a drain terminal 1, a source terminal 2, a control gate terminal 3 and a floating gate 4, as shown in FIG. . This transistor applies a high voltage to the drain terminal 1,
When the source terminal 2 is set to a ground potential or a voltage near the same, the control gate terminal 3 is set to a high voltage, and the floating gate 4 is set in a floating state, a desired voltage is induced on the floating gate 4. The thermoelectrons are injected and accumulated in the floating gate 4 from the inverted inversion electron flow (channel), whereby
By utilizing the fact that the threshold voltage of this transistor as viewed from the control gate terminal 3 is increased, the written state and the non-written state are distinguished. In this element structure, the injected thermoelectrons can be emitted from the floating gate 4 by irradiating light, and thus have an erasable structure. When a semiconductor integrated circuit is realized by using this element structure, most of the readout methods use the drain terminal 1 according to the charge stored in the floating gate 4.
-Reading the stored information "1" to "0" by detecting the magnitude of the current flowing between the source terminals 2. In FIG. 8, 5 is a gate insulating film, 6 is an insulating film, 7 is an intermediate insulating film, 8 is a metal layer, 9 is a substrate, and 10 is a protective film.

(Problems to be solved by the invention) However, in this element structure, V _cc +5 V is applied using the control gate terminal 3 as a control terminal at the time of reading. There is a disadvantage that the transconductance g _m between the control gate terminal 3 as viewed from the drain terminal 1 source terminal 2 is not so large for such a stacked gate structure. That the transconductance g _m can not be obtained so large, it does not take a large value of current flowing between the drain terminal 1 source terminal 2, than those using a floating gate 4 as a control terminal of the transistor in reading, detection It takes time and it doesn't get faster. For example, when reading is performed with the floating gate 4, the readout time is about 2 ns, whereas when the control gate terminal 3 is used as the control electrode, the readout time is 3 ns. On the other hand, SSD8
As described in 3-66 “Dielectric strength of thin silicon thermal oxide film” (Technical Research Report of the Institute of Telecommunications Society of Japan), the dielectric strength of a thin silicon thermal oxide film is significantly dependent on film thickness.
It is known that the breakdown voltage distribution is improved by improving the film quality. An object of the present invention is to provide a semiconductor integrated circuit device capable of obtaining a high operation speed as a writable semiconductor memory device (MOS PROM) and a method of manufacturing the same.

(Means for Solving the Problems) The gist of the present invention is that M
In an OS transistor, an insulating film that completely breaks down electrically at a voltage lower than the junction withstand voltage of a MOS transistor is provided over an impurity region forming a drain or a source by using a gate as a control line, and via the insulating film , A conductor different from the gate.

(Operation) In this way, a writable read-only memory element is obtained, the operating speed is increased, the power consumption is increased and the integration is increased, and the written information is not changed by ultraviolet rays or radiation.

(Embodiments) Embodiments of a semiconductor integrated circuit device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.
FIG. 1 is a sectional view showing the configuration of an embodiment of the semiconductor integrated circuit device of the present invention. In FIG. 1, several Ωcm
In the substrate 11 of P-type ~20Ωcm resistivity drain 12 and source 13 are ion implantation, etc., is made of N-type, the first gate insulating film 14 (SiO ₂ film having a thickness of several hundred Å thermally grown Formation) and the second gate insulating film 15 (SiO ₂
The film is formed by thermal growth). The thickness of the second gate insulating film 15 is about half or less, that is, 100
An insulating film 16 (formed of a SiO ₂ film by thermal growth) having a thickness of about 200 ° is formed on the drain 12. Also,
Conductive polycrystalline silicon 17 on first gate insulating film 14
(Thousands of square meters) are formed. On the second gate insulating film 15 and the insulating film 16, a conductive polycrystalline silicon 20 having a thickness of several thousand Å is formed. Conductive polycrystalline silicon 1
On the layers 7 and 20, an intermediate insulating film 18 is formed. This intermediate insulating film 18 is made 8000 to 1000 by PSG.
It is formed to a thickness of 0 °. Aluminum 19 is deposited so as to be in contact with intermediate insulating film 18 and conductive polycrystalline silicon 20.
And thus the enhancement type M
An OS type transistor is configured. FIGS. 2 (a) to 2 (g) show a method of manufacturing this MOS transistor.
Is shown in First, as shown in FIG. 2 (a), after forming a first gate insulating film 14 (several hundred Å) on a substrate 11,
The conductive polycrystalline silicon 17 is formed (several thousand Å) to form the first
Form a gate. Next, as shown in FIG. 2B, a diffusion layer of the drain 12 and the source 13 is formed on the substrate 11 by ion implantation. Next, as shown in FIG. 2 (c), the entire surface is thermally oxidized to form
It is formed to a thickness of 00 to 800 mm. Next, FIG. 2 (d)
As shown in (1), the second gate insulating film 15 in the region where the second gate electrode is to be formed is opened by etching using a first contact mask (not shown) to partially expose the drain 12. Next, as shown in FIG. 2 (e), a thin oxide film (100 to 200 °) is formed by thermal oxidation on the portion opened by etching to form an insulating film 16. Next, as shown in FIG. 2 (f), a conductive polycrystalline silicon 20 is grown to several thousand degrees by vapor phase growth. Next, the second
As shown in FIG. 2G, a second gate mask is used to form a second gate mask.
Unnecessary portions of the gate insulating film 15 and the conductive polycrystalline silicon 20 are removed. As a result, an electrode of polycrystalline silicon 20 is formed, and insulating film 16 is formed below conductive polycrystalline silicon 20. Thereafter, as shown in FIG. 1, the intermediate insulating film 18,
By forming aluminum 19 as a second contact metal electrode and finally forming a protective film 21, the semiconductor integrated circuit device shown in FIG. 1 is completed. Next, a first storage method in the semiconductor integrated circuit device shown in FIG. 1 will be described. Applying an appropriate voltage between the voltage V _pp (later described) from the supply voltage and grounding the source 13 to the conductive polysilicon 17 serving as a first gate, the voltage V _pp may electrically break the insulating film _16, for example 10 When ２５25 V is applied to aluminum 19 as a metal electrode, the channel below the first gate is in a strong inversion state, and this voltage is
It is applied to the conductive polycrystalline silicon 20, the thin insulating film 16, the drain 12, the channel under the conductive polycrystalline silicon 17 which is the first gate, and the source 13. Then, the thin insulating film 16 is electrically broken down, and the drain 12 and the conductive polycrystalline silicon 20 are brought into conduction. On the other hand, substrate 1
When the first and source 13 are grounded and the conductive polycrystalline silicon 17 is grounded, the source 13 and the drain 12 become non-conductive. When the voltage _Vpp is applied to the aluminum 19 in this state, the drain 12 is in a floating state, and the potential of the drain 12 is equal to the junction capacitance _Cj of the drain 12 and the total capacitance C of the insulating films 15 and 16 on the drain 12. _OXT Becomes If manufacturing conditions are selected such that the total capacitance C _OXT is several times to several tens times the junction capacitance C _j , the drain 12-
The potential difference between the conductive polycrystalline silicon 20 becomes several volts or less, and the insulating film 16 is not broken. FIG. 3 shows this state, in which the total capacitance C _OXT and the junction capacitance C _j are connected in series between the voltage V _pp and the ground, and a potential V _OXT is generated at both ends of the junction capacitance C _j . . The total capacitance C _OXT is a capacitance using the insulating films 15 and 16 between the drain 12 and the conductive polycrystalline silicon 20 as a dielectric. The junction capacitance _Cj is the junction capacitance between the drain 12 and the substrate 11. The total capacitance C _OXT is 2 PF, and the junction capacitance C _j is 0.2 P
F, the insulating film 16 is broken down at about 10 V in the case of a thickness of 100 °. Therefore, if the thickness of the insulating film 16 is set to 200 °, dielectric breakdown occurs at about 20V. On the other hand, the voltage applied to the insulating film is It is. Therefore, the voltage applied to the total capacitance C _OXT is about V _pp −V _OXT = 1V, and the thin insulating film 1
No destruction of 6. As is apparent from the above description, the conductive polycrystalline silicon 17 is grounded or an appropriate voltage from the power supply voltage to _Vpp is applied to the conductive polycrystalline silicon 17 and the aluminum 19 is grounded or the voltage V is applied to the aluminum 19. By applying _pp , the insulation film 16 is broken,
Since a destructible state can be created, this element can have a writing function. When reading stored information, conductive polycrystalline silicon 1 as a first gate
By raising the voltage 7 to the power supply voltage or its vicinity, "1" to "0" of the stored information is determined by whether the steady current flows depending on whether the thin oxide film 16 is broken between the aluminum 19 and the source 13. Can be detected. In this structure it is possible to the control terminal of the conductive polycrystalline silicon 17 at the time of reading, it is possible to increase the mutual conductance g _m between conductive polycrystalline silicon 17 as viewed from the drain 12 and the source 13. Further, since the state of the stored information “1” to “0” is determined depending on whether or not the insulating film 16 is broken, once the insulating film is broken, the stored information does not change. That is, it is possible to prevent changes in stored information due to ultraviolet rays or radiation. That is, P
It functions as a ROM. Therefore, the stored contents cannot be rewritten. Next, in the structure of FIG.
Will be described. A major difference between the first storage method and the second storage method is whether or not the transistor is irradiated with light during storage. The conductive polycrystalline silicon 20 is applied with a potential V _pp (10 to 25 V) in a state where the transistor is irradiated with light.
When the source 13 is set at a potential of V _pp −several volts (about 5 to 20 V) and the conductive polycrystalline silicon 17 is set at the ground potential, the drain 12 is in a floating state. 11 increases the leakage current,
When the substrate 11 is grounded, the voltage of the drain 12 becomes close to the ground potential, and the potential difference between the drain 12 and the conductive polycrystalline silicon 20 increases, so that the insulating film 16 is broken. On the other hand, in a state where the transistor is irradiated with light, a potential _Vpp is applied to the aluminum 19 and the source 13 is set to ( _Vpp−
The potential of the conductive polycrystalline silicon 17 is also set to ( _Vpp -several volts). As a result, the source 13 and the drain 12 are turned on and become conductive. At this time, the drain 12 has a threshold voltage of V _{pp -several} volts-transistor, and the potential difference between the drain 12 and the conductive polycrystalline silicon 20 becomes small.
Is not destroyed. Aluminum 19 when reading stored information
And applying a power supply voltage or a voltage in the vicinity thereof to the conductive polycrystalline silicon 17 to detect whether or not a steady current flows between the aluminum 19 and the source 13. Reads the stored information. FIG. 4 is a sectional view showing the configuration of the second embodiment of the present invention. In FIG. 1, a thin insulating film 16 is formed on the drain 12.
And a conductive polycrystalline silicon 20 as a second gate. In FIG. 4, a thin insulating film 16 and a conductive polycrystalline silicon 20 as a second gate are provided on the source 13. Further, in the embodiment of FIG. 1, conductive polycrystalline silicon 20 and aluminum 19 are connected by through holes, whereas in the embodiment of FIG. 4, conductive polycrystalline silicon 20 and aluminum 19 are connected. There are no through holes to connect. 4 and FIG. 1, the same portions are denoted by the same reference numerals and have the same meaning. Next, a first storage method in the embodiment of FIG. 4 will be described. When the conductive polycrystalline silicon 20 is grounded and a voltage _Vpp is applied to the conductive polycrystalline silicon 17 and aluminum 19, the source 1
3 is _Vpp- the threshold voltage of the transistor (1 to
The _{2V) V TE.} Pre _{V pp} by voltage V _pp -V _TE to a voltage value such as the insulating film 16 may be destroyed
If (10-25 V) is set, the source 13 and the conductive polycrystalline silicon 20 enter a conductive state due to the breakdown of the insulating film 16. On the other hand, the substrate 11, a conductive polysilicon 20,17 and the ground potential, when a potential is applied _{V pp} aluminum 19, the source 13 is in a floating state, the substrate 1
Since source 1 and conductive polycrystalline silicon 20 are at the ground potential, source 13 is also at the ground potential, and insulating film 16 is not destroyed. That is, by grounding conductive polycrystalline silicon 17 or applying potential _Vpp to aluminum 19,
Also, the potential V _pp is applied to the aluminum 19 from the ground or the aluminum 19.
By applying a voltage, a destruction or non-destruction state of the insulating film 16 can be created, so that this element can be provided with a storage function. When reading stored information, the substrate 11 and the conductive polycrystalline silicon 20 are grounded, and the aluminum 19
A suitable voltage may be applied to the conductive polycrystalline silicon 17 to make it a power supply voltage or a voltage close to the power supply voltage, and whether or not a steady current flows between the aluminum 19 and the conductive polycrystalline silicon 20 may be detected. Next, a second storage method of the element shown in FIG. 4 will be described. When a potential _Vpp is applied to the conductive polycrystalline silicon 20, the conductive polycrystalline silicon 17 is set to an appropriate voltage between the power supply voltage and the potential _Vpp , the drain 12 is set to the ground potential, and the substrate 11 is grounded. Since the potential difference between the conductive polycrystalline silicon 20 becomes the potential _Vpp , the insulating film 16 is broken. When the insulating film 16 is not broken, the conductive polycrystalline silicon 20 is set at the potential _Vpp , the conductive polycrystalline silicon 17 is set at the ground potential, and the drain
Between the potential _Vpp and the ground potential, or the conductive polycrystalline silicon 20 is set to the potential _Vpp ,
A conductive polycrystalline silicon 17 as a suitable voltage between the electric potential V _pp from the power supply voltage, V _pp to the drain 12 _- applying a voltage of several volts. At the time of reading, the substrate 11 and the conductive polycrystalline silicon 20 are grounded, an appropriate voltage is applied to the aluminum 19, and the conductive polycrystalline silicon 17 is set to a power supply voltage or a voltage in the vicinity of the power supply. It is detected whether or not a steady current flows between the polysilicons 20. Several examples have been described above, and FIG. 5 will be considered as an example of an integrated circuit using this element structure. The column selection lines B1, B2,... BN in FIG.
FIG. 4 corresponds to the aluminum 19 in FIG. Also, the row selection line W
1, W2... WM correspond to the conductive polycrystalline silicon 17 as the first gate in FIG. 1 and FIG. Further, V is a ground potential, and corresponds to the source 13 in FIG. 1 and the conductive polycrystalline silicon 20 in FIG. In FIG. 5,
Some of the storage schemes described above can be applied.
The row selection lines W1, W2... WM in FIG.
It is assumed that only books have a high (“H”) level.
The “H” level is a voltage equal to or higher than the threshold voltage of the enhancement MOS transistors T ₁₁ and T ₁₂ to T _MN , and the voltage lower than that is a low (L) level. Also, it is assumed that only one of the column selection lines B1 to BN is at the H level similarly to the row selection line. Also, enhancement type MOS
Transistor _{T 11} is the above-mentioned transistor, Q
₁₁ is a thin insulating film. As an example, the first storage method described in FIG. 1 is applied to FIG. Now, the row selection line W
Select 1 and column select line B1, and applying a suitable voltage between the power supply voltage to the row select line W1 to V _pp, the column select line B
Applying a _V pp _(10~25V) to 1, an enhancement-type MOS transistor _{T 11} is because the ON state, the potential difference of the insulating film _{Q 11} is _{V pp} becomes insulating film _{Q 11}
Is destroyed. At this time, since the BN from the column select line B2, and WM is the row selection line W2 is "L" level, _{Q 1N} is not destroyed from the _{Q M1} and the insulating film _{Q 12} from the insulating film _{Q 21.} Then the row selection lines W1 to "1", when the row select line W2 to "H", since the insulating film Q ₁₁ but is destroyed enhancement type MOS transistor T ₁₁ is turned off, the enhancement type MOS current from the column select line B1 through the transistor T ₁₁ to the ground V does not flow. Therefore, V across the dielectric film _{Q 21}
takes voltage _pp, insulating film _{Q 21} is destroyed. Hereinafter, an arbitrary row selection line and column selection line can be selected in the same manner, and the insulating film existing at the intersection can be destroyed. Therefore, a writable integrated circuit can be manufactured using this element. At the time of reading, when an arbitrary row selection line and a column selection line are set to “H” level, the element whose insulating film has been destroyed has a steady current of 0.1 mA from the column selection line B1 toward the source power supply voltage V. Although the current flows to the extent, the element whose insulating film is not broken does not flow (in the order of nA), so that the difference can be detected and the stored information can be read. As described above, the embodiment in which the storage integrated circuit is constituted by using the elements of the semiconductor integrated circuit device of the present invention has been described. However, it is easily analogized that some other storage methods can be similarly applied with a slight modification. You can do it. As described above, the present invention can be used for a writable read-only memory element in a MOS structure and a method for manufacturing the same. An advantage over the conventional device is that the first gate can be used for controlling and reading, so that the second gate can be used for controlling and reading, and the transconductance g _m is higher than that of the device using for controlling reading.
Can be increased, so that it is possible to increase the speed and to obtain the following advantages.

(1) Since writing is performed by the impossible destruction method, the written information does not change due to ultraviolet rays or radiation as compared with an element whose stored information changes due to light irradiation.

(2) Low power consumption and higher integration can be achieved than a junction-breakdown writable read-only memory element having a bipolar structure.

(3) In the MOS structure, the density can be further increased as compared with an element for storing information depending on whether or not a resistive element is thermally destroyed, that is, a so-called fuse-type writable read-only storage element. This is because the element can perform writing and reading with one high-resistance conductor and one transistor, whereas the present invention can realize the same function with the element area of one transistor. is there. In addition, some of the storage systems in the structures of FIGS. 1 and 4 will be described, and other systems can be considered with some modifications. However, they can be easily inferred from the above-mentioned method. Next, in the device structure shown in FIGS. 1 and 4, a manufacturing method that can further simplify the process steps and reduce the device area will be described with reference to FIGS.
This will be described with reference to the process diagram of FIG. FIG. 7 shows an element structure manufactured by the manufacturing method shown in FIGS. 6 (a) to 6 (e). The same reference numerals in FIG. 7 denote the same parts as those in FIG. In FIG. 7, as shown in FIG. 6 (a), a first gate insulating film 14 and a conductive polycrystalline silicon 17 are formed on a P-type substrate 11 in a thickness of several hundreds of .ANG. Form a gate. Next, as shown in FIG. 6B, a second gate insulating film 15 and a thin insulating film 16 are simultaneously formed. This second
The gate insulating film 15 and the thin insulating film 16 are formed by thermally oxidizing the entire surface in an oxidizing atmosphere. In this case, the thicknesses b and c of the second gate insulating film 15 on the conductive polycrystalline silicon 17 are 300 with respect to the insulating film thickness a (100 °) on the P-type substrate.
It is formed to a thickness of about Å. The reason is due to the difference in the oxidation rate of the silicon on the conductive polycrystalline silicon 17 and the silicon on the substrate 11. Thereafter, as shown in FIG. 6C, an N-type impurity is ion-implanted into the substrate 11 through the thin insulating film 16 to form the source 13 and the drain 12. Next, as shown in FIG. 6 (d), a conductive polycrystalline silicon 20 is formed to a thickness of several thousand 気 相 over the entire surface by vapor phase growth. Next, as shown in FIG. 6E, unnecessary portions of the second gate insulating film 15, the thin insulating film 16, and the conductive polycrystalline silicon 20 are removed by etching using a second gate mask. next,
As shown in FIG. 7, an intermediate insulating film 18 is formed on the entire surface,
A through hole is formed at a location of conductive polycrystalline silicon 20, and aluminum 19 is formed thereon. The aluminum 19 and the conductive polycrystalline silicon 20 are in contact through a through hole. Finally, a protective film 21 is deposited on the upper surface of the aluminum 19. The manufacturing method described in FIGS. 6A to 6E is different from the manufacturing method in FIGS. 2A to 2G immediately after the formation of the second gate insulating film 15. That is, the source 13 and the drain 12 are formed by ion implantation. When the silicon oxide film is grown on a P-type impurity substrate and when grown on polycrystalline silicon, the growth rate of the latter is generally about three times faster. Therefore, the oxide film thickness is 100 ° on a P-type substrate, while the oxide film thickness is 300 ° on polycrystalline silicon. By using the steps shown in FIGS. 6 (a) to 6 (e), this phenomenon can be utilized, so that the thin insulating film 16 on the drain 12 and the conductive polycrystalline silicon 17-conductive polycrystalline silicon 17 When the second gate insulating film 15 of crystalline silicon 20 is grown simultaneously, the latter can be three times thicker. Therefore, the withstand voltage of the insulating film is also different (about three times), and only the thin insulating film 16 between the conductive polycrystalline silicon 20 and the drain 12 can be broken. In addition, in the conventional method, an etching mask was required to form a thin insulating film, whereas the second gate insulating film 15 on the drain 12 and the conductive polycrystalline silicon 17-conductive polycrystalline Since the second gate insulating film 15 between the silicon 20 can be grown simultaneously, an etching mask is not required. As a result, a mask for forming the thin insulating film 16 in the steps of FIGS. 2A to 2G becomes unnecessary, and a margin for mask alignment is not required. It becomes possible to make it smaller than about ² to ²⁰ μ2.
This is because it is not necessary to provide a mask allowance of 1 to 2 μm for forming the thin insulating film 16 in FIGS. 2 (a) to 2 (g).

(Effects of the Invention) As described above, the present invention uses a gate as a control line, and forms an insulating film which is completely destroyed on an impurity region forming a drain or a source at a voltage lower than the junction breakdown voltage of a MOS transistor. Since a film is provided and a conductor different from the gate is provided through this insulating film, a writable read-only memory element can be obtained, and the operation speed can be increased, and low power consumption and high integration can be achieved. In addition, there is an advantage that written information is not changed by ultraviolet rays and radiation.

[Brief description of the drawings]

FIG. 1 is a sectional view of an embodiment of a semiconductor integrated circuit device according to the present invention, and FIGS. 2 (a) to 2 (g) are steps for explaining a method of manufacturing the semiconductor integrated circuit device of FIG. FIG. 3 is a view for explaining a state in which a thin insulating film in the semiconductor integrated circuit device of FIG. 1 is broken, and FIG. 4 is a cross section of a second embodiment of the semiconductor integrated circuit device of the present invention. FIGS. 5A and 5B are diagrams for explaining a writing function by forming an integrated circuit using the semiconductor integrated circuit devices of FIGS. 1 and 4, and FIGS. 6A to 6E show the present invention. FIG. 7 is a process explanatory view for explaining a method of manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention. FIG. 7 is a cross-sectional view of the third embodiment of the semiconductor integrated circuit device of the present invention. It is sectional drawing of a semiconductor integrated circuit device. 11 ... substrate, 12 ... drain, 13 ... source, 14 ... first gate insulating film, 15 ... second gate insulating film, 16 ... thin insulating film, 17 ... conductive polycrystalline silicon, 18 ... intermediate insulating film, 19 ... Aluminum, 20 ... conductive polycrystalline silicon, 21
…Protective film.

Claims (1)

(57) [Claims] 1. The gate, drain and source of a first conductor
Impurity region and one of the drain and source impurities
A second conductor disposed on the region with an insulating film interposed therebetween.
MOS transistor, wherein the second conductor and the second conductor
Between MOS transistors and the other impurity region
Between the drain and the substrate of the MOS transistor.
Is the same as applying a voltage lower than the junction withstand voltage of the source region.
Sometimes, light is irradiated to cause electrical insulation breakdown of the insulating film.
MOS type P characterized by writing more stored information
ROM writing method.