JP2568172B2 - Image information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information processing apparatus having a mask processing function, and more particularly to an image information processing apparatus that performs mask processing on a plurality of images. .

[Related Art] Generally, when performing image editing, it is often desired to mask a part of image data and cut out only a part of the image. In addition, the shape of this cutout is often a complicated shape other than a rectangle or a regular polygon. In such a case, as a method often performed conventionally, a cutout (mask) has a bit map memory, and depending on the contents of this bit map memory. There is a method of selecting the data to be extracted or the data to be discarded and performing the desired cutout selection.

In the method of masking the image data with the data from the mask bit map memory, only the data in a desired area is extracted from one image and the result is often written in a specified memory. Moreover, this memory is generally a bit map memory that stores image data binarized by the dither method, the density pattern method or the like. This is because when handling high resolution images, the cost of the memory for storing the image data is significantly reduced.

In such a method, when a plurality of masked images are combined in a specified memory, each image is sequentially overwritten in the memory and a priority is given to image data to be written later. FIGS. 2 (a) and 2 (b) show a combination of an image A masked in a circular shape and an image B masked in a heart shape for simplicity in this explanatory view. As a result of creating the image of A in the memory first and then synthesizing the image of B, the overlapped part of both is added to the image of B which was carried out later as shown in FIG. The processed image B is prioritized as. This is because the image data in the memory has already been binarized by the dither method or the like, and the original data of the overlapping image portion of the A image has been lost, so the process of prioritizing the A image becomes impossible. Is.

On the other hand, as shown in FIG. 2 (b), there is a demand to perform a portion c where both images are overlapped (that is, a watermark) so that the images of both are overlapped, but such a method is impossible with the above-mentioned conventional method. Is.

Further, when handling a high-resolution image, the capacity of the bit map memory for masking becomes large, resulting in a cost increase. Further, when the image is enlarged after the cutout processing by masking, there is a problem that the oblique edge of the mask becomes jagged.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-described conventional example, and independently cuts out a plurality of mutually different input images in arbitrary shapes, and cuts out the plurality of cut-out images. An object of the present invention is to provide an image information processing apparatus capable of diversifying processing functions when performing composition processing.

Another object of the present invention is to provide an image information processing device capable of smoothing mask information.

[Means for Solving Problems] In order to achieve the above object, the image information processing apparatus of the present invention has the following configuration. That is, an input unit (corresponding to a TV camera, a CCD sensor, or the like in the embodiment) for inputting first and second image data representing respectively different first and second images, and the first and second images. Area data generation means (corresponding to the mask memory 3 in the embodiment) for generating first and second area data for independently cutting out the first and second area data, and a first area represented by the first and second area data. And a detection means for detecting the overlapping portion of the second area (in the embodiment,
AND circuit 44) and the first and second area data using the first and second area data.
And a synthesizing means for synthesizing the first and second images in accordance with a signal (in the embodiment, the output signal 64 of the bit synthesizer 46) indicating the processing content in the overlapping portion detected by the detecting means. (Corresponding to the image processing circuit 7 in the embodiment).

[Embodiment] An image information processing apparatus according to an embodiment of the present invention shown in FIG. 1 includes a mask memory 3 as a mask information storage unit, a mask processing circuit 6 as a mask information conversion unit, a mask unit and a combining unit. Image processing circuit 7 of FIG.

In the configuration shown in FIG. 1, the bit synthesizer 4 creates image information of 10 bits by adding mask information of 2 bits to the input image information. The image information is enlarged / reduced by the scaling processing circuit 5. On the other hand, the 2-bit mask information is converted by the mask processing circuit 6 for smoothing. In the image processing circuit 7, according to the mask information from the mask processing circuit 6, mask processing is performed on a plurality of images, images are selectively output, and a plurality of images are combined.
Image information is stored in the bit map memory 9 through the binarization circuit 8.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Block Diagram of Image Information Processing Apparatus (FIG. 1)] FIG. 1 is a block diagram of the image information processing apparatus of the present invention. The image data 1 is, for example, a TV camera or
It is 8-bit data obtained by A / D converting the time-series image data read from the CCD sensor or the like. Such image data 1
Are sequentially input as raster image data 2, and are combined by a bit combiner 4 with the output of 2 bits from the mask memory 3 to form 10-bit data as shown in FIG.

In FIG. 1, the numbers on the line indicate the number of bits of data.

4 (a) and 4 (b) are views showing an example of the contents of the mask memory 3, in which the heart-shaped inside 60 is all 1's and the shaded area 61 is all 0's. Figure 4 (a)
Indicates the mask information of normal N _X × N _Y pixels, and FIG. 4 (b)
Shows a case where the mask information of FIG. 4 (a) is thinned out in 1 / k in the X and y directions, and the memory capacity is 1 / k ² times that of FIG. 4 (a).

The timing for fetching data from the mask memory 3 is
Since it is thinned out to 1 / k in each of the x and y directions, it is performed in k × k pixel units of image data. The content of the mask memory 3 is composed of 0 or 1. When 0, the extraction of the image data is prohibited (writing is prohibited to the bit map memory 8 which will be described later), and when it is 1, write permission to the bit map memory 8 is permitted. means.

The raster image data 2 and the mask data are 10 bit data in which the mask data is written in the uppermost 2 bits as shown in FIG. 3 by the bit synthesizer 4 as described above. One mask data is repeatedly added to the image data.

The bit-combined image data 10 is subjected to image scaling, that is, conversion such as enlargement and reduction, in the scaling processing circuit 5 in the subsequent stage. Explaining the case of image enlargement,
For example, in the case of enlarging vertically and horizontally three times, if one pixel of image data output in raster form is continuously output with the same data for three pixels in the main scanning direction and the same line data is output for three lines in the sub-scanning direction. good. Therefore, the output of image data can be paused line by line.

After the scaling processing is performed by the scaling processing circuit 2, the mask data of 2 bits of the image data of 10 bits is used in the mask processing circuit 6 for the smoothing processing of the mask edges, and the rough edges of the image cause the jagged edges of the image. Is smoothed. After that, the image processing circuit 7 performs watermark processing or the like on the overlapping portion between the two masks. Thereafter, the binarization circuit 8 binarizes the image data by a dither method or the like, and stores the result in the bit map memory 9.

[Description of Mask Memory Configuration (FIGS. 5A and 5B)] FIG. 5A shows a mask memory 3 having two mask data consisting of a mask A and a mask B. Although each has a bit map memory structure having a depth of 1 bit, it is more convenient to code it as shown in FIG. 5 (b) and treat it as a 2 bit mask memory in consideration of an overlapping image. That is, as shown in FIG. 5B, mask data: 0
0 (write protected to memory), 01 (only image B), 10
Code information (image A only) and 11 (watermarks of images A and B) are assigned.

[Explanation of Mask Smoothing Circuit (FIGS. 6 (a), (b), 7 (a), (b))] FIGS. 6 (a), (b) are block diagrams of the mask smoothing circuit. Here, for simplicity, the case where the mask data is one bit will be described.

The image data 24 input in FIG. 6 (a) is delayed by one line by the shift registers 23a and 23b, and mask information of three lines is simultaneously output. The output of each line is delayed by the 1-pixel delay elements 22a to 22f. Accordingly, the image data in the 3 × 3 matrix is simultaneously taken out from the taps 21a to 21i.

FIG. 6 (b) is a block diagram of conversion of the above-mentioned 3 × 3 mask data 21a to 21i generated based on one-bit mask data.

The nine mask data 21a to 21i are added by the adder 30,
It is output as 4-bit data 31 having a range of 0-9. The added data 31 is compared with a certain threshold value data 33 by the comparator 32 in the next stage, binarized, and output as data 34. The threshold data 33 can be appropriately set by a manual or the like. (By changing the threshold value data 33, the smoothing characteristic is somewhat changed.) As a result, the binarized output 34 is obtained.

FIG. 7 (a) shows the state before the mask processing when the mask data is one bit, and FIG. 7 (b) shows the mask data after the processing.

In FIG. 7 (a), the shaded portion shows 0 (that is, the portion to be masked), and in reality, we would like to expect a 45 ° diagonal mask along the line 70, but rough mask data or zooming (magnifying), etc. As a result, the eyes of the mask are enlarged and roughened as shown in the figure.

FIG. 7 (b) is a diagram showing the result of performing the processing, and each numerical value shows the addition result 31 of the mask data in the 3 × 3 matrix. Now, if the threshold value data 33 is selected to be 5 and it is determined that data ≧ 5 → output = 1 data <5 → output = 0, the shaded area in FIG. 7 (b) is 0.
Becomes As a result, the diagonal edge portion becomes closer to the line 70 and becomes a more natural smoothed portion, so that the boundary of the masked and extracted image can be seen smoothly.

Although the 3 × 3 matrix has been described in the present embodiment, the smoothing action can be further increased by using a larger matrix if there are no restrictions such as hardware.

[Description of Other Matrices (FIGS. 8A to 8C)] FIG. 8A is a diagram showing an example of a 5 × 5 matrix. Each element of this matrix is added with a weight of 1 (all equally). For this reason, the added result becomes a 6-bit value from 0 to 25, and it is necessary to design the circuit in the subsequent stage accordingly.

FIG. 8 (b) is an example of an averaging matrix in which weights are placed on 3 × 3 center pixels, and the averaging scan is performed with emphasis on the center value.

FIG. 8 (c) is a diagram showing an example of the averaging matrix in the case of not being a square. As described above, if the averaging matrix is made larger, the smoothing action becomes larger, but the line memory (or shift register), etc. The number of parts is large and the cost is considerably high. On the other hand, using a matrix having a large dimension only in the main scanning (horizontal horizontal) direction shown in this figure has an advantage that the hardware cost can be reduced by adding, for example, a delay element in the main scanning direction.

[Explanation of Mask Processing Circuit 6 (FIG. 9)] FIG. 9 is a block diagram of the mask processing circuit 6 of the present embodiment, showing the case where the mask data is 2 bits.

Since the mask data is 2 bits, 00,01,
It can take four states of 10,11. Now this is the top bit,
When divided into lower bits, only the upper bits have a mask area of image A, and only the lower bits have a mask area of image B. FIG. 9 shows that such two mask areas are smoothed simultaneously. In this circuit, the mask data of the upper 2 bits of the image data of 10 bits are separated by the mask data separation circuit 41, and the MSB and LSB of the mask data of 2 bits are smoothed by the mask smoothing circuits 43a and 43b of the next stage. Be converted. This mask smoothing circuit 4
The circuits 3a and 43b are the same as the one-bit mask smoothing circuit shown in FIGS. 6 (a) and 6 (b).

One of the two smoothed mask data 62, 63 is selected by the selector 45. This selection is made by the select signal 47. On the other hand, the overlapping portion of the two masks is detected by the AND circuit 44, the output of the selector 45 and the AND circuit 44 are combined by the bit combiner 46, and the converted mask data 64 of 2 bits is converted again.

The bit synthesizer 46 determines whether the one bit mask data from the selector 45 or the output from the AND circuit 44 is to be the MSB depending on the image A or the image B by the select signal 47. To do. For this reason, the bit combiner 46 includes a decoder. Thereafter, the bit synthesizer 47 adds the image data to the lower 8 bits to obtain the image data 50 of 10 bits.

[Explanation of Block Diagram of Image Processing Circuit (FIG. 10)] FIG. 10 shows the details of the image processing circuit 7 and the connection with subsequent circuits.

The 10-bit image data 50 is again separated into the 2-bit mask data 65 and the 8-bit image data 66, and the image data 66 is input to the selector 51. In the selector 51, when the mask data 65 of the first image A is 10 and the mask data 65 is 10,
That is, when there is no overlap, X is selected by the signal 67 from the decoder 57a. In the case of 11 indicating that the mask data 65 overlap, Y is selected and the image data 66 is output to the buffer memory 52. At this time, the decoder 57b outputs the R / W signal
Setting 68 to LOW instructs writing to the buffer memory 52. In the subsequent selector 54, the mask data 65 is 10
, The signal 69 from the decoder 57c selects X,
The input image data is output to the binarization circuit 8 in the next stage. When the mask data 65 is 11, the input X of the selector 54,
Neither Y nor Z is selected and no output is made to the binarization circuit 8.

Next, in the case of the second image B, when the mask data is 01, X is selected by the selectors 51 and 54 and the image data 66 is stored in the bit map memory 9 through the binarizing circuit 8. When the mask data 65 is 11, the selectors 51 and 54 select X and Y, respectively, and at the same time, the R / W signal 68 of the buffer memory 52 is set to HIGH, and the area of the previously stored image A (see FIG. b)
The area 11) in is read.

The image data passing through the X side of the selector 51 and the two data from the buffer memory 52 are added by the adder 53a and then halved by the divider 53b to average the two data. (This only needs to be shifted by one bit.) This data is inputted to Y of the selector 54, inputted to the binarization circuit 8 through the selector 54, binarized and stored in the bit map memory 9. The above is summarized in the following table.

The decoders 57a to 57d use the mask data (2 bits) and the select signal 47 to select the selectors 51 and 54 and the buffer memory 5.
2. Create a control signal for controlling the bit map memory 9. The select signal 47 is, for example, a 1-bit signal which becomes LOW level for the first image data and HIGH level for the second image data.

In the present embodiment, the order of the first and second images may be reversed. At this time, the first mask data
When 65 is 11, writing to the buffer memory 52 is performed, and at the second time, reading from the buffer memory 52 and averaging operation are performed in the same manner.

Furthermore, by setting the mask data 65 of the overlapping portion to a value other than 11, for example, selecting the Z input of the selector 54 and outputting the output of the buffer memory 52 to the binarization circuit 8 allows the corresponding priority image to be embedded. You can

[Effects of the Invention] As described above, according to the present invention, a plurality of input images that are different from each other are independently cut out in arbitrary shapes, and a processing function when performing a combining process on a plurality of cut out images is provided. There is an effect that can be diversified.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of the image information processing apparatus of this embodiment, FIGS. 2A and 2B are diagrams showing an example of a mask image, and FIG. 3 is an example of image data to which mask information is added. 4 (a) and 4 (b) are diagrams showing an example of the contents of the mask memory, FIGS. 5 (a) and 5 (b) are diagrams showing an example of the configuration of the mask memory, and FIGS. 6 (a) and 6 (b). ) Is a block diagram of the mask smoothing circuit, FIGS. 7A and 7B are diagrams for explaining the smoothing process, FIGS. 8A to 8C are diagrams showing an example of a matrix, and FIG. FIG. 10 is a block diagram of the mask processing circuit, and FIG. 10 is a block diagram of the image processing circuit. In the figure, 3 ... Mask memory, 4 ... Bit synthesizer, 5 ...
… Scaling circuit, 6 …… Mask processing circuit, 7 …… Image processing circuit, 8 …… Binarization circuit, 9 …… Bitmap memory, 23
a, 23b …… Shift register, 30 …… Adder, 32 …… Comparator, 33 …… Threshold data, 41 …… Mask data separation circuit, 45,51,54 …… Selector, 47 …… Select signal, 52
... buffer memory, 57a-57d ... decoder.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-58-217076 (JP, A) JP-A-52-106625 (JP, A) JP-A-50-122832 (JP, A) JP-A-57- 142092 (JP, A) JP 61-80466 (JP, A) JP 59-170959 (JP, A)

Claims (2)

(57) [Claims] 1. Input means for inputting first and second image data representing respectively different first and second images, and a first for independently cutting out the first and second images. And area data generating means for generating second area data, detection means for detecting an overlapping portion of the first and second areas represented by the first and second area data, and the first and second areas. A synthesizing unit for slicing the first and second images using the second area data, and synthesizing the first and second images in accordance with a signal instructing the processing content in the overlapping portion detected by the detecting unit. An image information processing apparatus comprising: 2. The image information processing apparatus according to claim 1, further comprising smoothing means for smoothing the first and second area data.