JPS6180466A - Image operator - Google Patents

Abstract

PURPOSE:To attain the selection of an arithmetic function obtained from the binary image data with addition and replacement of a small number of circuit parts and to simplify the circuit constitution, by providing a register file, an arithmetic logical operation unit and a control circuit. CONSTITUTION:Either one of 3-state buffers 33 and 34 within a register file 30 is selected by the control signal sent from a control circuit 40. A function designating signal S is applied to an arithmetic logical operation unit 12. The unit 12 receives the 1st and 2nd variable density image data at inputs A and B and performs the arithmetic processing of both data with a function designated by the signal S. The result of this arithmetic processing is delivered as the processed image data. When either one of both image data is extracted as the output image data, the (output F=input A) or (output F=input B) is designated by the signal S for the unit 12. Thus an image is selected and delivered as the 3rd variable density image data. In other words, an arithmetic function obtained by the binary image data can be selected with addition and replacement of a small number of circuit parts.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a paralysis device that is capable of switching performance performance according to binary image data.

(Prior Art) In some cases, one data is selected from two false images according to the area indicated by the binary image, and one 'a gray and white image is combined. Image processing units used for such purposes have conventionally been constructed by separately adding a multiplexer (MIJX) in addition to hardware represented by an arithmetic and logic unit (ALU) that can perform arithmetic and logic operations. .

FIG. 3 is a block diagram illustrating an embodiment of a conventional ammunition weapon. The image arithmetic unit 10 includes a multiplexer 11
．． Arithmetic logic unit 12. It is composed of a function designation register 13 and a 3-state buffer 14. The first and second grayscale images are transmitted through multiplexer 1 and gtJf V
It is commonly input to the li logic operation unit 12. That is, the 10'a light and dark image is input to the multiplexer 11 and the arithmetic and logic unit 12, and the second gray and dark image is input to the B input of the multiplexer 11 and the arithmetic and logic unit 12, respectively. The multiplexer 11 selects and outputs either the human input or the B input under the two-dimensional image selection signal SL. And that appearance] t&
fi (enable or disable) can be switched by a separately input mode signal.

The arithmetic and logic unit 12 has first and second shading li.
! Upon receiving the ii image data, various types of arithmetic processing are performed, and the type of the arithmetic operation is designated by a function designation signal @S from the function designation register 13. The output F of the arithmetic and logic unit 12 is outputted to the outside via a three-state buffer 14 whose output state is controlled by a mode signal. Multiplexer 11 and logical operation unit 12
The outputs of the two are commonly connected, and either one specified by the mode becomes processed II light image data.

(Problem to be solved by the invention) As mentioned above, according to the area indicated by the binary image,
When synthesizing one grayscale image by transporting one of two rounds of grayscale image data, conventionally, input selection means such as a multiplexer is required in addition to the hardware that implements the function represented by the arithmetic and logic unit. It had to be set up separately. In this way, in order to switch the function of the image arithmetic unit according to the 21-direction image data, it is necessary to add additional single-function hardware such as a multiplexer, making the circuit configuration complicated.

The present invention has been made with these points in mind, and its purpose is to realize an image arithmetic unit having a simple configuration and having the same functions as conventional image arithmetic units.

(Means for Solving the Problems) The present invention for solving the problems described above includes an arithmetic and logic operation unit that receives first and second image data and performs enclosing processing on the image data according to a predetermined functional relationship. , a register file that specifies input/output functions of the arithmetic and logic unit, and a logic circuit that receives binary image data and other control signals and specifies registers of the register file, and outputs an image from the arithmetic and logic unit. It is characterized in that it is configured to obtain data.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 3 are designated by the same numbers.

In the figure, 30 is a register file that provides a function designation signal S for designating a function to the arithmetic and logic unit 12;
Reference numeral 40 denotes a control circuit that receives binary image data, a mode signal, and a function signal Fn, and provides a control null signal to the register file 30. Fengjutsu logical performance n unit 12.
The register file 30 and the control circuit 40 constitute an image arithmetic unit 20.

The register file 30 includes first and second function registers 31, 32 . 3-state buffer 33.3 receiving the outputs of these function registers 31.32
It is composed of 4. 3 state buffer 33.34
The outputs of the two are commonly connected, and one of them is selected by the control 2B signal from the control circuit 40 and given to the arithmetic and logic unit 12 as a function designation signal S.

The control circuit 40 includes an AND gate 41.2111 that receives 2111 image data and a mode signal. It is comprised of an AND gate 42 that receives the function signal Fn and the mode signal, and an OR gate 43 that receives the outputs of these gates 41 and 42. Then, the output of the OR gate 43 is output to the control circuit 4.
The output will be 0. The operation of the circuit configured as described above will be explained as follows.

In the normal image processing mode, the arithmetic and logic unit 12 receives first and second grayscale image data at inputs A and B, performs arithmetic processing on both signals using a function specified by the specified signal S, and processes the signals. Output the results as processed image data. Here, the first and second grayscale image data correspond to, for example, image data stored in an image memory or image data obtained by A/D converting a video signal from a television camera. The power of the arithmetic and logic unit 12 is displayed, for example, on the CRT display [2]. In this mode, the select signal SLT is ignored and the function is fixed to either F uncl or l'' unc2 according to the function signal Fn.

On the other hand, the first and second i! When one of the light and light image data is extracted as output image data, the arithmetic and logic operation unit 12 may be operated as F-A or F=B using the function designation signal S. The first and second grayscale image data, output image data, and 2IITI image data are synchronized with the pixel clock, and the first and second grayscale image data are sequentially input to the arithmetic and logic unit 12, and each pixel clock 2 The function is F according to the fft image signal.
=A or F=B and the arithmetic logic unit 12
performs image selection. The result of the arithmetic processing is output as third grayscale image data.

Next, the operation of the register file 3o and the control circuit 40 will be explained. The designation signal S is applied to two data registers 31.3 in the register file 30 written in advance.
This is either one of the data in Func2 (Func1, Func2). Now, consider the case where the mode signal input to the control circuit 40 is °○''. At this time, the AND gate 42 is closed, so only binary image data is input.

When the binary image data is 0'°, the output of the OR gate 43 becomes 0'', the 3-state buffer 33 is enabled (the 3-state buffer 34 is disabled), and the data in the register 31 F uncl becomes the designated signal S. On the other hand, when the binary image data is 1'', the output of the A gate 43 becomes 1'', and the 3-state buffer 34 becomes enabled (the 3-state buffer 33 is in the disable state). ), data Fu of register 32
nc2 becomes the designation signal S.

On the other hand, when the mode signal is "1", the AND gate 42
, and the designated signal S becomes Funcl in response to "ON" and "1°" of the function signal Fn.

1" unc2. For example, when embedding the second image data in the first image data, F unc
It is sufficient to set l-A, Func2=B, and switch the function using binary image data. The binary image at this time indicates the embedding area with data ``1''.

In the above explanation, an arithmetic and logic unit is used as a two-manpower, one-output image processing circuit, but as shown in FIG. By converting the data through the LUT 50 and applying the converted data to the B input of the arithmetic and logic unit 12, it is possible to further increase the functionality. As LUT50, RO
It can be realized by M or RAM. In addition, LUT
The number of pages, 50, is designated using the page designation register 51. Each page of UT50 has a constant multiplication, absolute (
Conversion data corresponding to an arbitrary function such as direct or square is prepared in advance.

(Effects of the Invention) As explained in detail above, according to the present invention, the image calculation circuit is integrated into one, and the functions are switched according to the contents of the register file. This makes it possible to select the desired length by adding or replacing a few circuit parts, and it is possible to realize an image processing unit with a simple circuit configuration as a whole.

Further, according to the present invention, any function of the image calculation circuit can be selected, and the number of functions that can be selected in a binary image can be increased.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram showing another embodiment of the present invention, and FIG. 3 is a diagram showing an example of a conventional circuit. 10.20... Image calculator 11... Multiplexer 12... Arithmetic logic unit 13.31.32.51... Register 14.33.3
4...3 state buffer 3o...register file 4o...control circuit 41.42...AND gate 43...OR gate 50...LUT patent applicant Yokogawa Hokushinden Corporation Agent Person Patent Attorney Nobuo Ozawa Sukenuma Figure 1 Figure 2 Figure 1 Li Figure 3

Claims (1)

[Claims] an arithmetic and logic unit that receives first and second image data and performs arithmetic processing on the image data according to a predetermined functional relationship; a register file that specifies input/output functions of the arithmetic and logic unit; An image arithmetic unit comprising a logic circuit that receives image data and other control signals and specifies registers of the register file, and is configured to obtain output image data from the arithmetic and logic unit.