JP2560757B2 - Display data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention performs image display processing based on command data that defines display processing, and particularly adopts a method of storing input command data in a temporary buffer. Display processing device.

[Conventional technology]

Display processing devices that use a CRT display as a display device and display information such as sentences, figures, and images stored in a memory (for example, a refresh memory using a dynamic memory) include personal computers, word processors, and captain systems. As a new media-related device, it has spread to general households, and it is becoming more and more important as a man-machine interface including business-related fields such as OA devices. At the same time, display processing is becoming more sophisticated and diversified. Therefore, by receiving the data instructing the display process sent from the central processing unit or the external input device and efficiently performing the display process such as the control of the display timing and the operation of the display memory according to the instruction, It is becoming more important to disperse the system and improve the processing capacity of the entire system.

FIG. 6 is a block diagram showing a portion related to data input / output processing of a conventional display processing apparatus, and its operation will be described below.

The device shown in FIG. 6 includes a photo interface control unit 200,
It is composed of a processing execution unit 57 and an internal memory 58.

The photo interface control unit 200 includes data (hereinafter, referred to as a command) for directing display processing directly sent from a central processing unit (hereinafter, referred to as a host processor) or an external input device, or unprocessed variable data (hereinafter, referred to as a parameter). ) Is temporarily stored, an output data buffer register 51 for temporarily storing the data executed and processed based on a command, and passing the photo processor to the data buffer register by the write and read control signals 59, 60. It is composed of an input / output control circuit 53 for controlling the writing and reading operations of, and a status register 54. The status register 54 operates in conjunction with various states relating to display timing, such as the vertical blanking period state and the state of inputting a detection signal by the light pen, and the storage state of the data buffer register, and causes the host processor to display the internal state of the display processing device. Is a register for informing.

When the host processor reads the data in the output data buffer register 51, or when the host processor writes the command or parameter in the input data buffer register 52, the input / output control circuit 53 outputs the input / output interrupt signal.
61 is activated and supplied to the processing execution unit 57. When the processing execution unit 57 detects the occurrence of the input / output interrupt signal 61, the processing execution unit 57 stores the command or parameter input to the input data buffer register 52 in the input / output data storage area 55, or outputs the data in the input / output data storage area 55. Performs an interrupt process for outputting to the output data buffer register 51.

The processing execution unit 57 also reads and interprets commands and parameters input from the host processor from the input data storage area 55, and executes display processing according to each command such as display timing control and display memory rewriting.

The input / output data storage area 55 sequentially stores the commands input to the input data buffer register 52, and temporarily stores the data processed by the process execution unit 57 based on the command to the output data buffer register 51. It is a first-in first-out buffer (hereinafter referred to as FIFO format) buffer, and the write or read address is controlled by the pointer register 56. Input / output data storage area
55 is assigned to the internal memory 58 together with the pointer register 56.

In general, the data buffer register has a capacity of only about 1 byte, and in a device that does not have a FIFO format buffer, the process execution unit 57 interprets a previously input command, and when it is in process, , The host processor cannot continuously input the next command, and the process execution unit 57
Must finish the command processing, retrieve the command from the input data buffer, wait until the input data buffer is empty, and then input the next command. For this reason, as described above, the input / output data storage area 55 is provided in the internal memory 58, and the data input from the host processor is immediately taken from the input data buffer and temporarily stored and stored in time series in advance. By sequentially reading the commands from the area, the host processor can continuously input the next command without waiting for the completion of the command processing of the processing execution unit. By inputting a command in this way, the command input speed of the host processor is high, and even if the command processing of the processing execution unit is slow, if the command and parameter of the number of bytes for the input data storage area It is possible to input without waiting for command processing.

[Problems to be solved by the invention]

In recent years, there is a tendency for display processing to become more sophisticated and diversified, and accordingly, commands for instructing display processing are also required to have high functionality. As commands become more sophisticated, it is required to start processing immediately after input from the host processor, such as when issuing commands at timings according to the display state or when it is necessary to give priority to commands. There is a need for a command to be performed (hereinafter referred to as an emergency command).

The command issued at a timing corresponding to the display state includes, for example, a command for starting a process for generating the detected position information immediately after the detection signal by the light pen is detected, and an adverse effect on the display signal generation. In order to avoid this, there is a command that causes the display state to be changed every time the display timing changes to the vertical blanking period state. In the case of the above command, the host processor checks the status indicating the internal state of the display processing device,
It is necessary to start the process immediately after the command is input in order to take the procedure of inputting the command at the timing when a certain specific state is reached.

In addition, as a command having a high priority, there is a command having a function of invalidating an already input command, which is used when the program of the host processor is debugged.
In this case, it is required to perform the processing prior to the other command processing already input.

However, in the above-described conventional display processing device, the input / output data storage area 55 is provided, and as a FIFO format buffer,
Since the timing difference between the command input from the host processor and the command reception of the process execution unit and the command execution process is absorbed, the process execution unit 57 receives the input command after the host processor inputs the command. Even if the host processor reads the contents of the status register 54 to detect the internal state of the processing device and then inputs the target command at a desired timing, the processing will be executed because the time elapses before the processing is started. The department may still be processing other previously entered commands, that is, it may not process them. Therefore, inconvenience has arisen such that the target command may be interpreted or broadcast at a timing different from the timing expected by the host processor.

An object of the present invention is to eliminate the above-mentioned drawbacks when controlling the processing of commands and parameters written from the host processor using the FIFO type buffer,
An object of the present invention is to provide a display data processing device capable of executing processing of an urgent command input later, prior to a command already input and stored in a FIFO format input buffer.

[Differences from the Prior Art of the Invention]

In the conventional display processing device described above, the processing execution unit has conventionally received the commands stored in the input / output data storage area of the FIFO format in the order in which they were stored. On the other hand, according to the present invention, a flag register for determining whether or not the command input from the host processor is a command to be urgently processed is provided, and the processing execution unit starts command processing based on the value of the flag register. The original content is such that the execution of an emergency command input later is preferentially started by selecting the command to be executed before making a decision.

[Means for solving problems]

A display data processing device of the present invention includes a display memory for storing display information, a display timing generating circuit for generating display timing and horizontal and vertical synchronizing signals of a CRT display, and displaying the display information based on the display timing. A display device comprising a video signal generator for sending to a CRT display as data, which sequentially reads display information stored in the display memory and displays it on a CRT,
Storage means for temporarily storing command data input from an external processing device and instructing display processing, and a processing execution unit for reading command data from the storage means and executing display processing according to the command data. A determining means for determining whether the command data is command data to be urgently processed,
It has a flag register that can be read by the processing execution unit that stores the determined result, and a unit that selects command data to be executed by the processing execution unit from the storage unit in accordance with the value of the flag register. This makes it possible to start the processing of a command with a high degree of urgency input later, before the command already input to the storage means.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block configuration diagram of a display processing device according to a first embodiment of the present invention. In the apparatus shown in FIG. 1, the process execution unit 7 controls the operation of the entire system via an internal system bus by a program provided inside and process data stored in an internal memory 8. Further, it interfaces with a host processor or an external input device via the host interface control unit 100, and manipulates the display data stored in the display memory 32 via the display timing generation circuit 31 to perform desired CRT display and various types of display. It realizes the processing function. The display timing generation circuit 31 generates an address for the display memory 32 in synchronization with the display timing generated by itself and reads the display data. The read display data is parallel-serial converted by the video signal generating circuit 33 and supplied to the CRT 34 as a serial video signal. Further, the display timing generation circuit 31 activates the detection signal 40 when detecting that the light pen input signal 38 is input by the light pen 35, and activates the vertical blanking period signal 39 when the vertical blanking period is reached. To do. These signals and other signals indicating the internal state of the display processing device are input to the status register 4.

The host interface control unit 100 is a host processor, or an input data buffer register 2 for temporarily storing commands or parameters directly sent from an external input device, temporarily storing data executed and processed based on commands, and Output data buffer register 1 to be passed to and write and read control signals 9 and 10
And an input / output control circuit 3 for controlling writing and reading operations to and from the data buffer register, and a display timing state such as a vertical blanking period state and an input state of a detection signal by a light pen, or a storage state of the data buffer register. The status register 4 operates in conjunction with the host processor to inform the host processor of the internal state of the display processor.

When data is read from the output data buffer register 1 of the host processor or a command is written to the input data buffer register 2 of the host processor, the input / output control circuit 3 activates the input / output interrupt signal 11 and the process execution unit 7 Supply to. When the processing execution unit 7 detects the occurrence of the input / output interrupt signal 11, the processing execution unit 7 stores the command or parameter input to the input data buffer register 2 in the input / output data storage area 5, or the data in the input / output data storage area 5 is stored. Performs an interrupt process for outputting to the output data buffer register 4. This interrupt processing is performed prior to the interpretation and execution of commands and parameters.

Further, the processing execution unit 7 reads and interprets commands and parameters input from the host processor from the input data storage area 5 or the input data buffer register 2, and responds to each command such as display timing control and display memory rewriting. Display processing is executed.

The emergency command determination flag register 12 is a flag register that indicates that the host processor has input a command to be processed with priority over an already input command, and can be read and written by the processing execution unit 7. When a command is input to the input data buffer resist 2, at the same time, an identification bit indicating whether or not there is an emergency command is latched in the emergency command determination flag register 12. When an urgent command, that is, a command whose identification bit is "1" is input, the determination flag is set to "1". Emergency command input signal when the judgment flag is set
Activate 13. The urgent command input signal 13 is supplied to the input / output control circuit 3, and in the activated state, the input / output control circuit 3 inhibits data writing to the input data buffer register 2 subsequently generated from the host processor. When the determination flag is reset, the input / output control circuit 3 enables writing from the host processor to the input data buffer register 2.

The input / output data storage area 5 sequentially stores the commands input to the input data buffer register 2, and temporarily stores the data processed by the processing execution unit 7 based on the command to the output data buffer register 1. It is a FIFO type buffer to be stored, and the write address and the read address are controlled by the pointer register 6.

Here, a process (command input process) of temporarily storing data from the input data buffer register 2 in the input data storage area 5 and reading from the area each time command processing is performed will be described with reference to FIG.

The input data storage area 5 is defined by a storage area start address pointer (hereinafter referred to as ISP) and a storage area end address pointer (hereinafter referred to as IEP) where data can be stored. An input / output interrupt signal 11 is generated when writing is performed to the input data buffer register 2 of the host processor, but the process execution unit 7 inputs the command written in the input data buffer register 2 in this interrupt process. A process of writing in the data storage area 5 is performed. Specifically, it receives data from the input data buffer register 2 and writes it to the write address pointer (hereinafter referred to as IWP).
Write the command or parameter to the address indicated by and add "1" to the value of IWP. The input operation is repeated every time data is input to the input data buffer register 2. The processing execution unit 7 also uses a read address pointer (hereinafter referred to as IRP) or a second read address pointer (hereinafter referred to as IRP) used when an emergency command is input.
IRP2) command is taken from IRP2) IRP
, Or IRP2 value is incremented by “1”, and the process branches to command processing. In addition to IWP and IRP, a flag indicating that there is no free space in the input data storage area 5 is provided. This flag prevents the processing execution unit 7 from writing too many commands in the input data storage area 5. ing.

By inputting the command in this way, the command input speed of the host processor is high, and the process execution unit 7
Even if the command processing is slow, the command and the parameter of the number of bytes for the area of the input data storage area 5 can be input without waiting for the command processing of the processing execution unit 7.

FIG. 4 shows an example of the data format of commands and parameters input in this embodiment. Bits 0 to 6 of the first byte in FIG. 4 indicate a command code, and bit 7 is an emergency command identification bit for identifying whether or not the command is to start processing urgently. Command processing is prioritized over the command stored in area 5, and "0" indicates that processing is performed normally.
The second byte in FIG. 4 shows the parameter that is subsequently input to the command.

Next, the command receiving process in the process execution unit 7 when a command is input will be described with reference to the flowchart of FIG.

First, wait until there is a command input from the host processor or external input device to the input / output data storage area 5 (step). When there is an input, it is determined whether or not the input command is an emergency command by checking the value with the emergency command determination flag register 12 (hereinafter referred to as UFLG) (step). If it is determined that the input has been made, the emergency command processing is performed first. First, a command receiving process 1 for directly receiving a command from the input data buffer register 2 is performed (step). Since UFLG = 1 at this point, data input from the host processor is prohibited.
Reset UFLG (step) to allow entry of the next command or parameter. Next, after setting the number of parameters (hereinafter referred to as PCNT) corresponding to the received command (step), input / output data storage area 5
Is searched for the address storing the urgent command to be processed (step), and the second read address pointer IRP2 of the next address is set (step). Next, the parameter receiving process of steps 1 to 3 is performed. That is, it is determined whether or not PCNT is 0 (step), and if PCNT ≠ 0 and there is a parameter that has not been received yet, wait until the parameter is input to the input / output data storage area 5 (step). . When there is an input, the parameter is read from the address indicated by IRP2 in the input / output data storage area 5 (step), and "1" is added to the value of IRP2 (step). Next, the value of PCNT is set to +1 (step), and the process returns to the start of the parameter receiving process (step). When PCNT = 0 and the specified number of parameters have been received in the judgment in the step, the process branches to each command processing for processing the received parameters.

If it is determined in the step that UFLG = 0, that is, if a command that is not an emergency command is input, the command that is stored in the input / output data storage area 5 and that does not need to be processed urgently is stored. Process in order. That is, the bit 7 of the data stored in the input / output data storage area 5 pointed to by the IRP is judged (step), and when the bit 7 = 1 is judged to be the emergency command, the command processing has already been executed. Since it has already been completed, "parameter number + 1" is added to the IRP value (step), and the emergency command and parameter reception processing is skipped. When it is determined in step that the command pointed to by the IRP is bit 7 = 0 and the command does not require urgent processing, the command is received from the input / output data storage area 5 and the IRP value is incremented by 1 ( Command reception processing 2, spring) is performed. Next, the PCNT corresponding to the received command is set (step), and the parameter receiving process from step to is performed. That is, it is determined whether or not PCNT is 0 (step), and if PCNT ≠ 0 and there is a parameter that has not been received yet, wait until the parameter is input to the input / output data storage area 5 (step). . Check UFLG when entered (step). If UFLG = 0 and no command requiring urgent processing has been input,
After receiving the parameter stored in the input / output data storage area 5 pointed to by the IRP and performing the process of incrementing IRP (step), the value of PCNT is decremented by -1 (step), and the parameter receiving process is performed again. Start (return to step, repeat the above process for the number of times specified by PCNT. If it is determined in step that UFLG = 1, a command requiring urgent processing is input, the command code being executed, And save necessary command processing information such as the number of processed parameters in the internal memory (step) and branch to the receiving process of the command that should be processed urgently. Return the command code, the number of parameters, etc. that have been set, and continue the process.By the judgment at the step, PCNT = 0 and the specified number of parameters are set. When it is received, it branches to each command processing.

If the processing is performed as described above, it is checked whether or not the emergency command is input each time the reception processing of each parameter is completed. In addition, it is possible to start the processing before the command being processed and the command already input and stored in the FIFO buffer.

[Second Embodiment] FIG. 2 is a block diagram of a display processing apparatus according to a second embodiment of the present invention. Since the configuration diagram of the second embodiment has almost the same configuration as the configuration diagram of the first embodiment, only different cases will be described.

The urgent command specification register 14 is a register in which a command to be urgently processed by the host processor is specified in advance. The comparison circuit 15 compares the value of the input data buffer register 2 with the value of the emergency command designation register 14, and when they match, activates the match signal 16 to set the emergency command determination flag register UFLG12. Therefore, when a previously specified emergency command is input to the emergency command specification register 14, the emergency command determination flag register 12 is set.

When the emergency command determination flag register 12 is set, the interrupt signal 17 becomes active and the process execution unit 7
Generates an interrupt signal 17 to the. Unlike the first embodiment, the input command data format does not have an emergency command identification bit, and bits 0 to 7 are used as a command code.

Here, the interrupt process activated when the emergency command is input will be described with reference to the flowchart of FIG. First, a command reception process 1 for directly receiving a command from the input data buffer register 2 is performed (step), and UFLG is reset (step) to enable input of the next command or parameter. Next, PCNT corresponding to the received command is set (step), and it is determined whether PCNT is 0 (step). If PCNT ≠ 0 and there is a parameter, the input data storage area 5 is searched to find the address that stores the emergency command to be processed (step), and the second IRP2 is set to the next address. After setting (step), the normal command processing (step of the first embodiment) is returned to, and the same processing as that of the first embodiment is performed.

In addition, the processing for a non-urgent command is the same as the processing when UFLG = 0 is determined in the determination in the step in the first embodiment, and thus the description thereof is omitted here.

When the above processing is performed, when the data input from the host processor is temporarily stored in the FIFO format buffer, the time elapses between the input of the command and the actual start of command processing. Also, if a command to be processed urgently, which has been designated in the register in advance, is input, the processing can be started before the command already stored in the FIFO buffer.
Furthermore, by providing a plurality of emergency command designation registers 14 and a plurality of comparison circuits 15, it is possible to increase the types of commands that are to be processed urgently.

〔The invention's effect〕

As described above, according to the present invention, when the process of receiving the command and parameter written from the host processor is performed using the FIFO format buffer, the process execution unit actually receives the command. Display data that can start the processing of commands that are required to be processed urgently even if a certain amount of time elapses before the start of command processing, before the commands already stored in the FIFO buffer A processing device can be provided.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a display data processing device according to a first embodiment of the present invention, FIG. 2 is a block configuration diagram of a display data processing device according to a second embodiment of the present invention, and FIG. 3 is a first embodiment, an embodiment. Two
4 is a detailed diagram of the input data storage area of FIG. 4, FIG. 4 is a format diagram of the input data of the first embodiment, FIG. 5 is a flowchart of the program processing in the processing execution unit of the first embodiment, and FIG. 6 is an emergency of the second embodiment. FIG. 7 is a block diagram of a conventional display processing device, and FIG. 7 is a flowchart of interrupt processing in the processing execution unit that is activated when a command is input. 1 ... Output data buffer register, 2 ... Input data buffer register, 3 ... Input / output control circuit, 4 ... Status register, 5 ... Input / output data storage area, 6 ...
... Pointer register, 7 ... Processing execution unit, 8 ... Internal memory, 9 ... Write signal, 10 ... Read signal, 11 ... I / O interrupt signal, 12 ... Emergency command determination flag register, 13 ... Emergency Command input signal, 14 …… Emergency command specification register, 15 …… Comparison circuit, 16 …… Match signal, 17
...... Emergency command processing interrupt signal, 31 ...... Display timing generation circuit, 32 ...... Display memory, 33 ...... Video signal generation circuit, 34 ...... CRT, 35 ...... Light pen, 38 ...... Light pen input signal, 39 ...... Vertical timing signal, 40 …… Light pen detection signal, 51 …… Output data buffer register, 52
Input data buffer register, 53 Input / output control circuit, 54 Status register, 55 Input / output data storage area, 56 Pointer register, 57 Processing unit, 58 Internal memory, 59 ...... Write signal, 60 …… Read signal, 61 …… I / O interrupt signal, 100 …… Host interface control section, 200 …… Host interface control section.

Claims (1)

(57) [Claims] 1. A display memory for storing at least display information, a display timing generating circuit for generating display timing and horizontal and vertical synchronizing signals of a CRT display, and a CRT using the display information as display data based on the display timing. A display device that includes a video signal generator that is sent to a display, and that sequentially reads the display information stored in the display memory and displays it on a CRT, and command data that is input from an external processing device and that instructs the display processing. Is temporarily stored, a processing execution unit that reads out command data from the storage unit and executes display processing according to the command data, and the command data is command data to be urgently processed. Determination means for determining whether or not it is determined, a flag register that can be read by the processing execution unit and is stored in the determined result, and the flag Display data processing device, characterized in that from said memory means corresponding to the value of Gurejisuta and means for selecting a command data to be executed by the processing execution section.