JP2560734B2 - Computer performance adjustment method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Industrial field of application Conventional technology and problems to be solved by the invention Means for solving the problems Action Example Working effect of the invention [Outline] A buffer storage is provided. , For the performance adjustment method in the computer system which controls the pipeline by the micro program, to correct the performance adjustment error due to the memory access,
Stop the operation of the central processing unit (CPU) for the performance adjustment,
Or, for the purpose of improving the reproducibility of the start timing and eliminating the variation in the instruction execution time due to the memory access, (1) a main performance adjustment counter in the central processing unit (CPU), A stop change boundary register is provided, and when the count value of the main performance adjustment counter matches the value indicated by the stop change boundary register, a pseudo fault is generated,
In the method of adjusting the performance of the computer by stopping the operation of the central processing unit (CPU) and restarting the operation due to the overflow of the main performance adjustment counter, in order to correct the performance adjustment error due to the memory access. A correction counter (IPC) is provided, and a performance error caused by a miss hit is measured by the correction counter (IPC), and after the memory access is completed, the counting operation of the main performance adjustment counter is stopped by the correction amount. It was done.

(2) In the above computer performance adjustment method, one or more arbitrary ones are selected from various control signals in the central processing unit (CPU), and depending on conditions such as a combination thereof,
It is designed to control the operation period and stop period of the central processing unit (CPU). (3) In a computer using the above performance adjusting mechanism of the computer, the performance adjusting mechanism absorbs the performance variation due to the hit / miss hit of the buffer storage, and effectively eliminates the performance variation. Is.

[Industrial applications]

The present invention relates to a performance adjustment method in a computer system that includes a buffer storage and controls a pipeline by a microprogram, and particularly, to a performance error at the time of a memory access hit / miss hit in a computer system that includes a buffer storage. A highly accurate performance adjustment method or a performance adjustment method with good reproducibility, and further, the performance adjustment mechanism absorbs variations in performance due to hits / misses at the time of memory access and effectively varies the performance. It relates to a performance adjustment method for eliminating the problem.

With the recent spread of computer systems, data processing by computers has come to be performed in various fields, and as the diversification of data processing is promoted, the processing capacity and system configuration required by users are also diversified. It has become important how to economically supply a computer system having a processing capacity and a system configuration required by a user, for example, without changing the hardware configuration.

In this case, it is necessary to effectively limit the performance of the system configuration required by the user, that is, the hardware and software, especially the performance of the operating system (OS).

For example, in the case where the operating system (OS) submits jobs to a queue for processing, if a job exceeding the processing capability is submitted, the queue becomes full and the processing capability of the computer is reduced. Since an abrupt drop occurs, an effective performance adjustment method to know the limit is required. Further, since the usage rate for the main storage device (MS) is also a key to show the performance of the computer system, an effective performance adjustment method for investigating the usage rate becomes necessary.

In such a performance adjustment method, uniform performance adjustment must be performed regardless of its application.

Therefore, a performance adjustment method with high accuracy and good reproducibility is required.

Further, as one of the means for improving the performance, in a computer system equipped with a buffer storage, there is a problem that a large variation occurs in the performance due to a hit / miss hit to the buffer storage. Although it is awaited to build a computer system that can not see, the performance adjustment mechanism of the computer is an artificial operation,
Since it adjusts the performance of the computer, it is expected that the above performance variation can be absorbed by using the performance adjusting mechanism.

[Problems to be solved by conventional technology and invention]

FIG. 4 is a diagram for explaining a performance adjusting method of a conventional computer, (a) shows an example of the configuration of the entire computer, (b) shows an example of the configuration of the conventional performance adjusting method, and (c) shows an operation. The time chart is shown, and (d) shows a problem in performance adjustment when the main memory is read.

(1) The computer controlled by the microprogram of this example is, as shown in (a), a central processing unit (CPU).
1, a buffer memory unit (BSU) 2, a main storage unit (M
SU) 3.

In this computer, the central processing unit (CPU) 1 is provided with means for setting the operating time and the stop time of the central processing unit (CPU) 1 to adjust the performance. , A micro program processing counter (or main performance adjustment counter) (MPC) 11 and a CPU operation stop processing change boundary register (LR) 12 are provided.

A main performance adjustment counter (hereinafter referred to as MPC) 11 is an increment counter, which is incremented by, for example, a clock for operating the control memory. When the upper limit is reached, {that is, when the overflow (OVF bit is'on ': hereinafter omitted)} is cleared.

A CPU operation stop processing change boundary register (hereinafter, referred to as LR) 12 indicates a time at which the operation and stop of the central processing unit (CPU) 1 is switched.

As shown in this figure (c), the value of MPC11 changes from '0' to LR12.
Up to the value indicated by means that the system is operating, and until the MPC11 overflows from the value indicated by LR12, it indicates that the system is stopped.When the MPC11 overflows, MPC11 is cleared and the increment is started again. It is repeated to indicate that the operation is in progress.

By the above operation, logically, assuming that the operating time is t ₁ and the stop time is t ₂ , the performance of the computer is It should be possible to adjust it.

However, in the actual device, the main memory unit (MSU) 3
Is accessed via the buffer memory unit (BSU) 2.

An example of the read operation for the main memory unit (MSU) 3 is shown in FIG.

As is clear from this figure, in the microprogram control type computer system, the main memory access processing is performed in the form of a command by the microprogram.
(Refer to step 50), the main memory data is the central processing unit (CP
U) until it is returned to (1) (see steps 51 to 54), the buffer memory unit (BSU) 2 remains in the central processing unit (C).
PU) 1 is sent an interlock signal to stop microprogram processing.

In such a device, if the performance adjustment using the MPC11 described above is performed, the value of MPC11 reaches the value of LR12 even when the interlock signal is'on ', and the central processing unit (C
PU) 1 is in the processing stop state and does not meet the above performance ratio.

Further, the processing time of the main memory access instruction is clear from the diagram (d) when the buffer memory unit (BSU) 2 has a buffer hit and when there is no buffer hit (steps 52 to 55, 5255), the number of microinstruction steps during performance adjustment and the number of microinstruction steps during non-performance adjustment are There is a problem that it does not happen.

In addition to the interlock at the time of accessing the main memory, one instruction may take several τ for a micro instruction due to other factors (eg, 2τ read, write register instruction, etc.). The lock signal is activated.

On the other hand, as disclosed in Japanese Patent Application No. 60-217076 filed by the applicant of the present application, as means for stopping the operation of the central processing unit (CPU) 1 and the like in the performance adjusting method as described above. , When the value of MPC11 matches the value of LR12, a pseudo failure is generated by using the device stop function at the time of failure that the computer system originally has, and a micro processor such as the central processing unit (CPU) 1 There is a way to stop the program.

However, at the time of failure, when the pseudo error signal is output from the central processing unit (CPU) 1 to the buffer memory unit (BSU) 2, as shown in FIG. Returns to the process of step 50 from the time when the pseudo error is detected, and operates so as to restart from the process. Therefore, the processing time of the main memory read instruction is set to t _3, and the pseudo error signal of the read command is issued. When the up generation time and t _4, the pseudo overhead due error t _4, and the overall processing time of the read command t ₃ +
There is a problem that the accuracy of performance adjustment becomes more inaccurate because of t ₄ .

(2) Further, in the above-mentioned conventional method, as is clear from FIG. 2B, since the interruption and resumption of the processing are repeated depending on the value of MPC11, the central processing unit (CPU) that continuously processes an arbitrary instruction. In No. 1, the process is interrupted at random timing.

On the other hand, a bug in the performance adjustment circuit or a circuit caused by the performance adjustment often depends on the timing of interruption or resumption of the above processing. In this conventional method, the reproducibility of development is low and many bugs are used for debugging. There was a problem that it took time, and in some cases it was not possible to debug.

(3) Further, as a means for improving the performance of a computer, conventionally, a method using an address translation buffer (TLB) (a method for accelerating the conversion of a logical address to a real address), a local buffer storage (LBS), a global buffer storage Means for speeding up memory access such as (GBS) are well known.

However, since the hit ratio of these buffer storages varies greatly depending on the access environment at that time,
Even if the same processing was performed, there was a problem that the CPU time changed significantly. {Refer to (d) of this figure} In order to eliminate this change in CPU time (variation in performance), it is sufficient to eliminate the buffer storage (that is, the buffer memory device 2). In the end, it was impossible to eliminate the variation in the performance.

In view of the above-mentioned conventional drawbacks, the present invention corrects a performance adjustment error associated with memory access, and improves the reproducibility of the timing of stopping or starting the operation of the central processing unit (CPU) for the performance adjustment. It is also an object of the present invention to provide a performance adjustment method that suppresses variation in instruction execution time associated with the memory access.

[Means for solving problems]

The above problems are (1) In a computer system that includes a buffer storage and controls a pipeline by a microprogram, a main performance adjustment counter 11 is provided in a central processing unit (CPU) 1.
And a stop change boundary register 12 are provided, and when the count value of the main performance adjustment counter 11 matches the value indicated by the stop change boundary register 12,
When the performance of the computer is adjusted by stopping the operation of the central processing unit (CPU) 1 by causing a pseudo fault and restarting the operation when the main performance adjustment counter 11 overflows, When an interlock signal for stopping the operations of the central processing unit (CPU) 1 and the buffer storage unit 2 is activated in response to the access to the device (MS), etc. The performance adjustment counter 11 is configured to suppress the counting operation.

(2) In a computer system equipped with the above performance adjustment mechanism and equipped with a buffer storage, the operations of the central processing unit (CPU) 1 and the buffer storage unit 2 are stopped in response to an access to the main storage device (MS) or the like. When the interlock signal to activate the signal is activated, the central processing unit (CPU) 1 in the interlock is activated.
An interlock processing stop time counter 13 for counting the processing stop period is provided, and while the interlock signal is being output, the time during which the operation stop request is output by the main performance adjustment counter 11 is counted, and the interlock Is turned off, the operation of the central processing unit (CPU) 1 is restarted, and when the next operation stop time is reached, the interlocking process stop time counter 13
Is configured to stop the counting operation of the main performance adjustment counter 11 only for the time indicated by.

(3) In a computer system having a performance adjusting mechanism of the computer, a main performance adjusting counter and a stop change boundary register are provided in a central processing unit, and the count value of the main performance adjusting counter is the stop change boundary. When the value coincides with the value indicated by the register, a pseudo fault is generated, the operation of the central processing unit is stopped, and the operation is restarted when the main performance adjustment counter overflows. Of the control signal in the various control units in the central processing unit (CPU) 1.
One or a plurality of selected control signals and activates by detecting a specific logical condition between the selected plurality of control signals, or a specific logical condition between the selected plurality of control signals is activated. It is configured to detect and stop the central processing unit (CPU) 1.

(4) Equipped with the above performance adjustment mechanism and buffer storage,
In a computer system that controls a pipeline with a microprogram, a mechanism that adjusts the performance of the computer is used to obtain a logical sum signal of signal variations indicating a delay occurring at the time of hit / miss hit when accessing the buffer storage. , Adding means 120 to 122 for adding to the stop change boundary register (12), and when a match signal between the addition result obtained by the adding means 120 to 122 and the main performance adjustment counter 11 is obtained,
It is configured to stop the operation of the central processing unit (CPU) 1.

[Action]

That is, according to the present invention, in a computer system including a buffer storage and controlling a pipeline by a microprogram, a main performance adjustment counter (MP) is provided in a central processing unit (CPU).
C) and a stop change boundary register (LR) are provided. When the count value of the main performance adjustment counter (MPC) matches the value indicated by the stop change boundary register (LR), a pseudo fault is generated. It is generated and the operation of the central processing unit (CPU) is stopped, and the main performance adjustment counter (MP
When the performance of the computer is adjusted by restarting the operation when C) overflows, (1) When the main memory access instruction is issued from the central processing unit (CPU), the buffer memory unit (BSU) By interlock signal from, because it functions to suppress the counting operation of the main performance adjustment counter (MPC),
The adjustment ratio of the number of steps of microinstructions comes close to t ₁ / t ₁ + t ₂ .

(2) An interlock processing stop time counter (IPC) that counts the processing stop period for the central processing sugar coating (CPU) during the interlock is provided, and the operation is stopped by the MPC while the interlock signal is output. When the time when the request is output is counted, the interlock is turned off, the operation of the central processing unit (CPU) is restarted, and the operation stop time is reached again, the interlock processing stop time counter By causing the MPC counting operation to stop and the central processing unit (CPU) operation to stop only for the value indicated by (IPC), the memory access overhead caused by the occurrence of a pseudo fault during interlocking is caused. It is possible to eliminate the increase or decrease in the time taken to process the micro instruction.

(3) To select one or a plurality of various control signals in the central processing unit (CPU) and detect a specific logical condition between the selected control signals in the performance adjusting method of the computer. Registers (OPSR1, 2, ...) Are provided and the operation of the central processing unit (CPU) is stopped according to the detection result of the specific logical condition, or the MP
By activating the count operation of C, the operation of the central processing unit (CPU) is interrupted only at the specific timing specified by the above registers (OPSR1,2, ...), and the interruption is reproduced. And the efficiency of computer verification can be improved.

(4) Generally, the instruction execution time T in the central processing unit (CPU)
i is the number of basic steps of instruction execution × machine cycle E,
Penalty due to pipeline disturbance (disorder due to conditional branch) D, penalty associated with memory access {so-called address translation buffer (TLB miss), delay due to hit miss (LBS miss, GBS miss) on buffer memory} Let S be the following equation.

Ti = E + D + S On the other hand, the above (1) to (3) using the performance adjustment counter
In the computer system that adopted the performance adjustment method of
If the delay due to the performance adjustment is R, then Ti = E + D + S + R.

As described above, the S term changes greatly because the hit rate for the address translation buffer (TLB), buffer storage (LBS, GBS), etc. changes depending on the environment of the computer system.

However, since the R term is a performance adjustment term, it can be artificially changed arbitrarily.

Therefore, in order to eliminate the variation in the instruction execution time (Ti), that is, in order to keep Ti constant, R = -S may be set.

However, in reality, since R can take only a positive value, R = K−S where K = constant and Ti = E + D + S + (K−S) to keep the Ti constant. Therefore, the main performance adjustment counter (MPC) has a sufficient number of bits so that the above E + D + K time can be counted, and the CPU operation stop processing change boundary register (LR) has E
By setting + D time, when the MPC counts “E + D + S” for any S term within the range of K−S> 0, by stopping the operation of the central processing unit (CPU), It is possible to keep Ti apparently constant (Ti = E + D + K).

That is, in the present invention, the performance adjustment error associated with the memory access is corrected, the reproducibility of the timing of stopping or starting the operation of the central processing unit (CPU) for the performance adjustment is improved, and There is an effect that it is possible to suppress variation in instruction execution time due to the memory access.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram for explaining an embodiment of the present invention, (a),
(B) shows a configuration example, (c1 to c3) show operation time charts, FIGS. 2 and 3 are diagrams for explaining another embodiment of the present invention, and (a) shows A configuration example is shown (b)
Shows the operation time chart, and the main performance adjustment counter (MP
C) 11 count suppressing means 110, the interlocking process stop time counter (IPC) 13 of FIG. 1 (b) and its associated control mechanism 19, 130, and various control signals in FIG. 2 (a) are selected, Registers (OPSR1 to 5) for detecting a specific logical condition between the control signals, and an execution time register (EPR) 14,
Stop time register (SPR) 15, addition to add the logical sum of the signal indicating the delay that occurs at the time of a miss hit when accessing the buffer storage in FIG. 3 (a) to the CPU processing operation stop change boundary register (LR) 12 Means 120-123 are the means necessary to carry out the invention. Note that the same reference numerals indicate the same object throughout the drawings.

First, referring to FIG. 1, a buffer memory device (BSU)
A method of correcting a performance adjustment error associated with memory access in a computer system including the following will be described.

In this embodiment, the computer system shown in FIG. 4 (a) is taken as an example. That is, the computer system comprises a central processing unit (CPU) 1, a buffer memory unit (BSU) 2 and a main storage unit (MSU) 3. The buffer memory unit (BSU) 2 includes an address translation buffer (TLB) that translates a virtual (logical) address into a real address, a buffer storage (LBS, GBS) mechanism, and the like.

[1] Embodiment of FIG. 1A: A central processing unit (hereinafter referred to as a CPU) 1 includes an instruction processing unit (IU) 17, a control memory (CS) 16, its address register (CSAR) 160, and data. It is equipped with a register (CSDR) 161, MPC11 and LR12 for performance adjustment, and while the MPC11 is counting from "0" to the time indicated by LR12, each unit in the CPU1 is operating and the From the indicated time until the MPC 11 overflows, each unit in the CPU 1 stops its operation and adjusts the performance of the computer system.
{Refer to the time chart of this figure (c1)} In the present invention, in the CPU1 having such a performance adjusting mechanism, the main memory access command is output from the CPU1,
When the interlock signal is returned from the buffer memory unit (BSU) 2, while the units in the CPU 1 are stopped, the counting operation of the MPC 11 is suppressed and the performance adjustment accompanying the memory access by the interlock signal is performed. Correct the error. {Refer to the time chart shown by the dotted line in this figure (c2)} [2] Example of this figure (b): In this example, in addition to the functional blocks described in [1] above An in-lock processing stop time counter (hereinafter referred to as IPC) 13 is provided.

Normally, the IPC13 is "0", and the CPU1 continues to count up and the CPU1 continues to process until it reaches the value of LR12.

Then, when the value of the MPC11 exceeds the value of LR12, M
The operation of the CPU1 is stopped until the PC11 overflows, but as described above, the main memory access instruction is issued while the CPU1 is operating, and the interlock signal is returned from the buffer memory device (BSU) 2. And in the present invention,
When the CPU1 stop time (MPC = LR) is reached, a pseudo error signal is sent from the error controller 18 to the buffer memory device (BS
U) It is prevented from being sent to 2 to eliminate the memory access overhead caused by the occurrence of the pseudo error at the time of the memory access, and the stop instruction FF19
Is turned on, the IPC13 is started, and the CPU operation stop duration during the interlock is counted {(Fig. (C
3) Increment reference}, MPC11 overflows,
When the above stop instruction FF19 is turned off, the IPC1
The increment operation at 3 is stopped.

Then, when the interlock signal from the buffer memory device (BSU) 2 is turned “off”, the CPU 1 restarts its operation, and the next operation stop time (MPC = LR) is reached, that is, the above stop instruction. When FF19 turns on, the IPC1
For the count value of 3 (that is, while the IPC13 is decrementing), the count operation of the MPC11 is suppressed by the gate circuit 130, and when the count value of the IPC13 becomes '0', the MPC11
It restarts the counting operation in and functions to instruct the original stop time of CPU1. {Refer to (c3) decrement in this figure} The period (indicated by the dotted line) in which this MPC11 is prevented from counting becomes the CPU stop time correction time. And
In the case of the present invention, as is clear from the OR circuit 131 of FIG. 7B, even if the values of MPC11 and LR12 match, the error processing unit 1
Since the 8 is not activated, the pseudo error signal is not sent to the buffer memory device (BSU) 2 and, therefore, the memory access performance adjustment error does not occur.

Of course, when the interlock signal is not activated due to the memory access and other factors, Japanese Patent Application No.
The conventional performance adjustment method disclosed in Japanese Patent No. 217076 is executed, and a pseudo error signal for each unit in the CPU 1 causes the CPU 1, the buffer memory device (BSU) 2, etc.
Although the operation stop signal is issued, the performance adjustment error at that time is about several τ at the most, so the influence on the performance adjustment is negligible. {Refer to this figure (c1)} [3] Embodiment of FIG. 2: In this embodiment, for convenience of explanation, for example, MPC11
In place of the LR12 described in [1] and [2], an execution time register (hereinafter referred to as EPR) 14, a stop time register (hereinafter referred to as SPR) 15, and various control signals in the CPU 1 are selected. There are provided registers (OPSR2 to 5) and a register (OPSR1) for detecting a specific condition between the control signals.

That is, CPU1 selected by the register (OPSR2-5)
Various control signals within the control signals are further selected by the register (OPSR1), and a specific logical condition between the selected control signals is set, and the check circuit 110 allows each selected control signal to satisfy this condition. Checking is done.

Specifically, by comparing each bit of the control signal connected to the register (OPSR1) and a check bit (not shown) provided in the check circuit in a one-to-one correspondence, for example, It is possible to check a specific condition between the selected control signals. At this time, the coincidence signal is stored in a latch (not shown) in the check circuit 110 and is reset by a coincidence signal of MPC = EPR described later.

While it is detected that the above conditions are met, or while processing is suspended {Processing FF (EXECUT
E) 140 is'off '}, MPC11 is incremented.

Then, while the process is being executed (EXECUTE140: ON), it is counted up to the operation time upper limit value instructed by EPR14. ) Reset 140.
{Refer to (b) EXCUTE (E ₀ , E ₁ , ...) in this figure} In addition, when the process is stopped (EXECUTE 140: OFF), it is counted up to the stop time upper limit value indicated by SPR15, and if it matches, MP
Clear C11 and set FF (EXECUTE) 140 during the above processing.

In the case of this method, the processing execution time varies depending on the conditions to be set, but since it can be considered as a substantially constant ratio as a whole, as in the past, the ratio of the EPR14 and SPR15 values causes the computer system to change. You can adjust the performance of CPU1
Since the condition for operating is constant, there is an advantage that the reproducibility can be increased.

Further, in the present embodiment, an example in which the above-mentioned specific condition is detected and the MPC11 is activated has been described, but it goes without saying that the operation of the CPU1 may be directly stopped by the detection signal. That is not the case.

Also, as a matter of course, when the value of the MPC11 matches the value of the LR12, a pseudo fault is caused to stop the operation of the central processing unit (CPU) 1, and the operation is performed when the MPC11 overflows. It goes without saying that it may be applied to a method of adjusting the performance of the computer by restarting. In this case, the specific condition is detected and the operation of the central processing unit (CPU) 1 is stopped, or the specific condition is detected and the count operation of the MPC 11 is started. .

[4] Embodiment of FIG. 3: First, in the performance adjusting mechanism of this embodiment, an MPC 11 having a sufficient number of bits is prepared, and, for example, a wraparound operation is performed by the operation clock of the CPU 1.

Next, in the LR12, the above-mentioned basic number of instruction execution steps x machine cycle is E, the penalty due to the disturbance of the pipeline is D, the penalty associated with memory access (so-called TLB miss,
Set the value of “E + D / E + D + K × MPC”, where S is the LBS miss and GBS miss delay) and K is the constant.

Then, the adder 122 calculates “LR + αS”, and the comparator 1
At 12, compare with the value of MPC11.

 The GO / STOP control unit 111 is caused to function so as to send out a “GO” signal when MPC <LR + αS and a “STOP” signal when MPC> LR + αS.

During the “GO” period, the delay due to the S term is generated by the gate circuit 121, multiplied by α by the multiplier (Xα) 120, and input to the adder 122. At this time, α is 0 ≦ α, but is usually set to a fixed value “1”.

In order to make the above operation easier to understand, (b) of the figure shows the operation in a time chart. Within a certain unit time (for example, the time when the EPC 11 totally counts), the E term, the D term, and the S term are operating in a mixed manner in the time of the “GO”.

The “GO” operation is performed for the time (E + D) set in the LR12, and the delay of the S term during that time (indicated by GO _L in the figure) is counted by the adder 122.

And in some cases, if this term is'S1 ', the extra'GO' operation is performed by the amount of'S1 'and the remaining value, that is, the time of'K-S1 = R1'is'STOP'."(STOP1)
To operate.

In another case, if this term is'S2 ', the extra'GO' operation is performed by the amount of'S2 'and the remaining value, that is, the time of'K-S2 = R2'is'STOP'."(STOP2) to operate.

By operating as described above, the delay due to the S term can be absorbed by decreasing the R term, and the apparent performance (Ti) of the CPU 1 can be made constant.

Thus, the present invention comprises buffer storage,
In a computer system that controls a pipeline with a micro program, a system that has a performance adjustment mechanism with a performance adjustment counter (MPC), at the time of memory access,
Paying attention to the fact that an interlock signal is sent from the buffer memory device, the performance adjustment counter (MPC) is controlled by using the interlock signal, or another interlock processing stop time counter (IPC) is used. Is provided to count the processing stop period of the MPC during the interlock, and the MPC is counted at the processing stop point (MPC = LR) output by the MPC after the interlock is released. The operation is suppressed to correct the performance adjustment error at the time of accessing the memory, or the central processing unit (CP
By specifying the operation stop condition for U) by using one or more control signals in the central processing unit (CPU), performance adjustment with good reproducibility is performed, and the performance adjustment mechanism is It is characterized in that it absorbs the variation in performance at the time of memory access hit / non-hit and keeps the apparent performance (Ti) at the time of memory access constant.

〔The invention's effect〕

As described in detail above, the computer performance adjustment method of the present invention is as follows: (1) The main performance adjustment counter and the stop change boundary register are provided in the central processing unit (CPU), and the main performance adjustment counter is provided. When the count value of is equal to the value indicated by the stop change boundary register, a pseudo fault is generated,
In the method of adjusting the performance of the computer by stopping the operation of the central processing unit (CPU) and restarting the operation due to the overflow of the main performance adjustment counter, in order to correct the performance adjustment error due to the memory access. A correction counter (IPC) is provided, and a performance error caused by a miss hit is measured by the correction counter (IPC), and after the memory access is completed, the counting operation of the main performance adjustment counter is stopped by the correction amount. It was done.

(2) In the above computer performance adjustment method, one or more arbitrary ones are selected from various control signals in the central processing unit (CPU), and depending on conditions such as a combination thereof,
It is designed to control the operation period and stop period of the central processing unit (CPU).

(3) In a computer using the above performance adjusting mechanism of the computer, the performance adjusting mechanism absorbs the performance variation due to the hit / miss hit of the buffer storage, and effectively eliminates the performance variation. Is.

Therefore, the performance adjustment error accompanying the memory access is corrected, the reproducibility of the timing of stopping or starting the operation of the central processing unit (CPU) for the performance adjustment is improved, and the memory access is accompanied. Instruction execution time (T
There is an effect that the variation of i) can be suppressed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an embodiment of the present invention, FIG. 2 is a diagram illustrating another embodiment of the present invention, FIG. 3 is a diagram illustrating another embodiment of the present invention, and FIG. Is a diagram explaining a conventional computer performance adjustment method. In the drawing, 1 is a central processing unit (CPU), 2 is a buffer memory unit (BSU), 3 is a main memory unit (MSU), 11 is a main performance adjustment counter (MPC), 111 is a GO / STOP control unit, 112 and 113 are Comparator, 12 is CPU operation stop change boundary register, or simply stop change boundary register (LR), 120 is a multiplier (× α), 121 is a gate circuit, 122 is an adder, 13 is a processing stop time counter during interlock (IPC), 130 is a gate circuit, 131 is a logical sum circuit, 14 is an execution time register (EPR), 140 is a processing execution FF (EXECUTE), 15 is a stop time register (SPR), and 16 is a control memory (CS). , 17 is an instruction processing unit (IU), 18 is an error processing unit, 50 to 55 are processing steps, OPSR1 to 5 are registers, E is the basic number of instruction execution steps x machine cycles, D is a penalty due to disturbance of the pipeline, S Is a penalty for memory access, K is a constant, and Show.

Claims (4)

(57) [Claims] 1. A computer system having a buffer storage and controlling a pipeline by a microprogram, wherein a main performance adjustment counter and a stop change boundary register are provided in a central processing unit, and a count value of the main performance adjustment counter. However, when it matches the value indicated by the stop change boundary register, a pseudo fault is caused to stop the operation of the central processing unit,
This is a method for adjusting the performance of the computer by restarting the operation when the main performance adjustment counter overflows, and the operation of the central processing unit and the buffer storage unit corresponding to the access to the main storage device. A performance adjusting system for a computer, characterized in that, when an interlock signal for stopping the operation is activated, the counting operation of the main performance adjusting counter is suppressed by the interlock signal. 2. In a computer system having a buffer storage and controlling a pipeline by a microprogram, a main performance adjustment counter and a stop change boundary register are provided in a central processing unit, and a count value of the main performance adjustment counter. However, when it matches the value indicated by the stop change boundary register, a pseudo fault is caused to stop the operation of the central processing unit,
This is a method for adjusting the performance of the computer by restarting the operation when the main performance adjustment counter overflows, and the operation of the central processing unit and the buffer storage unit corresponding to the access to the main storage device. When an interlock signal for stopping the interlock is activated, an interlock processing stop time counter for counting the processing stop period for the central processing unit during the interlock is provided, and when the interlock signal is being output. , Counting the time when the operation stop request is output by the main performance adjustment counter,
When the interlock is turned off and the operation of the central processing unit restarts to reach the next operation stop time, the main performance adjustment counter is counted for the time indicated by the interlock processing stop time counter. A computer performance adjustment method characterized by stopping the operation. 3. A main performance adjustment counter and a stop change boundary register are provided in the central processing unit, and when the count value of the main performance adjustment counter matches the value instructed by the stop change boundary register. , Causing a pseudo fault to stop the operation of the central processing unit,
A method of adjusting the performance of the computer by restarting the operation when the main performance adjustment counter overflows, wherein the counting operation of the main performance adjustment counter is performed in various control units in the central processing unit. Select one or more of the control signals and detect and activate a specific logical condition between the selected control signals, or specify between the selected control signals. A method of adjusting the performance of a computer, characterized in that the central processing unit is stopped by detecting the logical condition of. 4. A computer system having a buffer storage and controlling a pipeline by a microprogram, wherein a main performance adjustment counter and a stop change boundary register are provided in a central processing unit, and a count value of the main performance adjustment counter. However, when it matches the value indicated by the stop change boundary register, a pseudo fault is caused to stop the operation of the central processing unit,
A hit / access when the buffer storage is accessed by using the mechanism for adjusting the performance of the computer by restarting the operation when the main performance adjustment counter overflows.
Addition means is provided for adding to the stop change boundary register a logical sum signal of variations in the signal indicating the delay occurring at the time of a mishit, and the addition result obtained by the addition means and the coincidence signal between the main performance adjustment counter are A computer performance adjustment method characterized by stopping the operation of the central processing unit when it is obtained.