JP2554185B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which reduces parasitic capacitance of bit lines to prevent operation delay.

<Prior Art> Conventionally, a basic ROM (read-only memory) has an equivalent circuit as shown in FIG. This RO
M is a word line in which the memory cells M formed of MOSFETs are arranged in a matrix and the gate of each memory cell M extends in the row direction.
Bit lines B ₁ , B ₂ , B ₃ , ..., Bi, Bi + connected to WL ₁ , WL ₂ , ..., WL (nm) and extending sources s and drains d in the column direction
Connected to ₁ . Note that the sources s and drains d of the adjacent memory cells are connected to one bit line so that the chip area can be reduced. For example, when reading the memory cell M indicated by an arrow in FIG. 3, the word line WL _{1 is set} to the high level, the bit line B _{1 is set} to the ground level, and the bit line B ₂ is connected to a sense amplifier (not shown). Then, the data (1 or 0) is read according to the ON or OFF state of the memory cell M. In this ROM, the junction capacitance of all memory cells arranged in the column direction becomes the parasitic capacitance of the bit line, so
As the capacity increases and the number of memory cells connected to the bit line increases, the read operation naturally becomes slow.

Recently, as shown in FIG. 4, a ROM (hereinafter referred to as “bank system ROM”) in which a memory cell array is divided into a plurality of banks to reduce the parasitic capacitance of bit lines has been proposed. This ROM divides each column of the memory cell array in the column direction into banks Bm, 2i−1; Bm + 1,2i shown by broken lines in the figure.
−1; ... and Bm, 2i; Bm + 1,2i ;. The sub bit line S is provided between each bank Bm, 2i−2; Bm, 2i; ... arranged in the row direction.
Bm, 2i-2; SBm, 2i-1; SBm, 2i; ... are provided to connect each sub-bit line to each memory cell M in the bank in the same manner as the bit line of the ROM shown in FIG. ing. Further this sub bit line
SBm, 2i−2; SBm, 2i−1; SBm, 2i; ... is a bank selection MOSFET
(Transfer gate transistor) QOm, 2i-2; QOm, 2i
−1; Main bit line MBi− extending in the column direction via QOm, 2i;
Connected to 1, MBi, ... It should be noted that two sub-bit lines are connected together to one main bit line. Odd Bank B
When the first memory cell M belonging to m, 2i-1 is selected, the main bit line MBi-1 is grounded and the main bit line MBi is electrically connected to the sense amplifier. Further, the bank selection signal BOm indicating selection of the bank Bm, 2i-1 is set to a high level to turn on the bank selection MOSFETs QOm, 2i-2; QOm, 2i-1, and the sub bit lines SBm, 2i- 2; SBm and 2i-1 are electrically connected to the main bit lines MBi-1 and MBi, respectively. Then, reading the data of the memory cell M and the word lines WL ₁ to a high level. As described above, the junction capacitance of the memory cells M in each column is operated in the column direction to reduce the parasitic capacitance of the bit line and prevent the delay of the data read operation.

<Problems to be Solved by the Invention> In a conventional bank-type ROM, reading is performed through two bank selection MOSFETs QOm, 2i-2 and QOm, 2i-1, in addition to the memory cell M, that is, through three MOSFETs. Is done. Therefore, there is a problem that the resistance connected to the bit line is increased and the read operation is delayed as compared with a basic ROM in which the read is performed only through the memory cell. In addition, bank selection MOSFET QOm, 2i−
2; QOm, 2i−1; ... are sub-bit lines SBm, 2i−2; SBm, 2i−1;
Similarly, each bank is arranged in the row direction, that is, each column of memory cells is provided at a narrow pitch. Therefore, a sufficient gate width cannot be secured, the switching speed is reduced, and the read operation is delayed. As described above, the conventional bank-type ROM has a problem in that it cannot sufficiently fulfill the purpose of speeding up the read operation.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of operating at a large capacity and at a high speed by suppressing an operation delay in a bit line.

<Means for Solving the Problems> In order to achieve the above object, according to the present invention, each column of a matrix-shaped memory cell array is partitioned in the column direction to form a plurality of banks, and each bank includes a sub-bit line. Is connected to each memory cell in the bank, and this sub-bit line is connected to the main bit line extending in the column direction through the transfer gate transistor to select a specific memory cell of this memory cell array. , The transfer gate is operated based on a bank selection signal indicating selection of the bank to which the specific memory cell belongs, and the sub-bit line of the bank is electrically connected to the main bit line to connect the memory cells of each column. In a semiconductor memory device in which operation delay is prevented by operating in a state where the capacitance is divided, the sub bit line, the main bit line, and the transfer Gate transistors are provided between every two columns of memory cells arranged in the row direction, and a virtual ground line extending in the column direction and connected to the memory cells on both sides is provided between the two columns. I am trying.

<Operation> One terminal of each memory cell is connected to the sub-bit line,
Further, it is connected to the main bit line via a transfer gate transistor and functions as a drain. The other terminal of each memory cell is directly connected to the virtual ground line and functions as a source. In this case, reading is performed through the memory cell and one transfer gate transistor. That is, the number of transfer gate transistors is reduced by one as compared with the conventional bank ROM. Therefore, the resistance connected to the bit line is reduced as compared with the conventional bank ROM, and the operation delay on the bit line is suppressed. Further, one transfer gate transistor is provided for every two columns of memory cells arranged in the row direction. Therefore, the gate width can be approximately doubled as compared with the conventional ROM in the bank direction, which improves the switching speed and suppresses the operation delay in the bit line. In this way, the operation delay is suppressed in both the number of MOSFETs connected to the bit line and the resistance. Therefore, the read operation is performed at high speed.

<Example> Hereinafter, the semiconductor memory device of the present invention will be described in detail with reference to Examples.

FIG. 1 and FIG. 2 are ROMs of an embodiment of the present invention.
Shows the equivalent circuit and pattern layout. As shown in FIG. 1, this ROM is divided into a plurality of banks Bp−1,2q− indicated by broken lines by partitioning each column of a matrix-shaped memory cell array in the column direction, similarly to the conventional bank type ROM. 2; Bp, 2q−2; B
p + 1,2q-2; ...; Bp-1,2q + 2; Bp, 2q + 2; Bp + 1,2q + 2; ...
Is composed. The symbol Bp, q indicates that this bank B is p
It indicates that it is located at the column, column q. A sub bit line SB is provided between two banks B arranged in the row direction, that is, every two columns of the memory cells M. For example, between the p-th bank Bp, 2q-2 and Bp, 2q-1 the sub-bit line SBp, q
-1, sub-bit line SBp, q is provided between the banks Bp, 2q and Bp, 2q + 1. Similar to the conventional ROM, each sub-bit line SB is connected to each memory cell M arranged on both sides. Each sub bit line
A main bit line MB extending in the column direction is provided along SB. For example, the main bit line MBq−1 is provided between the (2q−2) th column and the (2q−1) th column, and the main bitline MBq is provided between the 2nd column and the (2q + 1) th column. Each sub bit line SB is connected to the main bit line MB via a bank selecting MOSFET (transfer gate transistor) QE provided between banks B adjacent in the column direction. For example, for the p-th row, for bank selection
MOSFET QEp, q−1; Sub-bit line SB via QEp, q
p, q−1; SBp, q is connected to the main bit lines MBq−1, MBq.
On the other hand, between the two columns sandwiched by the main bit lines MB, virtual ground lines IG extending in the column direction are provided and connected to the memory cells arranged on both sides. For example, in the (2q-1) th column
Virtual ground line IGq, (2q + 1) th column and (2q +) between 2nd column
2) A virtual ground line IGq + 1 is provided between columns.

As shown in FIG. 2, this ROM has a pattern in which an equivalent circuit is faithfully laid out. The sub bit line SB and the virtual ground line IG are formed by using metal wiring, the main bit line MB is formed by using an upper layer metal wiring, and the sub bit line and the main bit line are connected by providing a through hole TH between layers. The bank selection line BE and the word line WL are made of polysilicon. The memory cell M is
The word line WL is sandwiched between the contact C on the virtual ground line IG side and the contact C on the sub bit line SB side. In this case, the gate width of the transfer gate transistor QE can be set to be approximately twice the pitch of the memory cells M in the row direction. Therefore, the switching speed can be improved, and the operation delay in the bit line can be suppressed.

This ROM reads data as follows.
For example, assume that the data of the first memory cell M belonging to the bank Bp, q shown in FIG. 1 is read. First, the virtual ground line IGq connected to the memory cell is set to the ground level. Next, the bank select line BEp is set to a high level to turn on the bank select MOSFET QEp, q, and the memory cell M is transferred to the main bit line MBq via the sub bit line SBp, q and the bank select MOSFET QEp, q. Conduct to. Then, the word line WL _{1 is set} to a high level, the sense amplifier determines whether the memory cell is in the on or off state, and the determined result is output as data. When the read operation is performed in this manner, the read can be performed through the two MOSFETs of the memory cell M and the bank selection MOSFETs QEp, q. That is, compared to the conventional bank ROM, bank selection MOSFE
The number of T can be reduced by one. Therefore, the resistance connected to the bit line can be reduced as compared with the conventional bank ROM, and the operation delay in the bit line can be further suppressed. Therefore, reading can be performed at high speed.

Whether the on-state or off-state of the memory cell corresponds to data 1 or 0 can be arbitrarily set. Further, the ON state and the OFF state of the memory cell M are
It is set by ion implantation.

The parasitic capacitances of the bit lines of this ROM and the conventional basic ROM shown in FIG. 3 are compared. Each column of the memory cell array consists of nm memory cells. In the ROM of this embodiment, each column is composed of m banks B, and each bank B is composed of n memory cells. In the read operation, for one main bit line MB, 2n memory cells M on both sides of the sub bit line SB of the selected bank B and unselected (m-1) bank selections Connected with the MOSFET. That is, {2n + (m-1)} MOSFETs are connected. On the other hand, in the case of the conventional basic ROM shown in FIG. 3, nm bit MOSFETs are connected to one bit line Bi. For example, when n = 16 and m = 128, the numbers of MOSFETs of both are 59 and 2048, respectively. This shows that the ROM of this embodiment can effectively reduce the parasitic capacitance of the bit line.

Although the embodiment is a ROM, the present invention is not limited to this, and the present invention can be widely applied to other types of memories.

<Effects of the Invention> As is apparent from the above, in the semiconductor memory device of the present invention, the sub bit line, the main bit line and the transfer gate transistor are provided between every two columns of memory cells arranged in the row direction. , A virtual ground line extending in the column direction and connected to the memory cells on both sides is provided between the two columns, so that a MOSFET connected to the bit line during a read operation is formed.
It is possible to reduce the number and improve the switching characteristics of the transfer gate transistor to prevent the operation delay in the bit line. Therefore, a large capacity and high speed operation can be achieved.

[Brief description of drawings]

FIGS. 1 and 2 are diagrams showing an equivalent circuit and a pattern layout of a ROM according to an embodiment of the present invention, FIGS. 3 and 4, respectively.
FIG. 1 is a diagram showing an equivalent circuit of a conventional basic ROM and a bank-type ROM, respectively. B ... Bank, BE ... Bank selection line, IG ... Virtual ground line, M ... Memory cell, MB ... Main bit line, QE ... Bank selection MOSFET, SB ... Sub bit line, WL ... Word line.

Claims (1)

(57) [Claims] 1. A plurality of banks are formed by partitioning each column of a matrix-shaped memory cell array in the column direction, a sub-bit line is provided for each bank and connected to each memory cell in the bank. A bank indicating that when a specific memory cell of this memory cell array is selected by connecting a bit line to a main bit line extending in the column direction through a transfer gate transistor, the bank to which the specific memory cell belongs is selected. The transfer gate is operated based on the selection signal to operate the sub-bit line of the bank to the main bit line so that the junction capacitance of the memory cells in each column is divided, thereby preventing an operation delay. In such a semiconductor memory device, the sub bit line, the main bit line, and the transfer gate transistor are arranged in every two columns of memory cells arranged in the row direction. And a virtual ground line extending in the column direction and connected to the memory cells on both sides is provided between the two columns.