JP2552757B2 - Digital audio signal intermittent control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Each sample value is accommodated in a temporary accommodation memory from a continuous signal memory accommodating continuous or silent digital values of a plurality of audible signals, and the read address of the temporary accommodation memory is rewritten and multiplexed. A digital audible signal sound intermittent control method for controlling intermittent audible signals, which suppresses the generation of noise such as a click sound generated at the time of switching the intermittent signal without causing a large change in memory capacity. The purpose of the present invention is to provide a digital audio signal interrupt control system capable of storing a signal indicating whether or not the sample data is in a low level section of the audio signal, corresponding to each sample data of the continuous signal memory. An instruction to change the read address of the sample data of the audible signal sound of the temporary signal accommodating memory is generated by the control of the intermittent control unit. At this time, the signal representing the low level section added to the corresponding sample data read from the continuous signal memory to the temporary signal accommodating memory is identified to control the change of the read address of the temporary signal accommodating memory.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio signal interruption control system for generating a multiplexed digital audio signal sound used in a digital exchange system or the like.

The digital exchange system is provided with a configuration for generating a digital audio signal sound in order to send various audio signal sounds such as a dial tone and a ringing tone to the subscriber. At this time, the audible signal sound is stored in the memory as a digital signal, and the continuous signal sound can be reproduced by sequentially reading out by addressing each digital signal.
By multiplexing such read operations, a plurality of audible signal sounds can be simultaneously generated.

[Prior Art] In a digital exchange system, audible signal tones such as dial tone (dial tone), ringing tone (ring back tone), and busy tone (busy tone) are transmitted to the subscriber depending on the status of each connection in the exchange. Sent to notify the status to.

FIG. 7 shows a configuration of a conventional example for generating such an audible signal sound, and FIG. 8 shows data and waveform charts of the conventional example.

In FIG. 7, reference numeral 70 denotes a continuous signal accommodating ROM (read only memory) in which continuous signals of various audible signals (digital signals of sampling signals) are stored, and 71 stores one frame from the continuous signal accommodating ROM 70. Temporary signal accommodating memory, 72 is a parallel-serial converter (indicated by P / S) for converting 8-bit parallel PCM code into serial signal, and 73 is a read address accommodating the address for reading the temporary signal accommodating memory The accommodating memory 74 is an interrupt control unit that controls the interrupt timing of the audible signal.

The continuous signal accommodating ROM 70 accommodates sampling data of one or more cycles of an audible signal calculated in advance by a computer or the like in a time-divided manner for each frequency. Conventional continuous signal accommodation
An example of data stored in the ROM 70 is shown in A. of FIG.

In this example, the first sample (or the first frame) of various audible signal tones is stored at addresses 0 to 31,
For address 0, 425 Hz (beep tone) -15 dBm0 (minus 1
Data of the first sampling (first data) of a waveform of 5 decibels, where 1 milliwatt is 0 dB) is stored,
The silent pattern data is stored in the address 31, and the addresses 32 to 63 respectively correspond to the addresses corresponding to the first data (values obtained by adding 32 to each address of the first sample) to the second of each audible signal sound. Samples are stored, and subsequently, third sample ... Nth sample are sequentially stored for each audible signal for one cycle or more.

The continuous signals in the continuous signal accommodating ROM 70 are sequentially read out and sequentially written in the signal temporary accommodating memory 71 for each sample. The read address accommodating memory 73 accommodates each address for reading each signal written in the signal temporary accommodating memory 71, and sequentially performs reading. Each signal (parallel 8 bits) read from the temporary signal storage memory 71 is converted into a serial signal by the parallel / serial converter 72 (displayed by P / S), and each sample data of each signal is converted into each time slot. It is sent as a time-division-multiplexed serial signal to each part in the exchange, and the necessary signal tones are extracted.

Audible signal sounds include those that are continuously generated (a dial tone) and those that are intermittent at a certain time such as a ringing tone and a busy tone. In the intermittent control corresponding to such a signal sound, the intermittent control of an arbitrary pattern can be performed by rewriting the address stored in the read address storage memory 73 from the intermittent control unit 74 as necessary. That is, it is realized by rewriting the read address of the read address accommodating memory 73 from the address of the audible signal data until then to the address of the silent pattern data at every time determined by the intermittent control unit 74. After changing to the address of the silent pattern and setting it to the "off" state, it is rewritten to the address of the original audible signal after a time determined by the interrupt control unit 74.

B. in FIG. 8 is an example of generating an intermittent waveform (analog image). In the figure, each sample value (specific address of the signal temporary accommodating memory 71) is sequentially read for a specific audible signal sound, and when the signal is cut off, it becomes the address of the silent pattern data, and the silent section ends. Then, it is shown that the address of the original audible signal is rewritten.

[Problems to be Solved by the Invention] According to the above-mentioned conventional method, the read / write address is rewritten by the intermittent control unit 74 at any time, and the switching to the silent pattern and the silent pattern at the high level portion of the continuous signal sound are performed. There is a possibility that switching to a high-level signal sound may occur, and there is a problem in that noise such as a click sound becomes large at the switching point of the intermittent signal, which is often offensive to the listener. The waveform of B. in FIG. 8 shows an example in which the change at the switching point is large.

Such an intermittent signal of the audible signal may be stored in the memory as a waveform switched in advance so that noise is not generated, but since the intermittent period is a long time of seconds, the memory capacity is enormous. There's a problem.

It is an object of the present invention to provide a digital audible signal sound intermittent control method capable of suppressing the generation of noise such as a click sound generated when switching intermittent signals without causing a large change in memory capacity. .

[Means for Solving the Problems] FIG. 1 is a basic configuration diagram of the present invention.

In FIG. 1, 1 is a continuous signal memory in which data of a plurality of samples of continuous audible signal sound and a low level detection signal indicating whether or not each data is low level are stored, 2 is a signal temporary storage memory, 3 is a parallel / serial converter (indicated by P / S), 4 is a read address accommodating memory, 5 is a read address temporary accommodating memory, and 6 is an intermittent control unit.

According to the present invention, a low level detection signal indicating whether or not the level is below a certain level is added to each signal sound data in the continuous signal memory, and when the read address is rewritten, the low level signal is referred to Only when it is a level, rewriting is possible.

[Operation] Inside the continuous signal memory 1, a low-level detection signal (representing whether or not it is low level is represented by 1 bit) 11 corresponding to each sampled data 10 of continuous signal or silence is provided for each data. The data 10 is written in the signal temporary accommodating memory 2 while the low level detection signal 11 is supplied to the read address accommodating memory 4 when the contents are read out.

The content of rewriting of the read address (the read address that is rewritten corresponding to the interruption) from the interrupt control unit 6 at any time is stored in the read address temporary storage memory 5. The read address to be rewritten accommodated in the read address temporary accommodating memory 5 is rewritten when the low level detection signal of the signal sound to be rewritten in the read address accommodating memory 4 displays the low level section. If it is not in the low level section, rewriting is prohibited until the low level section, and rewriting is permitted after the low level section.

When each signal read from the temporary signal accommodating memory 2 by the read address accommodating memory 4 is converted into a serial signal in the parallel-serial converter 3, and each time slot includes each sample data of various signals as in the conventional case. It is output as a division multiplexed signal.

In this way, it is possible to minimize noise such as clipping sound that occurs when signals are switched.

[Embodiment] FIG. 2 is a block diagram of an embodiment, FIGS. 3 (a) and 3 (b) are examples of data stored in each memory, and FIG. 4 is an example of waveforms and low-level detection signals. , FIG. 5 shows an example of the waveform of the intermittent control for the audible signal sound, and FIG. 6 shows an example of the switching operation according to the present invention.

In FIG. 2, 20 is a step counter that generates an address for reading the continuous signal accommodating ROM, 21 to 26 correspond to the respective units 1 to 6 in FIG. 1, 21 is a continuous signal accommodating ROM, 2
2 is a temporary signal accommodating memory, 23 is a parallel / serial converter (indicated by P / S), 24 is a read address accommodating memory, 25 is a read address temporary accommodating memory, and 26 is an intermittent control unit.

In the continuous signal accommodating ROM 21, as shown in A. of FIG. 3A, the sampling data 210 of each audible signal sound and a low level detection signal indicating a low level section indicating whether the level of each data is low level or not. 211 is contained for each data, one bit for each data. In this example, the bit of the low-level detection signal is "0", and the bits of the other sections are "1".

This relationship will be described with reference to the waveform of FIG. 4 and the row of low-level detection signals. In FIG. 4 (a), the data of each sample value of the audible signal is shown in an analog image, and the level (0 If the section below the positive and negative levels 1) is set to the low level and the other sections are set to the high level, the bit value of the low level detection signal becomes a value as shown in FIG. 4 (b).

In FIG. 2, the contents of the continuous signal accommodating ROM 21 are incremented and read by the increment counter 20, and the sampling data 210 of each frequency is stored in the temporary signal accommodating memory 22 by one.
The low-level detection signal 211 is stored for each sample period, and a bit corresponding to one sample is supplied to the read address accommodating memory 24.

Sampling data for one sample is temporarily stored in the signal temporary accommodating memory 22 as shown by B. in FIG. 3 (a), and is randomly stored at the address specified by the read address accommodating memory 24. Irrelevant) and time-division-multiplexed to parallel-serial converter 23
Is converted to a serial signal and output.

The read address accommodating memory 24 is A. of FIG. 3 (b).
As shown in FIG. 5, the address necessary for creating each signal is stored, and when the audible signal is interrupted, the read address of each frequency is rewritten to a silent pattern.

Rewriting of the address is performed by temporarily accommodating the address data output from the interrupt control unit 26 in the read address temporary accommodation memory 25 and writing the output in the read address accommodation memory 24.

When the read address accommodating memory 24 is rewritten, if the bit of the low level detection signal 211 supplied from the continuous accommodating ROM 21 is "0" indicating the low level section, rewriting is possible, but " When it is 1 ", it functions as a rewrite inhibit signal. If prohibited, rewriting is executed after waiting for the low level section.

The intermittence control unit 26 controls the intermittence control ROM 262 accommodating the intermittence control signal, the increment counter 261 for incrementing the increment / decrement control signal, and the increment counter 261 when it is not necessary to rewrite the read address of the temporary signal accommodating memory 22. It is composed of a stop counter 263 which is kept stopped and a monitoring circuit 264 which monitors the control thereof.

The intermittent control ROM 262 stores the contents as shown in B. of FIG. 3 (b). At each address position, the read address rewriting data, the stop counter control data, or the A control bit indicating the content of control such as whether the binary counter is reset data is accommodated. Next, in the case of rewriting data of the read address, the address of the read address temporary accommodation memory 25 and the read address which is the data to be written. (DT signal address, BT signal address, etc.) is stored, and in the case of stop counter control data, start data (load value) and load signal are used as stop step stop counter and stop counter 263 control data. In the case of the step counter reset data, a control signal for instructing the step counter reset is stored.

FIG. 5 shows an example of waveforms and control contents of the intermittent control by the intermittent control ROM 262.

Fig. 5 shows examples of dial tone (DT tone), busy tone (BT tone) and ringing tone (RBT tone). DT tone is a continuous tone, but like BT tone and RBT tone. When the ON time and the OFF time are defined respectively, the read address is rewritten from the intermittent control ROM 262 to the read address temporary accommodation memory 25 at each switching point. In the example in the figure, the BT sound is repeatedly turned on for 0.5 seconds and turned off for 0.5 seconds, and the RBT sound is turned on for 1 second and turned off for 2 seconds.

At the time of this on / off switching, a stop counter 263 of the intermittent control unit 26 of FIG. 2 is provided to control the on time (audible signal data generation time) and off time (silent pattern data generation time). There is.

In the intermittent control unit 26, when the step counter 261 reads addresses 0 to 31 of the intermittent control ROM 262, the monitoring circuit 264
The control bit is identified by and the read address of the signal temporary accommodation memory 22 is initialized in the read address temporary accommodation memory 25. For a signal that is not intermittent like a continuous signal, the read address is not changed until the end position of the address of the intermittent ROM 262 (the address n of the ROM shown in B. of FIG. 3B).

After that, whether the read control bit of the intermittent control ROM 262 is rewritten by the monitoring circuit 264, the stop of the step counter 261 and the stop counter 263 are started,
Alternatively, it is determined whether the step counter 261 is reset. When indicating a read address rewrite request, the write address of the read address temporary storage memory 25 and the data to be written are output.

During the stop counter control, the interrupt control ROM 262 outputs the stop instruction and the stop counter load value of the step counter 261 and the monitoring circuit 264 determines the read control bit to stop the step counter 261 (step). Stop counter 263
A load signal is output to, the load value (stop time value) is loaded into the stop counter 263, and the count operation is started. When the stop counter 263 reaches the time of the loaded value, the count end output is input to the monitoring circuit 264. Then, the monitoring circuit 264 starts the stepping operation of the stepping counter 261 to read the next address.

When the control bit of the intermittent control ROM 262 is a reset request for the step counter, the step counter 261 is reset, and reading is started again from the address 0 of the intermittent control ROM 262.

FIG. 6 shows an example of the switching operation according to the present invention. As shown in the figure, by switching with the low-level detection signal, intermittent switching is performed in the low-level section of the audible signal, so that the click waveform that becomes noise does not occur in the waveform shown in the analog image.

[Effects of the Invention] According to the present invention, it is possible to reduce noise such as a click sound generated when switching the intermittent control of the audible signal sound in the digital telephone exchange system.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment, FIGS. 3 (a) and 3 (b) are examples of data stored in each memory, and FIG. 4 is a waveform. And example of low level detection signal,
FIG. 5 is a waveform example of intermittent control for an audible signal sound, FIG. 6 is an example of switching operation according to the present invention, FIG. 7 is a configuration diagram of a conventional example, and FIG. 8 is data and a waveform diagram of the conventional example. In Fig. 1, 1: continuous signal memory 2: temporary signal storage memory 3: parallel-serial converter 4: read address storage memory 5: read address temporary storage memory 6: intermittent control unit

Front page continuation (72) Kenji Fujiwara, Kenji Fujiwara, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (56) References JP-A-2-277370 (JP, A) JP-A-63-280560 (JP, A)

Claims (2)

(57) [Claims] 1. A continuous signal memory in which continuous or silent sample data of a plurality of types of audible signals are stored for a certain time or more, and each sample data is stored in a signal temporary storage memory at each sample time period, The sample data of a large number of time-division multiplexed audible signals are output to each time slot by reading the sample data from each address of the signal temporary accommodation memory, and the read address of the signal temporary accommodation memory is controlled by the intermittent control unit. In the digital audio signal interruption control method for controlling the interruption of the audio signal by changing it, it is determined whether or not the sample data corresponds to each sample data of the continuous signal memory and is a low level section of the audio signal. A signal representing the audible signal sound is stored in the temporary signal accommodating memory under the control of the intermittent control unit. When an instruction to change the read address of the data is generated, the signal representing the low level section added to the corresponding sample data read from the continuous signal memory to the signal temporary accommodation memory is identified to identify the signal temporary accommodation memory. A digital audio signal interrupt control method characterized by controlling a change of a read address. 2. The read address temporary storage memory according to claim 1, wherein the read address of the signal temporary storage memory is stored at each address, and the read address is changed by a rewriting instruction from the intermittent control unit; A read address accommodating memory for performing rewriting according to the contents written in the address temporary accommodating memory and reading the signal temporary accommodating memory, and when storing sample data from the continuous signal memory to the signal temporary accommodating memory, A signal representing the low level section of each read sample data is supplied to the read address accommodating memory, and the read address temporary accommodating memory transfers the read address accommodating memory to the read address accommodating memory only when the signal indicates the low level section. Characterized by rewriting the address Digital audio signal tone off control scheme.