JP2552216Y2 - IC test equipment - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus for testing whether an IC having an I / O terminal operates normally.

[0002]

2. Description of the Related Art FIG.
2 shows a connection portion between a test apparatus and an IC under test. The conventional IC test apparatus has a structure in which the output terminal of the driver 10 and the input terminal of the comparator 11 are connected in common, and the common connection point and the I / O terminal of the IC under test 13 are connected by a cable 12.

The driver 10 performs an operation of supplying a test pattern signal to an IC under test. When the response signal output from the IC under test 13 has a normal logic level, the comparator 11 performs an operation of taking the response output signal into the IC test apparatus. The IC under test 13 is supported by a specimen support plate 14 called a performance board. The driver 10 and the comparator 11 are mounted on a board 15 called pin electronics. The pin electronics 15 and the performance board 14 are connected by a cable 12, and the cable 12
And the driver 10 and the comparator 11 are connected.

The input terminal of the comparator 11 is a driver 1
0 output terminal. The driver 10 uses a three-state type amplifier having an output terminal function, and is controlled to a high impedance state in addition to outputting the H logic level and the L logic level of the test pattern signal. While the output terminal of the driver 10 is controlled to a high impedance state, the IC under test 13 operates using the terminal as an output terminal, outputs a response signal to the cable 12, and the comparator 11 takes in the response signal. The comparator 11 is an IC under test 13
It is checked whether the logic level of the response signal output by the device falls within the normal voltage range. The comparator compares the expected value pattern signal with the expected value pattern signal, detects a match or mismatch, and tests whether the IC under test 13 is operating normally.

[0005]

When tested IC13 [devised is to solve the above outputs a response signal, the response signal is input delayed by a delay time T ₁ of the cable 12 to the input terminal of the comparator 11. Therefore, the timing at which the driver 10 can output the next test pattern signal is determined by the comparator
This is the timing after all the response output signals output by C13 are taken. As a result, the cycle of the test pattern signal output from the driver 10 cannot be shortened by the delay time of the cable 12, and the high-speed pattern signal is
13 cannot be applied. That is, the upper limit of the test speed is limited, and there is a disadvantage that a high-speed test cannot be performed.

FIG. 5 shows this state. Figure 5A shows a test pattern signal P _A to be output from the driver 10. FIG. 5B
Indicates a test pattern signal P _B sent to the terminal portion of the IC under test 13. 5A and 5B have a phase difference of the delay time T ₁ of the cable 12. Figure 5C shows the response output signal P _C output to the terminal of the test IC 13. The delay time C indicates a response delay time of the IC under test 13.

FIG. 5D shows the waveform of the input terminal of the comparator 11. Cable from the response signal P _C shown in FIG. 5C 1
Only 2 of the delay time T ₁ delay applied to the input terminal of the comparator 11. Consequently the driver 10 can not be the signal P _D shown in FIG. 5D unless a timing after falling of outputting a next test pattern signal P _A. Thus the period of the test pattern signal P _A is at least a cable 12
2T ₁ to twice 2T ₁ the delay time T ₁ of the addition of the response delay time of the tested IC 13 C and pulse width 2W of two pulses
+ C + 2W.

[0008]

In this invention, the input terminal of the comparator is directly connected to the terminal side of the IC under test, that is, the performance board via a cable and a buffer amplifier.
The signal input port of the comparator is separated from the output terminal of the driver. The driver is High, Low level.
A ternary driver that can generate _VTT in addition to the bell is used. IC under test Ru final outputs a response signal according to the construction of this invention
More simply faster timing delay time of the cable T _1, be output the next test pattern signal from the driver under test
The test pattern signal output from the driver and the response signal output from the IC under test do not overlap at the input / output end of the IC, that is, at the comparator signal input port . As a result, the cycle of the test pattern signal can be shortened, a high-speed test pattern can be applied to the IC under test, and a high-speed test and a reduction in test time can be realized.

[0009]

FIG. 1 shows an embodiment of the present invention. In this invention, the input terminal of the comparator 11 is disconnected from the output terminal of the driver 10 and is directly connected to the terminal side of the IC under test 13 through the second cable 16 and the buffer amplifier 17. At the same time, the driver 10 uses a ternary driver. A ternary driver in addition to the H logic level and the L logical level of the test pattern signal, it is possible to output a termination voltage V _TT defined by the standard of the test IC 13. Termination voltage V
_TT generally has an H logic level of +5 V and an L logic level of 0 V
At this time, V _TT規定 1.73 V is defined.

After the driver 10 outputs the test pattern signal, by maintaining the potential of its output terminal at about V _TT ≒ 1.73 V, when the cable 12 is viewed from the IC 13 side, the driver 10 It looks equivalent to a resistance and is maintained in a state where impedance matching has been achieved. Therefore, reflection does not occur at the end of the cable 12 (on the driver side), and waveform distortion is reduced.

According to the present invention, the comparator 11
Was changed to the IC under test 13 side,
The output of the next test pattern signal can be started at a timing earlier by the delay time of the cable 12 than when the IC under test 13 finishes outputting the response output signal. This will be described with reference to FIG. Figure 2A shows a test pattern signal P _A that is output from the driver 10. If the test pattern signal P _A is output, the test pattern signal P _A reaches the terminal under test IC13 shown in Figure 2B Upon expiration of the delay time T ₁ of the cable 12. Tested IC13 outputs a response signal P _C after a time C. Response signal P _C
Following the outputting of the test pattern P _A from the front timing than the timing t ₀ of the fall delay time T ₁ of the cable 12, the test pattern signal P _A cable 12
At a timing of reaching the terminal under test IC13 through the response signal P _C is falling at a timing t _0, it is taken to a comparator 11. Be output the next test pattern signals P _A in W-T ₁ only timing earlier than the timing t ₀ without waiting for the fall of the result response signal P _C, to the test pattern signal P _A response signal P _C There is no overlap. After all, according to this invention, the test pattern signal P _A
Can be set to C + 2W, the delay time of the cables 12 and 16 can be shortened by 2T ₁ minute, and the test speed can be increased.

[0012]

As described above, according to the present invention, the signal input port of the comparator 11 is connected to the driver 10.
Separately from the from taken to the terminal side of the test IC 13, the test pattern signal P _A period the delay time of the cable 12 of the T
₁ of two pins, can be shortened by 2T _1. As a result, the test can be sped up and the time required for the test can be shortened.

FIG. 3 shows a modified embodiment of the present invention. In this example, an example in which a resistor R is connected in series to the input / output terminal of the IC under test 13 is shown. The resistor R is mounted on performance board 14, used in the case of standard capacity is small in the output current of the test IC 13 IC.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the present invention.

FIG. 3 is a connection diagram showing a modified embodiment of the present invention.

FIG. 4 is a connection diagram for explaining a conventional technique.

FIG. 5 is a waveform chart for explaining the operation of the conventional technique.

[Explanation of symbols]

 Reference Signs List 10 driver 11 comparator 12, 16 cable 13 IC under test 14 performance board 15 pin electronics

Claims (1)

(57) [Scope of request for utility model registration] An I / O switchable between an input terminal and an output terminal.
In an IC test apparatus for testing an IC having an O terminal, a test pattern signal is supplied to an IC under test through a first cable, and a test pattern signal is output in addition to an H logic level and an L logic level defining the amplitude of the test pattern signal. A ternary driver that can apply a termination voltage determined by the test IC standard to each terminal of the IC under test, a buffer amplifier that takes out a response signal output from the IC under test near the terminal of the IC under test, The second to take the output of the buffer amplifier into the comparator
An IC testing device comprising: a cable;