JP2550861B2 - ECL type logic circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ECL (emitter coupled logic) type logic circuit, and more particularly to a current control and a logic threshold value control system in an ECL type logic circuit.

[0002]

2. Description of the Related Art An example of a conventional ECL type logic circuit is shown in FIG. This circuit includes a pair of differential pair transistors 33 and 34.
And a constant current source composed of a transistor 35 and a resistor 36 for supplying a current to the emitter coupling portion of the differential pair transistor, and collector load resistors 31 and 32 of the differential pair transistors 33 and 34.

The current value of this constant current source is the transistor 3
Reference voltage generation circuit (not shown) connected to the base of No. 5
Is determined by the constant current control voltage value from the emitter resistor 36 and the value of the emitter resistor 36. The value of the resistor 36 is selected by the current value according to the signal propagation delay amount required at the time of design.

At this time, since the output voltage V0 obtained at the emitter follower output section (transistor 37 and resistor 38) fluctuates due to the setting of the current value, the differential pair transistors 33 and 34 have their respective outputs for the purpose of correcting it. The values of the collector load resistors 31 and 32 are determined in conjunction with the value of the resistor 36 of the constant current source.

Another structure for changing the current value of the constant current source of the ECL type logic circuit is disclosed in Japanese Patent Laid-Open No. 63-126316.
There is one disclosed in the publication, and FIG. 5 shows its circuit. This circuit includes a pair of differential pair transistors 41,
42, collector resistors 39 and 40, and a constant current source 43, and a switch 44 for turning on / off the current of the constant current source 43 is provided. The switch 44 is controlled by a control voltage generation circuit 46 that generates an on / off control voltage by an external control signal 45.

In this ECL logic circuit, unnecessary current consumption is prevented from occurring when the output signal of the circuit is not required to be referred to by the circuit in the subsequent stage.

[0007]

In the circuit shown in FIG. 4, it is impossible to change the setting of the current value suitable for the required signal propagation delay at the time of designing and manufacturing. Yes, it is not possible to switch the current value setting especially during operation.

In the circuit shown in FIG. 5, the current value can be controlled, but there are only two types, that is, ON and OFF, and the control for setting the minimum current value according to the required signal propagation delay time. Is impossible.

As described above, the conventional circuit configuration has a drawback that the current value cannot be optimized according to the propagation delay time required for the logic gate.

An object of the present invention is to provide an ECL type logic circuit capable of optimizing a current value according to a propagation delay time required for a logic gate.

Another object of the present invention is to provide an ECL type logic circuit which enables the optimization of the current and is not affected by the fluctuation of the logic level due to the current setting.

[0012]

An ECL type logic circuit according to the present invention comprises a pair of differential pair transistors, a current source for supplying a current to an emitter coupling portion of the differential pair transistors, and the differential pair. For one base of the transistor
Reference voltage that supplies the reference voltage to determine the logical threshold
And a reference voltage of the reference voltage generating means.
It can be changed from the outside so that the logic threshold value can be controlled.
Characterized in that the.

[0013]

[0014] Another ECL-type logic circuit Ru good to the present invention includes a pair of differential pair transistors, a first ECL-type and a current source for supplying a current to the emitter junction of the differential pair transistors A second circuit having a logic circuit, a pair of differential pair transistors driven by the output of the first ECL type logic circuit, and a current source for supplying a current to the emitter coupling portion of the differential pair transistor. An ECL type logic circuit, and a control means for controlling the current value of the current source of the first ECL type logic circuit and the reference voltage value for defining the logic threshold value of the second ECL type logic circuit in cooperation with each other. It is characterized by

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
A current source 3 supplies a current to the emitter coupling portions of the pair of differential pair transistors 1 and 2. The current value of the current source 3 is freely changeable, and the current value is variable according to the control voltage from the control voltage generating circuit 8. The control voltage generating circuit 8 can change the control voltage by a control signal 9 from the outside.

Reference numerals 4 and 5 are collector resistors of the transistors 1 and 2, and reference numerals 6 and 7 are differential inputs.

FIG. 2 is a circuit diagram of another embodiment of the present invention. A constant current source 13 supplies a constant current to the emitter coupling portions of the pair of differential pair transistors 11 and 12. A reference bias voltage is applied from a reference voltage generating circuit 18 to the base of one of the differential pair transistors 11 and 12, and the reference bias voltage can be changed by a control signal 19 from the outside. ing.

FIG. 3 is a circuit diagram of another embodiment of the present invention, which is a logic circuit formed by combining the ECL type logic circuits of FIGS. In FIG. 3, the same parts as those in FIGS.

The output of the ECL type logic circuit of FIG. 1, that is, the collector output of the transistor 2 is passed through the emitter follower circuit (transistor 20, resistor 21) to the ECL of FIG.
It is said to be the input of the type logic circuit. Then, the current control of the current source 3 and the base reference bias control of the transistor 12 are performed by the control circuit 22 in cooperation with each other. The control in this case is commonly performed by a control signal 23 from the outside.

Now, when the current value control voltage generated from the control circuit 22 is changed by the external control signal 23, the current value of the current source 3 is changed accordingly, and as a result, the ECL type logic circuit of the preceding stage is changed. In particular, the low level of the logic output (collector output of the transistor 2) changes. As a result, the logic level (low level) input to the base of the transistor 11 of the ECL type logic circuit in the subsequent stage changes, but the differential pair transistors 11 and 12 are changed.
Control circuit 22 uses the transistor 1 so that
It operates so as to change and control the two base bias voltages at the same time.

That is, by controlling the current value of the ECL circuit in the preceding stage to an optimum value in accordance with the required signal propagation time, at the same time controlling the logical threshold value of the ECL circuit in the succeeding stage. The correct operation is possible as a whole circuit.

[0023]

As described above, according to the present invention, EC
The current value of the constant current source of the L-type logic circuit can be changed freely, and the logic threshold value can be changed simultaneously. By controlling both of them simultaneously, the optimum current according to the propagation delay time required for the logic gate can be obtained. There is an effect that the value can be set and the influence of the change of the logic level can be eliminated.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

FIG. 4 is a diagram showing an example of a conventional ECL type logic circuit.

FIG. 5 is a diagram showing another example of a conventional ECL type logic circuit.

[Explanation of symbols]

 1,2,11,12 Differential pair transistor 3,13 Current source 4,5,14,15 Resistor 6,7,16 Differential input 8 Control voltage generation circuit 9,19,23 External control signal 18 Reference voltage generation circuit 22 Control circuit

Claims (2)

(57) [Claims] 1. A pair of differential pair transistors, a current source for supplying a current to an emitter coupling portion of the differential pair transistors, and a logic threshold value for defining one of the bases of the differential pair transistors. and a reference voltage generating means for supplying a reference voltage, and controls the logic threshold to freely change the reference voltage of the reference voltage generating means from the outside
An ECL type logic circuit characterized by the above . 2. A first ECL type logic circuit having a pair of differential pair transistors and a current source for supplying a current to an emitter coupling portion of the differential pair transistors, and the first ECL type logic circuit. A second ECL type logic circuit having a pair of differential pair transistors driven by the output of the circuit, and a current source for supplying a current to the emitter coupling portion of the differential pair transistors; and the first ECL. An ECL-type logic circuit, comprising: a control unit that controls a current value of a current source of the type-logic circuit and a reference voltage value that determines a logic threshold value of the second ECL-type logic circuit in conjunction with each other.