JP2546279B2 - Variable amplitude equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a variable amplitude equalizer for compensating for the amplitude characteristics of a digital signal transmitted by a cable or the like, and it is possible to realize a variable IC equalizer. The present invention relates to an amplitude equalizer.

[Outline of Invention]

According to the present invention, a capacitor forming emitter peaking of a differential amplifier is composed of a Miller integrator, and a multiplier capable of arbitrarily controlling a multiplication coefficient is used as an amplifier of the Miller integrator, so that a capacitor having a small capacitance value is obtained. None, which allows the variable amplitude equalizer to be integrated into an IC.

[Conventional technology]

When a digital signal such as image data is transmitted by a long-distance cable, amplitude distortion and delay distortion are generally generated. Therefore, there is a need for an equalizer to correct these distorted waveforms at the receiving end to reproduce the digital signal at the transmitting end without error.

Fig. 4 shows the frequency characteristics with respect to the cable length L (L ₃ <L ₂ <L ₁ ) when the transmission line is a coaxial cable. The attenuation γ is generally approximated by the following equation. It

However, L: cable transmission length α, β: constant f: transmission frequency That is, the longer the cable length L, the greater the attenuation of the high frequency component of the signal. For example, when a single pulse of clock cycle T is transmitted. As shown in FIG. 5, when the line is long (L ₃ ), the waveform S ₃ has a widened pulse width.

Therefore, an amplitude equalizer is provided at the receiving end, and the received waveform is corrected to a waveform that becomes 0 at an integral multiple of the period T as shown in S ₂ to reduce the error rate due to intersymbol interference. Waveform equalization is performed in the case where the fixed amplitude equalizer is used when the transmission cable length becomes short (L ₁ )
Becomes a received waveform as seen in waveform S ₁ , and the error rate becomes high again due to intersymbol interference.

Therefore, conventionally, it has been considered to perform variable amplitude equalization in a transmission system in which the transmission path length is not constant and the amplitude distortion is not fixed. (HwBode: BSTJ, 17, PP.229〜244
Variable Equalizers) Figure 3 is shows a circuit example of variable amplitude equalizer, Z ₁
(Ω) is a first time constant circuit, and Z ₂ (ω) is a second time constant circuit.

Since the first time constant circuit Z ₁ (ω) is capacitive and is connected to the collector side of the transistor Q, the first time constant circuit Z ₁ (ω) operates as a filter that suppresses the frequency on the high frequency side, and the second time constant circuit Z ₁ (ω) _{Since 2} (ω) is connected to the emitter side of the transistor Q, it has a filter characteristic that raises the frequency on the high frequency side with respect to the output S _out . Therefore, if the resistance values of the variable resistors r ₁ and r ₂ connected in series to these time constant circuits Z ₁ (ω) and Z ₂ (ω) are changed in the opposite direction, the signal at the input terminal S _in Only the high frequency characteristic can be changed, and the received waveform can be equalized into a waveform with little intersymbol interference as shown by the waveform S ₂ in FIG.

In this case, by automatically selecting the control values of the variable resistors r ₁ and r ₂ in accordance with the cable length, it is possible to perform amplitude equalization within a range of ± ΔL around the cable length L. .

[Problems to be solved by the invention]

Since the variable resistors r ₁ and r _{2 in} the circuit example of FIG. 3 are used in a high frequency region, it is necessary to use a variable resistor circuit using, for example, a PIN diode, and the time constant circuit Z ₁ (ω), Z ₂
Since (ω) needs to be configured by an impedance element having a value that cannot be integrated into an IC, it is externally attached to the transistor Q. Therefore, the circuit example of FIG. 3 has a problem that it is difficult to form an IC.

[Means for Solving Problems] The variable amplitude equalizer of the present invention is made in order to solve such problems, and uses a capacitor having a small capacitance value formed on the wafer of the IC. However, in order to obtain a predetermined time constant, the Miller integrator circuit is adopted, and the gain of the Miller integrator circuit is controlled by controlling the multiplication coefficient with a voltage by providing an IC-based multiplier circuit. The frequency-amplitude characteristic of is obtained.

[Action]

It is known that the apparent capacitance value of the capacitor connected to the Miller integrator circuit is the gain of the Miller integrator circuit.

That is, since the apparent capacitance value of the capacitor connected to the Miller integrating circuit can be changed by changing the gain of the Miller integrating circuit, the time constant of the time constant circuit composed of this capacitor can also be changed. it can.

Therefore, the present invention changes the gain of the Miller integrator circuit according to the length of the cable so that the amplitude distortion of the cable transmission signal can be equalized by using a capacitor having a small capacitance value.

Furthermore, since the Miller integrator circuit is composed of a multiplication circuit that can control the multiplication coefficient according to the magnitude of the control voltage, the time constant can be easily changed.

〔Example〕

FIG. 1 is a circuit showing an embodiment of an IC-equipped variable amplitude equalizer of the present invention, in which a digital signal transmitted by a cable is a transistor Q ₁ , which is differentially connected from input terminals IN ₁ and IN ₂ . Applied to the base of Q ₈ .

The emitters of the transistors Q ₁ and Q ₈ are respectively connected to the bases of the transistors Q ₂ and Q ₉ which are differentially connected, and are also connected to the collectors of the transistors Q ₆ and Q ₁₃ which are current sources.

Further, the emitters of the transistors Q ₁ and Q ₈ are capacitors C ₁ and C ₂ and a transistor Q ₁ which form part of the time constant circuit.
Inter-emitter resistors R ₁₀ for differentially operating ₁ and Q ₈ are respectively connected, and load resistors R ₁ and R ₂ are respectively connected to the collectors of the power supply lines.

The collector of transistor Q ₂ is connected to the commonly connected emitters of transistors Q ₃ and Q ₄ , and the collector of transistor Q ₉ is similarly connected to the commonly connected emitters of transistors Q ₁₀ and Q ₁₁ . And the transistors Q ₃ and Q
₁₁ collectors are connected together and connected to power supply V _CC through resistor R _3.
And the collectors of the transistors Q ₄ and Q ₁₀ are also connected in common and connected to the power supply V _CC via the resistor R ₄ .

Further, the connection point between the resistor R ₃ and the collectors of the transistors Q ₃ and Q ₁₁ is connected to the base of the transistor Q ₅ , and the emitter thereof is connected to the other end of the capacitor C ₁ .

Similarly, the connection point between the resistor R ₄ and the collectors of the transistors Q ₄ and Q ₁₀ is connected to the base of the transistor Q ₁₂ , and the emitter thereof is connected to the other end of the capacitor C ₂ .

The collectors of the current source transistors Q ₇ , Q ₁₄ , and Q ₁₅ that supply current to the above transistors are respectively transistor Q ₅
Connected to the common emitter of the transistors Q ₂ and Q _{9 and} the emitter of the transistor Q ₁₂ to supply a current determined by the voltage value of the terminal IC and the values of the resistors Q ₆ , Q ₇ and Q ₈ to the respective transistors. ing.

The control voltage input terminals E _C and E _C ′ are the transistors Q ₃ and
This input terminal is connected to the commonly connected base of Q _{10 and} the commonly connected bases of transistors Q ₄ and Q _11.
The gain of the multiplier can be controlled according to the input voltage values of E _C and E _C ′.

Multiplier transistor Q ₂ to Q _4, is composed of Q ₉ to Q _12, the input of the amplifying transistor Q _2, Q ₉ of the differential pair gain is variable by capacitors C _1, C ₂ the multiplier And the output are connected via the buffer transistors Q ₅ and Q ₁₂ . Therefore, the apparent capacitance values C _i1 and C _i2 of the capacitors C ₁ and C ₂ are C _i1 = C ₁ (1 + KA) (2) C _i2 = C ₂ (1 + KA) (3) due to the Miller effect. A: Maximum gain of multiplier K: Coefficients (1 to 0) controlled by input terminals E _C and E _C ′. Since the apparent capacitance values C _i1 and C _i2 of the capacitors form the emitter peaking circuit of the transistors Q ₁ and Q ₈ together with the resistor R ₁₀ , the frequency characteristics F ₁ (ω of the output terminals OUT ₁ and OUT ₂ ) ・ F ₂ (ω) is Then, by setting R ₁ = R ₂ and C ₁ = C ₂ , the output terminal OUT
The frequency characteristics of the signals output to ₁ and OUT ₂ are equal.

As is clear from the expressions (4) and (5), the capacitor
If the capacitance value of C ₁ and C ₂ is increased, the high-frequency characteristics will be raised, and if K is changed, the frequency characteristics of the variable amplitude equalizer will change as shown in Fig. 2, depending on the cable length. If K is changed, it is possible to equalize the waveform as shown by the waveform S ₂ in FIG. 5 with less intersymbol interference.

 Next, the operation of the circuit example of FIG. 1 will be described.

The alternating signal applied to the input terminals IN ₁ and IN ₂ is amplified by the differential amplifier composed of the transistors Q ₁ and Q ₈ , and the output terminal OUT
₁ and OUT ₂ are differentially output. The gain characteristics of the differential amplifier are the ratio of the resistance R ₁₀ connected between the emitters and the load resistances R ₁ and R ₂ , and the capacitors C ₁ and C connected to the emitters, respectively.
_{In step 2} , it is determined by the above equations (4) and (5).

The multiplier consisting of the transistors Q _{2 to} Q ₄ and Q _{9 to} Q ₁₁ is of the differential type, and the differential signal voltage applied between the bases of the transistors Q ₂ and Q ₉ and the control voltage input terminal E _C , E _C ′ and the voltage applied between them are output from the collector side of the resistors R ₃ and R ₄ . That is, the voltage input between the input terminals E _C and E _C ′ determines the gain of the differential input applied between the bases of the transistors Q ₂ and Q ₉ . In other words, the gain of the multiplier can be arbitrarily set by the voltage applied between the input terminals E _C and E _C ′.

The capacitors C ₁ and C ₂ are connected to the transistors Q ₅ and
Since it is controlled between the base and collector of the multiplier via Q ₁₂ , it becomes a so-called Miller integrating circuit, and the capacitance values of the capacitors C ₁ and C ₂ are the emitters of the transistors Q ₁ and Q ₈ and the gain of the multiplier. It will be added as a capacitor having a doubled apparent capacitance value.

Then, since this capacitor acts as emitter peaking, increasing the capacitance value increases the gain on the high frequency side of the differential amplifier including the transistors Q ₁ and Q _8, and increasing the capacitance value, on the contrary, increases the differential amplifier The gain on the region side becomes smaller.

That is, if this variable amplitude equalizer is connected to the output end of the cable and the applied voltage between the input terminals E _C and E _C ′ is controlled according to the cable length, the desired equalization characteristic can be obtained.

The transistors _{Q 6, Q 7, Q 13} ~Q 15 is a constant current source, a current determined by the resistor connected to a stable voltage applied to the terminal IC and the emitter of each transistor is connected Supply to each circuit part.

When the circuit of the present invention is integrated into an IC, capacitors C ₁ and C ₂
1 to 10 _PF is sufficient, and the maximum gain of the multiplier can be about 20 dB.

When the transmission characteristic of the cable is compensated by the variable amplitude equalizer of the present invention, equalization is performed in which two or three variable amplitude equalizers having different peaking characteristics are cascade-connected to more closely approximate the transmission characteristic of the cable. It is preferable to use a container.

〔The invention's effect〕

As described above, in the variable amplitude equalizer of the present invention, by creating the Miller integrator circuit in the IC circuit, it becomes possible to obtain a predetermined time constant even with a capacitor having a small capacitance value. By using it, the time constant can be controlled by changing the applied voltage, so external components can be eliminated and circuit elements that can be created on the IC wafer are used. However, since these circuit elements are arranged differentially to form the variable amplitude equalizer, there is an effect that stable operation is possible even in a high frequency region without secular change.

[Brief description of drawings]

1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a characteristic diagram of a variable amplitude equalizer of the present invention, FIG. 3 is a circuit diagram of a conventional variable amplitude equalizer, and FIG. 4 is a cable. FIG. 5 is a transmission characteristic diagram of FIG. In the figure, Q _{1 to} Q ₁₅ are transistors, C ₁ and C ₂ are capacitors, and R _{1 is}
~ R ₉ is a resistance, Z ₁ (ω), Z ₂ (ω) are time constant circuits, E _C , E _C ′
Indicates an input terminal for control.

Claims (1)

(57) [Claims] 1. A first differential amplifier comprising a pair of transistors, whose emitters are connected to each other via a resistor, and an input signal is supplied to each base, and a pair of transistors of the first differential amplifier. The emitter output signal is applied to the pair of first input terminals, and the signals from the multiplier having the pair of second input terminals as control terminals and the pair of output terminals of the multiplier are respectively applied to the first differential signal. Equipped with a feedback circuit consisting of a transistor and a capacitor that feed back to each emitter of the amplifier,
A variable amplitude equalizer, characterized in that a control signal is supplied to a second input terminal of the multiplier to obtain a variable amplitude signal from each collector of the first differential amplifier.