JP2546223B2 - Timing adjustment device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an index signal of a magnetic disk device such as a floppy disk device (hereinafter referred to as FDD) or a hard disk device (hereinafter referred to as HDD) or an optical disk device, and a video tape recorder (VTR). The present invention relates to a timing adjusting device for the PG signal and the like.

[0002]

2. Description of the Related Art Conventionally, in a magnetic disk device such as an FDD, an index signal of one pulse is generated for one rotation of the disk to determine the start of writing a recording track. The timing of this index signal must be generated at a specific rotation angle position of the disk so as to ensure compatibility of the disk.
In the case of DD, it is necessary to include the temperature, the change over time, etc. within an allowable range of ± 0.72 ° (± 400 μsec) with respect to the reference value. However, since an error of about ± 2 ° is usually expected in the mounting accuracy of the index signal generating means for generating the index signal according to the rotation of the disk, the error of the index signal is finally determined by using the timing adjusting device. To obtain the required accuracy.

A conventional timing adjusting device for index signals will be described below. FIG. 9 is a circuit diagram of a conventional timing adjusting device, and FIG. 10 is a flowchart showing its operation. The timing adjustment device 100 includes a transistor Q41, resistors R41 to R45, and a capacitor C4.
1 and a comparator CMP41, and the input index signal is delayed with a time constant determined by the resistor 41 and the capacitor C41. A specific method of timing adjustment is performed by adjusting the delay time by making the resistor R41 variable.

The input index signal of the timing adjusting device 100 generated by the index signal generating means is a negative logic signal which becomes L level in the active state, and its leading edge is the effective timing. That is, while the index signal is at the H level, the transistor Q41 is turned on to discharge the electric charge of the capacitor C41, and the terminal potential of the capacitor C41 becomes approximately zero. On the other hand, during the period when the input index signal is at L level, that is, during the period from the leading edge to the trailing edge of the effective timing, the transistor Q41 becomes non-conductive, the capacitor C41 is charged by the resistor R41, and the terminal potential of the capacitor C41. Vc changes as shown in Equation 1, where t is the elapsed time from the leading edge. Vc = VDD ・ (1-EXP (-t / (C41 ・ R41))) (1)

Further, the comparator CMP41 compares the reference potential V1 determined by the voltage division ratio of the resistors R44 and R45 serving as a threshold with the potential Vc of the capacitor C41, and V1 <
In the Vc portion, the output index signal is at the L level. As a result, the leading edge of the output index signal appears after the delay time Td1 shown in Expression 2 from the leading edge of the input index signal, and the trailing edge of the output index signal appears immediately after the trailing edge of the input index signal. Td = -C41.R41.LN (1-V1 / VDD) (2) That is, the effective leading edge timing is the delay time Td1.
Adjusted by the change of. As shown in Expression 2, the delay time Td1 is proportional to the resistance value of the resistor R41. Therefore, if the resistor R41 is made variable, the timing adjusting device capable of adjusting the effective leading edge timing of the output index signal. Can be easily configured.

[0006]

However, as shown in Expression 2, the delay time Td1 is also proportional to the value of the capacitor C41. Therefore, if the value of the capacitor C41 changes due to, for example, temperature characteristics or aging. Since the delay time Td1 also changes accordingly, the effective leading edge timing of the output index signal also changes. If the change in the timing of the output index signal exceeds the above-mentioned allowable range and becomes large, the compatibility of the disks cannot be obtained. Since the timing of the index signal is defined by the rotational angle position of the disc, the delay time Td1 needs to be changed in inverse proportion to the rotational speed of the disc.
To use by switching between 0 rpm and 360 rpm,
It is also necessary to switch the reference potential V1 which is a threshold value. However, it is difficult to switch the required reference potential V1 with high accuracy even with the control technique, and there is a problem that the timing error of the output index signal when switching the rotation speed becomes large. The present invention has been made to solve such a problem, and an object of the present invention is to provide a timing adjustment device that is stable with respect to temperature and changes with time.

[0007]

To solve the above problems, a timing adjusting device according to the present invention comprises a reference time generating means for generating a reference time, a first current source for generating a first current, and a variable current source. A second current source that generates a second current having a magnitude corresponding to the resistance value of the resistor, and a capacitor that is discharged by the current generated by the first current source at the reference time generated by the reference time generating means. After (charging), charging / discharging control means for controlling the capacitor to be charged (discharged) again with the current generated by the second current source, and an output index signal at a timing corresponding to the terminal potential of the capacitor And a signal generating means for

[0008]

In the timing adjusting device according to the present invention, the delay time of the output index signal is determined by the ratio of the reference time and the resistance, and the generation timing is equivalent to the rotational angular position of the disk.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings. 1 is a block diagram of a timing adjusting device according to a first embodiment of the present invention, FIG. 2 is a circuit diagram thereof, and FIG. 3 is a timing chart showing its operation. The timing adjusting device 1 includes a first current source 2, a reference time generating means 3,
Second current source 4, variable resistor VR1, charge / discharge control means 5,
It is composed of a capacitor C21 and a signal generating means 6. Although one end of the capacitor C21 is grounded in this embodiment, the invention is not limited to this, and it may be connected to a stable potential.

The operation principle of this structure will be described with reference to a timing chart. The terminal potential Vc of the capacitor C21 is initially charged to the reference potential V1. next,
By discharging the reference time Tc1 set by the reference time generation means 3 based on the input index signal by the current I1 generated by the first current source 2, the terminal potential Vc becomes
It decreases by ΔV shown in Expression 3 up to the potential V2. ΔV = Tc1 · I1 / C21 (3)

After that, while the input index signal is at the L level, the reference potential V1 is charged again by the current I2 corresponding to the resistance value of the resistor VR21 of the second current source 4. The time Td2 required for this charging is expressed by Equation 4. Td2 = ΔV · C21 / I2 (4) Here, when Expression 4 is substituted into Expression 3, Expression 5 is obtained. Td2 == Tc1 · I1 / I2 (5) That is, the time Td2 required for charging is the reference time Tc1.
And a current I1 whose value is stable against temperature and changes over time
Is similarly determined by the ratio to the current I2 determined by the resistor VR21 whose value is stable, and is not affected by the value of the capacitor C21.

A clock signal fc which is a reference frequency signal
Is supplied to one input terminal of the NAND gate G21 and D type flip-flops F21 and F22. At the same time, the flip-flops F21 and F22 are
The input index signal is also supplied, and its output signal is input to the AND gate G22. The AND gate G22 generates a reset signal of one cycle width of the clock signal fc synchronized with the leading edge of the input index signal under a predetermined condition, and supplies the reset signal to the reset terminal R of the counter CNT21.
The output signal of the eighth output terminal O8 of the counter CNT21 is inverted by the inverter I21 and the NAND gate G21.
Is supplied to the other input terminal. Therefore, the inverter I
When the signal inverted at 21 is at H level, the counter C
The clock signal fc is supplied to the count input CK of the NT21. The count of this counter CNT21 is 12
When the count reaches eight, the output signal of the eighth output terminal O8 becomes H level, and the other input terminal of the NAND gate G21 is supplied with the L level output signal inverted by the inverter I21. Therefore, the clock signal fc is not supplied to the count input CK of the counter CNT21,
The counter CNT21 stops counting. That is,
During 128 counts (reference time Tc1) from the leading edge of the input index signal, the output signal of the eighth output terminal O8 of the counter CNT21 is at L level, and it is at H level in other periods.

The first current source 2 includes transistors Q21-Q21.
It is composed of Q28 and resistors R22 to R26, and the current I28 shown in Expression 6 flows from the collector to the emitter of the transistor Q28. I28 = R23 × VDD / ((R22 + R23) × R26) (6)

The second current source 4 is a transistor Q.
29-Q34, resistors R27-R30 and variable resistor V
It is constituted by R21, and the current I33 shown in Expression 7 is output from the collector of the transistor Q33. I33 = R28 × VDD / ((R27 + R28) × VR21) (7) Here, R23 / (R22 + R23) = R28 / (R2
7 + R28), the relation of I33 = I28 × R26 / VR21 (8) is derived from the equations (6) and (7), and it is understood that the above-mentioned current ratio is determined by the resistance ratio.

The charging / discharging control means 5 is composed of transistors Q35 and Q36 and resistors R31 to R34, and the eighth output terminal O8 of the counter CNT21 is L.
During the level period, that is, during the reference time Tc1,
The transistor Q35 becomes non-conducting, the capacitor C21 is discharged by the current I1 generated in the first current source 2, and the transistor Q36 becomes non-conducting during the other period, that is, the time Td2, and the second current source 4 The capacitor C21 is charged with the electric current I2 generated in the above.

The signal generating means 6 includes a transistor Q.
37, Q38, resistors R35 to R38, AND circuit G23
And an inverter I22, and a resistor R35.
And R36 applies a constant potential to the base of the transistor Q37. Therefore, the emitter potential, which is higher than the base potential by about 0.7 volt, becomes the reference voltage V1. Capacitor C
If the current generated by the second current source flows through the capacitor C21 even after the potential of 21 reaches the reference potential V1, this current flows through the emitter of the transistor Q37 to the collector and drives the transistor Q38. The collector output of the transistor Q38 and the input index signal are AND-operated by the AND gate G23 having the input negative logic.
It is inverted by the inverter I22 and output.

As a result, the leading edge of the output index signal appears at the timing delayed from the leading edge of the input index signal by the delay time Ts shown in equation 9, and the trailing edge appears at the same time as the trailing edge of the input index signal. Ts = Tc1 + Td2 = Tc1 × (1 + VR21 / R26) (9) From this 9 equation, the delay time Ts is calculated by the resistors VR21 and R2.
It can be seen that it is determined by the resistance ratio of 26 and is not affected by the capacitor C21. The delay time Ts is the reference time Tc.
Since it is proportional to 1, the delay time Ts can be accurately switched by switching the count value of the counter CNT21 and the frequency of the clock signal.

FIG. 4 is a block diagram of the timing adjusting apparatus according to the second embodiment of the present invention, and FIG. 5 is a timing chart showing the operation of this timing adjusting apparatus. In this embodiment, the drive circuit 7 is based on the reference frequency signal and the FG signal.
Is configured to control the rotation speed of the motor 8, and a part of the speed control circuit 9 for controlling the rotation speed is used as the reference time generation means 10 shown in FIG. The reference frequency signal is generated by the reference frequency signal generating means 14 including the oscillation circuit 12 and the frequency division ratio switching circuit 13.
Is generated by.

The FG signal of the motor 8 is waveform-shaped by the FG amplification / shaping circuit 11 and inverted by the inverter I50. The digital signal is composed of the reference frequency signal and the counters CNT51 and CNT52 forming part of the reference time generating means 10. It is configured to be converted into a speed control signal in the mono-multi circuit 15 and to be fed back to the drive circuit 7 via a low pass filter 16 composed of an amplifier, a resistor and a capacitor. The division ratio switching circuit 13 is composed of a counter and a logic circuit, and receives an oscillation signal of the oscillation circuit 12 and a signal indicating the disk rotation speed inverted by the inverter I53. With this configuration, the motor 8 is controlled to have a predetermined rotation speed.

As shown in FIG. 7, the reference frequency signal is generated by the oscillation circuit 12 using the ceramic or crystal oscillator and the frequency division ratio switching circuit 13, converted into a signal of a predetermined frequency, and then the reference time signal. It is supplied to the generating means 10. In the case of this circuit configuration, the frequency of the reference frequency signal generated by the reference frequency signal generating means 14 is set in proportion to the predetermined rotation speed of the motor 8.

In this embodiment, the counter CNT5 forming the digital mono-multi circuit 15 shown in FIG.
At 1, the reference time is generated. Inverter I5 shown in FIG.
The input index signal inverted by 2 is D shown in FIG.
Type flip-flop F51 and is synchronized with the waveform-shaped FG signal. The flip-flop F52 is set at the falling edge of the output signal of the flip-flop F51. That is, the flip-flop F52 is set at the rising edge of the FG signal immediately after the input index signal becomes active (in other words, the output signal of the inverter I52 is at H level). The flip-flop F51 and the flip-flop F52 constitute the charge / discharge control means 17. The counter CNT51 is also reset at almost the same timing and starts counting the reference frequency signal. When the counter CNT51 counts 512 reference frequency signals, the output signal of the output terminal O10 is set to H level, and the flip-flop F52 is reset.

As a result, the flip-flop F52 input to the first current source 18 or the second current source 19 shown in FIG.
The output signal of is at the L level only during the period when the counter CNT51 counts the reference frequency signal for 512, and operates as the reference time Tc2. During the period when the output signal of the flip-flop F52 is at L level, that is, during the reference time Tc2, the amplifier A52, the transistor Q54, and the resistor R5.
The first current source 18 composed of 1 operates to discharge the capacitor C51, and the terminal potential of the capacitor C51 is V11.
To V21. Also, the flip-flop F5
The second current source 19 including the amplifier A51, the transistor Q52, and the resistor VR51 operates during the period when the output signal of 2 is at the H level, that is, during the time Td3, and the terminal potential of the capacitor C51 is charged to V11 again. . In addition, 20 shows a signal generation means.

The current generated by the first current source 18 is proportional to the resistance R51, and the current generated by the second current source 19 is
Since it is proportional to the resistance VR51, the timing of the output index signal can be adjusted by the resistance VR51 as in the first embodiment. Since the reference frequency signal that determines the reference time is proportional to the predetermined rotation speed of the motor 8 as described above, the reference time is also proportional to the predetermined rotation speed. Further, since the delay time is inversely proportional to the rotation speed of the disk, the timing of the index signal is equivalent to the rotation angle position of the disk, and the timing error is small even when the disk rotation speed is switched between 300 rpm and 360 rpm. It is possible to perform stable timing adjustment with respect to temperature and changes over time.

As described above, in this embodiment, a part of the speed control circuit is used as the reference time generating means. Therefore, if these parts are formed on the same IC chip, the timing adjusting device becomes compact as a whole. Can be configured. In this embodiment, the speed control circuit has been described as a digital mono-multi circuit, but it may have another structure including a reference frequency signal and a counter. Further, in this embodiment, charging is performed after discharging at the reference time, but conversely, charging may be performed at the reference time and then discharging, and a time difference may be provided during this charging / discharging. Further, although the reference time is generated in synchronization with the FG signal in this embodiment, it is not always limited to this and may be asynchronous with the FG signal.

[0025]

As described above, according to the timing adjusting apparatus of the present invention, the delay time of the output index signal is determined by the ratio of the reference time and the resistance and is not influenced by the value of the capacitor. Even if the value of the capacitor changes due to temperature change or the like, the timing of the effective leading edge of the output index signal does not change. Moreover, since the resistance does not change with time, the change in the timing of the index signal does not exceed the allowable range, and compatibility is ensured.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a timing adjusting device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of the timing adjusting device according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the timing adjusting device according to the first embodiment of the present invention.

FIG. 4 is a block configuration diagram of a timing adjustment device according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the timing adjusting device according to the second embodiment of the present invention.

FIG. 6 is a circuit diagram of reference time generation means.

FIG. 7 is a circuit diagram of reference frequency signal generating means.

FIG. 8 is a circuit diagram of a first current source, a second current source, and signal generating means.

FIG. 9 is a circuit diagram of a conventional timing adjustment device.

FIG. 10 is a flowchart showing the operation of a conventional timing adjustment device.

[Explanation of symbols]

1 ... Timing adjusting device, 2, 18 ... First current source,
3, 10 ... Reference time generating means, 4, 19 ... Second current source, 5, 17 ... Charge / discharge control means, 6, 20 ... Signal generating means, 7 ... Drive circuit, 8 ... Motor, 9 ... Speed control circuit 1
DESCRIPTION OF SYMBOLS 1 ... FG amplification shaping circuit, 12 ... Oscillation circuit, 13 ... Dividing ratio switching circuit, 14 ... Reference frequency signal generating means, 15 ... Digital mono-multi circuit, 16 ... Low pass filter.

Claims (2)

(57) [Claims] 1. A reference time generating means for generating a reference time, a first current source for generating a first current, and a second current for generating a second current having a magnitude corresponding to a resistance value of a variable resistor. The second current source and the capacitor are discharged (charged) by the current generated by the first current source at the reference time generated by the reference time generation means, and then the capacitor is discharged by the current generated by the second current source. 2. A timing adjusting device comprising: a charging / discharging control means for controlling so as to charge (discharge) the battery again; and a signal generating means for generating an output index signal at a timing corresponding to the terminal potential of the capacitor. 2. The frequency F corresponding to the rotation speed of the motor.
A speed control circuit provided with a counter for counting the reference frequency signal generated by the reference frequency signal generating means based on the G signal, and a speed control circuit for outputting a speed control signal according to the count value of the counter, and according to the output of this speed control circuit 2. The timing adjusting device according to claim 1, further comprising a drive circuit for rotationally driving the motor, wherein the reference time generating means generates the reference time based on the count value of the counter.