JP2545108B2 - Line monitor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial field of use" The present invention relates to a line for transmitting information in a modulated carrier wave, which is useful for control of monitoring transmission characteristics and improving the transmission characteristics. The present invention relates to a monitor circuit.

"Prior Art" In a line that transmits information by a modulated carrier wave, it is necessary to monitor the line and monitor the carrier level and phase fluctuation.

As a carrier wave level detection circuit, generally used is a structure in which after detecting and amplifying the output of each stage of amplifiers connected in multiple stages, the synthesized signal is used as a level signal and this level signal is monitored. Has been done.

On the other hand, as a circuit for detecting the phase fluctuation, there are few circuit examples that are generally used, but the phase fluctuation can be detected by a jitter detector developed for level detection.

FIG. 7 shows an example of a conventional jitter detection circuit for detecting a phase fluctuation.

This circuit is a circuit using a differential detection circuit, and uses a shift register as a delay circuit and a D flip-flop as a detection circuit.

In the figure, 1 is an IF (intermediate frequency) signal input terminal, 2
Is a shift register for delay, 3 is a clock input terminal for shift register, 4 and 5 are D flip-flop circuits for detection,
6 is a NAND circuit. In this jitter detection circuit, the input IF
The output of the A-stage and B-stage shift registers varies due to the phase variation of the signal (where A <B). If the output is adjusted to the Mth stage when there is no phase fluctuation, the NAND circuit 6 is used when the phase fluctuates below the Ath stage or above the Bth stage
The output of becomes "1", and the jitter can be detected.

[Problems to be Solved by the Invention] However, in the above-described jitter detection circuit, a frequency of several times the carrier frequency of the IF is required as the clock of the delay shift register 2. Further, the frequency of this clock becomes the accuracy of jitter detection.

Therefore, a high-speed element is required, and there is a drawback that it is not suitable for low power consumption when the accuracy is set high. Furthermore, when there is no phase fluctuation, it is necessary to adjust the output to the Mth stage, which is not suitable for no adjustment.

The present invention solves the above-mentioned drawbacks of the conventional phase fluctuation detector, and provides a line monitor circuit that achieves high sensitivity of carrier phase fluctuation detection, low power consumption, and no adjustment. To aim.

"Means for Solving the Problems" In order to solve the above problems, the present invention relates to a synchronous detector that controls the phase of a reproduced carrier wave by the output of a phase locked loop filter so as to follow the carrier wave phase component of a received signal. In the carrier recovery circuit, the input signal of the phase-locked loop filter is input to a low-pass filter having a short time constant, and the carrier phase fluctuation signal from which the modulation component and the component of the carrier frequency or higher are removed by the low-pass filter, It is characterized in that the time rate or frequency exceeding a preset threshold value is measured and the time rate or frequency is sent to the line control device.

[Operation] According to the above means, the function of detecting the timing when the phase difference output of the phase locked loop inside the synchronous detector exceeds the threshold value, and the function of measuring the time rate of the high level and the low level of the detected signal , A function of measuring the number of pulses of the detected signal.

It differs from the conventional jitter detector in that it has the above-mentioned three functions.

As a result, the line monitor circuit according to the present invention can predict the fading frequency almost accurately and can eliminate adjustment. In addition, since it can be configured with an element that is slower than the conventional example and consumes less power, it is possible to achieve lower power consumption.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

In the figure, 7 and 7a are multipliers, 8 and 8a are low-pass filters, 9 is a multiplier, 11 is a π / 2 phase shifter, 12 is a voltage controlled oscillator (VCO), 13 is a low-pass filter (hereinafter referred to as a loop filter). ), And the above circuit constitutes a Costas loop type synchronous detector. Further, 10 is a discriminator, 14 is a low-pass filter, 15 is a fading detector, and 16 is a time rate measuring device.

The input IF signal is multiplied by the reproduced carrier wave by the multiplier 7, and is also multiplied by the wave obtained by shifting the phase of the reproduced carrier wave by π / 2 by the multiplier 7a. The output of the multiplier 7,7a is
The harmonics are removed through the low-pass filters 8 and 8a, respectively, and are input to the multiplier 9. At the output of the multiplier 9, the modulation component is removed and only the phase difference between the input IF signal and the reproduced carrier wave appears. The output is smoothed through the loop filter 13, applied to the control voltage terminal of the VCO 12, and controlled so that the phase difference is minimized.

Here, when a phase variation occurs in the input IF signal due to the change in the transmission path, a variation waveform proportional to the phase difference between the input IF signal and the reproduced carrier wave appears in the output of the multiplier 9. The output fluctuation waveform is passed through a low-pass filter 14 to a fading detector.
Enter in 15. The fading detector 15 changes the output state of the fading detector 15 from the “0” state to the “1” state when the fluctuation waveform passing through the low-pass filter 14 exceeds the threshold value. The time rate measuring device 16 in the next stage measures the ratio of the time when the output of the fading detector 15 is in the "1" state.

If a phase fluctuation occurs in the input IF signal by the above operation,
The value of the time rate output of the time rate measuring instrument 16 increases and the input IF
The phase fluctuation of the signal can be detected.

FIG. 2 shows a specific example of the fading detector 15, and FIG. 3 shows its timing chart.

In FIG. 2, reference numerals 17 and 18 are comparators, and when a voltage higher than the reference input voltages REF1 and REF2 is input, the output signal becomes high level. 19 is an inverter, 20
Is an OR circuit.

Reference input voltage REF of comparator 17 described above
1, and the reference input voltage REF2 of comparator 18
As shown in FIG. 3 (a), the voltage is set to be substantially symmetrical with respect to the center voltage of the input voltage. Then the comparator
17 detects a voltage higher than the reference input voltage REF1 (see (b) in the figure), and the comparator 18 uses the inverter
Along with 19, a voltage lower than the reference input voltage REF2 can be detected (see (c) and (d) in the same figure).

Therefore, when the input voltage fluctuates outside the range of the two reference input voltages REF1 and REF2, the output of the OR circuit 20 becomes high level and the phase fluctuation state can be detected ((e) in the figure).
reference).

In the fading detector 15 described above, the sensitivity of phase fluctuation detection can be changed by changing the time constant of the low-pass filter 14 at the input stage. If the time constant of the low-pass filter 14 is made small, its output changes greatly with respect to the phase fluctuation, so that the sensitivity becomes high.

 FIG. 4 shows a concrete example of the time rate measuring device 16.

In the figure, 21 is a clock pulse generator capable of generating a pulse having a frequency sufficiently higher than the week number of the input IF signal, 22
Is an AND circuit, 23 is a counter circuit, and 24 is a timer circuit.

The output of the fading detector 15 and the output of the clock pulse generator 21 are input to the AND circuit 22. The AND circuit 22 transmits the pulse from the clock pulse generator 21 to the counter circuit 23 only when detecting the phase fluctuation of the carrier wave. On the other hand, the timer circuit 24 constantly counts the pulses of the clock pulse generator 21, counts N _T pulses, and then sends the pulses to the control circuit 25.
After the control circuit 25 receives the pulse, the counter circuit 23
The count value N _{F of} is measured and the time rate N _F / N _T is calculated.

FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention.

In the figure, 26 is a counting circuit. In this embodiment, a counting circuit 26 is connected instead of the time rate measuring device 16 of the first embodiment described above.

In this configuration, the counting circuit 26 measures the output pulse of the fading detector 15 caused by the phase fluctuation of the carrier wave. When the ratio of the phase fluctuation of the carrier increases, the number of output pulses of the fading detector 15 also increases, and the ratio of the phase fluctuation of the carrier can be predicted from the output value of the counting circuit 26.

FIG. 6 shows the count value of the counter circuit 26 when the phase fluctuation of the carrier wave is artificially generated by the fading simulator and the signal is detected. Since the count value monotonically increases with respect to the fading frequency, the fading frequency can be predicted from the count value.

As described above, the line monitoring circuit is characterized in that the fading frequency can be predicted almost accurately and that no adjustment can be made. In addition, each of the above-described embodiments can be configured with elements that are slower and consume less power than the conventional example, so that lower power consumption can be achieved.

"Effects of the Invention" As described above, the line monitor circuit according to the present invention is effective as a means for measuring a fading frequency, and can be configured with only a small number of additional circuits when used in combination with a synchronous detector. Then, the fading frequency can be predicted almost accurately, and the power consumption can be reduced and the adjustment can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention,
FIG. 2 is a circuit diagram showing a specific example of the fading detector in the same embodiment, FIG. 3 is a timing chart showing the operation of the fading detector, and FIG. 4 is a specific example of the time rate measuring device in the same embodiment. Block diagram, FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention, FIG. 6 is a graph showing the count value of the output pulse of the fading detector with respect to the fading frequency, and FIG. 7 is a conventional phase fluctuation. It is a circuit diagram which shows an example of the jitter detection circuit for detecting. 1 ... IF signal input terminal, 2 ... delay shift register, 3 ... shift register clock input terminal, 4 ... detector D flip-flop circuit, 5 ... detector D flip-flop circuit, 6 ... … NAND circuit, 7,7a …… Multiplier, 8,8a …… Low-pass filter, 9 …… Multiplier, 10 …… Identifier, 11 …… π / 2 phase shifter, 12 …… Voltage controlled oscillator, 13 …… Loop filter, 14 …… Low-pass filter, 15 …… Fading detector, 16 …… Time rate measuring instrument, 17 …… Comparator, 18 …… Comparator, 19 …… Inverter, 20 …… OR circuit, 21 …… Clock pulse oscillator, 22 …… AND circuit, 23 …… Counter circuit, 24 …… Timer circuit, 25 …… Control circuit, 26 …… Counting circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-52136 (JP, A) JP-A-62-161230 (JP, A)

Claims (1)

(57) [Claims] 1. A carrier recovery circuit of a synchronous detector for controlling a phase of a reproduced carrier by an output of a phase locked loop filter so as to follow a carrier phase component of a received signal, wherein an input signal of the phase locked loop filter has a time constant. Of the carrier phase fluctuation signal, which is input to a short-pass low-pass filter of which the modulation component and the component higher than the carrier frequency are removed by the low-pass filter, exceeds the preset threshold value, and the time rate or frequency is measured. A line monitor circuit that sends the rate or frequency to the line controller.