JP2545053Y2 - Address setting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an address setting device suitable for an electronic musical instrument capable of loop reproduction.

[Prior art and its problems] In a conventional sampling instrument, the setting of a loop section when a desired range is repeatedly read out from an external sound sampled and stored waveform and reproduced is performed based on a trial and error of a player. Or automatically through the detection of zero cross points by circuit operation. In the former case, fine settings can be made, but it requires labor and requires a complicated operation that takes time. On the other hand, in the latter case, since it is based on only the zero cross point detected first, it is not always smooth, and sometimes a noticeable noise called a click sound is generated. .

[Purpose of the Invention] The present invention has been made in view of the above-mentioned circumstances, and aims at an optimum loop start address and a waveform start-up which do not cause waveform discontinuity without bothering the user. An object of the present invention is to provide an address setting method capable of automatically setting a loop end address.

[Gist of the invention] In the invention, in order to achieve the above-described object, an address corresponding to one end of a section to be loop-reproduced and an address corresponding to the other end are selected from a waveform value sequence stored in a waveform storage unit. A first designating means for sequentially reading the waveform values in the waveform storage means from an address corresponding to one end designated by the designating means and detecting a first waveform value whose polarity is inverted; Means, first setting means for setting a read address corresponding to the first waveform value detected by the first detecting means to the first address, and setting by the first setting means. Of the waveform values from the first address to the address corresponding to the other end designated by the designation means, the polarity inversion direction of the first waveform value detected by the first detection means. And the same as
A second detecting means for detecting a second waveform value having a minimum difference from the first waveform value; and a read address corresponding to the second waveform value detected by the second detecting means. And second setting means for setting to the second address, and one of the first and second addresses set by the first and second setting means becomes a start point of loop reproduction. The key point is that the loop start address and the other end are set as the loop end address which is the end of the loop reproduction.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

<Structure of Embodiment> FIG. 1 shows an entire circuit of an electronic musical instrument to which the present invention is applied. In the figure, reference numeral 1 denotes a CPU which controls the entire circuit according to a program in a built-in ROM. This CPU
The output of the switch unit 2 is input to 1.

The switch section 2 includes a keyboard section 2a and a control key section 2b including various control keys, as well as all switches necessary for this type of electronic musical instrument, such as a tone color selection switch. Further, the control key section 2b includes a mode selection switch and a loop section designation switch. The mode selection switch is used to set the electronic musical instrument to the sampling mode or the play mode, and the loop section designation switch is sampled and stored. Used to specify the desired loop section for the waveform.

In the sampling mode, the CPU 1 sends a write signal (R / W) to the waveform RAM 4 while the A / D converter 6
To the drive command signal CS. Therefore, A / D converter 6
Converts the external sound of the analog value that is picked up and input by the microphone 7 into a digital value and sends it to the waveform RAM 4, so that the external sound obtained by sampling is stored in the waveform RAM 4 as waveform data. You.

Which section of the waveform data stored in the waveform RAM 4 is repeatedly read and used is generally determined by the performer, and then internally determined. That is, when the player designates the start address α and end address β of a desired section using the loop section designation switch, the CPU 1 sets the address of the waveform RAM 4 from the end address β toward the start address α by one. While decrementing one by one, the first zero crossing point where the sign in the waveform value changes is searched for, and the address at which the sign changes is determined as a normal end address. A zero-cross point having the same sign as the slope of the waveform is searched for, and the level difference between the waveform value at the address corresponding to the zero-cross point and the waveform value at the determined end address is a predetermined value given in advance. And the level difference is set as a new predetermined value on condition that the level difference is smaller than a predetermined value. At the same time, the address at that time is determined as the start address, the same processing is continued until the address of the waveform RAM 4 becomes α, the start address is updated every time a predetermined value is reset, and the last An address corresponding to the reset of the predetermined value is determined as a normal start address, and the thus determined start address and end address are stored in a predetermined register in the address control unit 3.

On the other hand, in the performance mode, the CPU 1 detects a key depression operation on the keyboard 2a and sends a key code corresponding to the pressed key to the frequency data generation unit 5, so that the frequency data generation unit 5
Creates pitch data corresponding to the key code.
The address control unit 3 controls the speed of reading the waveform data from the waveform RAM 4 based on the pitch data given from the frequency data generation unit 5, so that the tone data corresponding to the key code read from the waveform RAM 4 is D. After the digital / analog conversion in the / A converter 8,
The sound is emitted as a musical tone by the speaker 10 via the amplifier 9.

The address control unit 3 is shown as including all registers used in the operation for determining the loop section.

<Operation of Embodiment> Next, the operation of this embodiment will be described.

FIG. 2 is a flowchart showing a flow of an operation for automatically determining a loop start address and a loop end address to be actually used based on a loop start address α and a loop end address β specified by a player. FIG. 2 (A) shows the main flow, and FIG.
FIG. 2 (B) and FIG. 2 (C) show the sub-flow.

The main flowchart shown in FIG. 2A starts in response to the end of the designation of the start address α and the end address β of the desired loop section by the player, and
In step S1, the end address β previously specified by the player is set in the register adr as the first end address, and then the predetermined value is set in the register mSUBY. Initialization (step
S2), the waveform RAM indicated by the register adr at this time
The waveform value at address 4 is stored in register y (step S
3) Looking at the contents of the MSB, which is the sign bit of register y,
That is, it is determined whether the waveform value of the register y is plus (+) or minus (-), and it is stored in the register PF (step S4). Then, in step S5, a zero-cross detection process is performed.

In the flow chart of FIG. 2B showing this zero-cross detection processing, the CPU 1 decrements the contents of the register adr at step T1, and then starts the processing in which the contents of the register adr are specified in advance by the player. It is determined whether it is equal to the address α (step T2).

If the determination in step T2 is YES, this means that the address in the waveform RAM 4 has reached the start address α, and all processing will be terminated.
If NO, the waveform value at the address of the waveform RAM 4 indicated by the register adr at this time is stored in the register y (step T
3), the sign bit in the MSB of register y and register PF
It is determined whether or not the flag, that is, the sign bit is the same (step T4).

As long as the determination in step T4 is equal, steps T1, T2,
By circulating through T3 and T4, the contents of the register y are sequentially updated while decreasing the address by -1.
Then, the sign bit of the MSB in the register y is put in the register PF, and the process returns. In other words, in the processing of steps T1 to T5 described above, the first zero cross point was found in the process of decreasing the address from the loop end address β specified by the player, and the waveform value of the address indicated by the register adr was stored in the register y. Will be.

Now, returning to FIG. 2A, in step S6, the CPU 1 puts the contents of the register adr into the register OXP1, and
At the same time as determining the normal end address, the contents of the register y, that is, the waveform value is transferred to the register Y1, and the zero cross detection process is performed twice in steps S7 and S8.

The contents of the zero-crossing detection processing in steps S7 and S8 are exactly the same as the contents in step S5 (see FIG. 2 (B)). By performing the processing twice, the same sign bit as the zero-crossing point detected in step S5 is obtained. Find the zero crossing point you have. That is, assuming that the waveform value at the zero cross point detected in step S5 has changed from plus (+) to minus (-), the waveform value at the zero cross point detected in step S7 has changed from minus (-) to plus. Since it changes to (+), the sign bit of each zero cross point detected in step S5 and step S7 is different. Therefore, the zero cross point is detected again in step S8. Since the waveform value at the zero cross point detected in step S8 changes from plus (+) to minus (-), step S5 and step S5 are performed.
The sign bit of each zero cross point detected in S8 is the same. Subsequently, in step S9, the waveform value of the register y stored in step S8 is entered into the register Y2, and then the subtraction process is performed on the contents of the registers Y1 and Y2 (step S10).

The content of the subtraction process in step S10 is shown in FIG. 2 (C), and the CPU 1 sets the register Y1 in step W1.
And compare the size of the contents to Y2. If,
In the determination in step W1, if Y1> Y2, the result is YES. In step W2, the content of the register Y2 is subtracted from the content of the register Y1 and the result is stored in the register SUBY. If Y1 <Y2, the result is NO. Subtract the contents of register Y1 from the contents of Y2 and put in register SUBY,
It returns to step S11 in FIG.

In step S11, the contents of the register SUBY are stored in the register mSUBY.
It is determined whether the value is smaller than the predetermined value in the above, and the processing of steps S7 to S11 is repeated until a zero cross point of a waveform value smaller than the predetermined value is found. Therefore, the content of the register SUBY is set in the register mSUBY, and the initial predetermined value is reset to a smaller value.
The contents of r are stored in the register OXP2, determined as a temporary start address at this point, and the process returns to step S7.

In steps S7 and S8, two zero-cross detections are continuously performed, and the waveform value at that time is obtained (step S7).
9), a subtraction process is performed (step S10), and on the condition that the subtraction result (SUBY) is smaller than the previously updated predetermined value (mSUBY) (step S11: YES), the register SUB
The content of Y is stored in the register mSUBY to update the predetermined value to a smaller value, and the content of the register adr is stored in the register OXP2 to be a temporary start address at that time (step S12).

Thereafter, the CPU 1 repeats the update of the predetermined value and the provisional start address by circulating through steps S7 to S12, but this processing ends when the content of the register adr reaches α (step T2). .

By such processing, the address value stored in the register OXP2 is finally determined as a normal start address.

[Effects of the Invention] As described in detail above, the present invention provides that when a user roughly designates one end and the other end of a section to be loop-reproduced, a waveform value sequence existing between the one end and the other end is specified. When a loop is played, a waveform value at the beginning and a waveform value at the end such that the waveforms are smoothly connected are detected, and a loop start address and a loop end address corresponding to the waveform values at the beginning and end are automatically determined. Since the setting is performed, it is possible to determine the optimum loop start address and loop end address that does not cause the waveform discontinuity without bothering the user.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of an electronic musical instrument to which the present invention is applied, and FIG. 2 is a flowchart showing an operation flow for automatically determining a loop section. 1 ... CPU, 2 ... switch section, 3 ... address control section, 4 ... waveform RAM, 5 ... frequency data creation section, 6 ...
… A / D converter, 7… Microphone, 10 …… Speaker.

Continuation of the front page (56) References JP-A-58-143398 (JP, A) JP-A-60-1022693 (JP, A) JP-A-56-35192 (JP, A) JP-A-61-45298 (JP, A) JP-A-57-58195 (JP, A) U.S. Pat. No. 4,442,745 (US, A) Keyboard Magazine September 1983, pp. 156-157.

Claims (1)

(57) [Scope of request for utility model registration] 1. A designating means for designating an address corresponding to one end and an address corresponding to the other end of a section to be loop-reproduced from a waveform value sequence stored in a waveform storage means, and Sequentially read the waveform values in the waveform storage means from the address corresponding to the other end,
First detecting means for detecting a first waveform value whose polarity is inverted; and a first address for setting a read address corresponding to the first waveform value detected by the first detecting means to a first address. 1 setting means, and the first detection of waveform values from a first address set by the first setting means to an address corresponding to the other end specified by the specifying means. Second detection means for detecting a second waveform value which is the same as the polarity inversion direction in the first waveform value detected by the means and has a minimum difference from the first waveform value; A second setting unit that sets a read address corresponding to the second waveform value detected by the second detection unit to a second address, wherein the first and second setting units include: One of the first and second addresses set as the start address of the loop playback An address setting device for setting a loop start address and a loop end address at the other end of loop reproduction.