JP2540327B2 - Control power supply for reactor load - Google Patents

Description

The present invention relates to a reactor load control power supply for supplying electric power to a reactor load such as a magnet coil.

[Conventional technology]

FIG. 5 is a block diagram showing a configuration of a conventional reactor load control power supply. In the figure, 1 is a reference signal generating circuit, 2 is a subtractor, and the output of the reference signal generating circuit 1 is a thyristor converter which will be described later. To subtract the output of the voltage sensor.

Reference numeral 3 denotes an arithmetic circuit for amplifying the output of the subtractor 2, and 4 denotes a gate pulse generating circuit for generating a gate signal based on the output of the arithmetic circuit 3.

Reference numeral 5 denotes a thyristor converter, which is controlled by an AC power supply e _a and a gate signal from the gate pulse generation circuit 4.
It is composed of TH _{1 to} TH ₄ and voltage sensor VS.

6 indicates a reactor load, for example, reactor L, resistance R
It is a magnet coil composed of a series element of.

FIG. 6 is a waveform diagram for explaining the operation of the control power supply for the reactor load shown in FIG. 5, and FIG. 6 (a) is a reference signal generation circuit 1 via a contact or non-contact element (not shown). 6 (b) shows an input reference signal C output from the reference signal generating circuit 1 as shown in FIG.
FIG. 6C shows the output voltage V _D of the thyristor converter 5, and FIG. 6D shows the load current.

As a reactor load control power supply having a configuration similar to that shown in FIG. 5, there is one disclosed in Japanese Patent Laid-Open No. 59-122365.

 Next, the operation will be described.

The input signal A shown in FIG.
Is input, the reference signal generating circuit 1 outputs the output reference signal C shown in FIG. 6 (b). The subtractor 2 subtracts the output of the voltage sensor VS output by the gate pulse generation circuit 4 from the output reference signal C of the reference signal generation circuit 1, and the arithmetic circuit 3
The output of the subtractor 2 is amplified by.

The gate pulse generation circuit 4 generates a gate pulse for controlling the thyristors TH _{1 to} TH ₄ of the thyristor converter 5 based on the output of the arithmetic circuit 3.

As a result, the output voltage (average value) V _D shown in FIG. 6 (c) is obtained at the output terminals P and N of the thyristor converter 5.

This output voltage V _D is applied to the reactor load 6 composed of a series element from the reactor L and the resistor R, and the reactor load 6
The load current shown in FIG.

When the equivalent reactance of the reactor load 6 as viewed from the output terminals P and N of the gate pulse generation circuit 4 is L _E and the equivalent resistance is R _E , the load current i _d can be expressed by the equations (1) and (2). .

However, τ = L _E / R _E, put the t ₁ = 0 at time t ₁ ~t _4.

However, τ = L _E / R _E, put a t ₄ = 0 at time t> t _4.

[Problems to be solved by the invention]

Since the conventional control power source for the reactor load is configured as described above, the output reference signal C is constant and the output voltage V _D is also constant. Therefore, at the rising and falling portions of the load current, the reactor load 6 Due to the restriction of the time constant τ, the high speed response is lost.

In order to obtain a control power supply for a reactor load that responds at high speed, it is necessary to connect a resistor in series with the reactor load 6 and take measures such as increasing the voltage of the AC power supply e _a , which makes the configuration complicated and expensive. There was a problem that

The present invention has been made to solve the above problems, and an object thereof is to obtain a reactor load control power supply that responds at high speed.

[Means for solving problems]

The reactor load control power supply according to the present invention is configured to add a signal larger than the steady value of the output reference signal within a predetermined time width at each of the "on" and "off" times of the output reference signal.

[Action]

In the reactor load control power supply according to the present invention, by adding a signal larger than the steady value of the output reference signal within a predetermined time width at each of the "on" and "off" points of the output reference signal, The load current rises and falls faster.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a reference signal generating circuit, which includes a waveform shaping circuit 11, first and second time limiting circuits 12A and 12B, and first and first
The second and third switch circuits 13A, 13B and 13C, the first, second and third setting command circuits 14A, 14B and 14C, the inverting addition circuit 15 as the arithmetic circuit, and the diodes D ₁ and D ₂ It is composed of.

Note that the other circuits are the same as those of the conventional circuit, and therefore the illustration thereof is omitted.

FIG. 2 is a waveform diagram for explaining the operation of the control power supply for the reactor load of the present invention. FIG. 2 (a) shows the input signal A of the reference signal generating circuit 1 and FIG. 2 (b) shows the waveform. The output signal B of the shaping circuit 11 is shown in Fig. 2 (c) and (d).
The output signals of the first and second timing circuits 12A and 12B are shown in FIG. 2 (e).
Is an output reference signal C output from the reference signal generation circuit 1.
2 (f) shows the output voltage V of the thyristor converter 5.
_2D shows the load current.

 Next, the operation will be described.

The waveform shaping circuit 11 shapes the inverted waveform of the input signal A shown in FIG. 2 (a), and outputs the period output signal B of the time period T _B corresponding to the input signal “ON” period shown in FIG. 2 (b). .

The first timing circuit 12A detects the rising edge of the input signal A, and outputs an output signal for the period T _A after the input signal "ON" shown in FIG. 2 (c).

The second time limit circuit 12B detects the falling edge of the input signal A, and outputs the output signal during the time period T _C after the input signal is turned off as shown in FIG. 2 (d).

The first switch circuit 13A is driven by the first time limit circuit 12A and closes the switch only during a time period (timer period) T _A after the input signal “turns on”.

The second switch circuit 13B is driven by the output of the waveform shaping circuit 11 and closes the switch only during the period T _B corresponding to the "ON" period of the input signal.

The third switch circuit 13C is driven by the second time limit circuit 12B and closes the switch only during the time period (timer period) T _C after the input signal is turned off.

The first setting command circuit 14A includes a first switch circuit 13A, a diode D ₁ , a second switch circuit 13B and an inverting addition circuit 1
5 via a second diagram (e) the time t ₁ the command voltage E ₁ shown in ~t
Output for period ₂ (time period T _A ).

The second setting command circuit 14B outputs the command voltage E ₂ shown in FIG. 2 (e) through the diode D ₂ , the second switch circuit 13B and the inverting addition circuit 15 for the period of time t ₂ to t _3. .

The third setting command circuit 14C receives the command voltage shown in FIG. 2 (e) via the third switch circuit 13C and the inverting addition circuit 15.
E ₃ the period of time t ₃ ~t ₄ (period timed T _C) outputs.

Diodes D ₁ and D _{2 form} a diode OR circuit,
The above output is obtained at t _{1 to} t ₃ . Since the first and second setting command circuits 14A and 14B have the same polarity and the third setting command circuit 14C has the opposite polarity to the first and second setting command circuits 14A and 14B, the inverting addition circuit As the output reference signal C of 15, the command voltage waveform shown in FIG. 2 (e) is obtained.

The command voltages E ₁ and E ₂ have a relationship of E ₁ > E ₂ .

When the reference signal generating circuit 1 is configured as described above, the output voltage V _D shown in FIG. 2 (e) can be obtained as the output signal of the reference signal generating circuit 1, and the output of the thyristor converter 5 is the second voltage. It is possible to obtain a waveform (average value) having the output voltage pattern shown in FIG.

As a result, the output voltage V _DF in the timer period T _A after the input signal “turns on” becomes larger than the output voltage V _D in the steady period (between time points t _{2 and} t ₃ ).

Also, the output voltage V during the timer period T _C after the input signal is turned off
_DR also increases with the opposite polarity to the output voltage V _D.

Therefore, as shown in FIG. 2 (g), the load current rises and falls earlier than the conventional one,
Fast response.

FIG. 3 is a circuit diagram showing another embodiment of the present invention,
The same parts as those in FIG. 1 are designated by the same reference numerals, and R _{1 to} R ₁₅
Is a resistor, Q is a transistor, AMP ₁ is a buffer amplifier, AM
P _{2 to} AMP ₄ are operational amplifiers, CP _{1 to} CP ₃ are comparators, FET ₁
~ FET ₃ is a field effect transistor, VR ₁ ~ VR ₃ is a volume, OS ₁ is a monostable multi-circuit that detects falling edges, OS ₂ is a monostable multi-circuit that detects rising edges, and D ₃ and D ₄ are diodes. Indicates.

4 (a) to (l) are waveform charts for explaining the operation.

 Next, the operation will be described.

From the transistor contactless signal circuit shown in the input terminal of the waveform shaping circuit 11 composed of the resistors R ₁ and R ₂ , the transistor Q, and the buffer amplifier AMP ₁ , the input signal A shown in FIG.
There is input to the buffer amplifier AMP _1, (a negative signal in the input signal "ON" period T _B) of the fourth obtaining an output signal B shown in Figure (b).

The monostable multi-circuit OS ₁ of the first time limit circuit 12A detects the falling edge of the output signal of the buffer amplifier AMP ₁ (corresponding to the "input" time point of the input signal), and only the timer period T _A is shown in FIG. 4 (c). The output signal shown in is output.

The comparator CP ₁ compares the output signals of the monostable multi-circuit OS ₁ with a predetermined voltage (depending on the voltage division of the resistors R ₃ and R ₄ ) and outputs the output signal shown in FIG. 4 (d). This output signal is applied to the gate of the field effect transistor FET ₁ for the timer period.
Only T _A turns off the field effect transistor FET ₁ .

Therefore, the output of the operational amplifier AMP ₂ command voltage E ₁ equivalent voltage is set by Boryuumu VR _1, the timer period T
Only _{A, the} output signal shown in FIG. 4 (e) is output.

The comparator CP ₂ compares the output signal of the buffer amplifier AMP ₁ with a predetermined voltage (depending on the voltage division of the resistors R ₇ and R ₈ ) and outputs the output signal shown in FIG. 4 (f). This output signal is applied to the gate of the field effect transistor FET ₂ , and the field effect transistor FE is applied only during the period T _B (corresponding to the “input” period).
Turn on T ₂ .

Voltage command voltage E ₂ corresponds to the output of the operational amplifier AMP ₃ is set by Boryuumu VR _2, the output signal shown in FIG. 4 (g) is outputted.

The monostable multi-circuit OS ₂ detects the rising edge of the output signal of the buffer amplifier AMP ₁ (corresponding to the “off” time point of the input signal) and outputs the output signal shown in FIG. 4 (h) only during the timer period T _C.

The comparator CP ₃ compares the output signal of the monostable multi-circuit OS ₂ with a predetermined voltage (by dividing the voltage of the resistors R ₁₂ and R ₁₃ ) and outputs the output signal shown in FIG. 4 (j). This output signal is applied to the gate of the field effect transistor FET _3, to turn on the field effect transistor FET ₃ only period T _C.

The volume VR ₃ outputs a voltage equivalent to the command voltage E ₃ shown in Fig. 4 (j).

As a result, the input signal shown in FIG. 4 (k) is added to the input of the operational amplifier AMP ₄ , and the output reference signal C shown in FIG. 4 (l) is obtained at the output.

Therefore, the same effect as the embodiment of FIG. 1 can be obtained.

〔The invention's effect〕

As described above, according to the present invention, a signal larger than the steady value of the output reference signal is added within a predetermined time width at the “on” and “off” points of the output reference signal. On the other hand, there is an effect that the rising speed and the falling speed of the load current can be increased, and a high speed on / off characteristic can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a reference signal generating circuit of a control power source for a reactor load according to an embodiment of the present invention, and FIGS. 2 (a) to (g) are diagrams for explaining the operation of the control power source for a reactor load of the present invention. 3 is a block diagram showing a reference signal generating circuit of a control power supply for a reactor load according to another embodiment of the present invention, and FIGS. 4 (a) to 4 (l) are control of the reactor load according to the present invention. 5 is a waveform diagram for explaining the operation of the power source, FIG. 5 is a block diagram showing a reference signal generating circuit of a conventional reactor load control power source, FIG.
(D) is a waveform diagram for explaining the operation of a conventional control power source for a reactor load. In the figure, 1 is a reference signal generation circuit, 3 is an arithmetic circuit, 4
Is a gate pulse generator circuit, 5 is a thyristor converter, 6 is a reactor load, 11 is a waveform shaping circuit, 12A and 12B are first and second time limit circuits, and 13A, 13B and 13C are first, second and first circuits. 3 switch circuits, 14A, 14B and 14C are first, second and third setting command circuits, 15 is an inverting addition circuit, VS is a voltage sensor, OS ₁ and OS ₂ are monostable multi-circuits, D ₁ and D ₂ is a diode, CP ₁ and CP ₃ are comparators, and FET ₁ , FET ₂ and FET ₃ are field effect transistors. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. An arithmetic circuit for amplifying a difference between an output of a reference signal generating circuit and an output of a voltage sensor, a gate pulse generating circuit for generating a gate signal based on an output of the arithmetic circuit, and the gate pulse generating circuit. While outputting a voltage to a reactor load based on the output of, in the reactor load control power supply including a thyristor converter having the voltage sensor, the reference signal generation circuit, a waveform shaping circuit for shaping the input signal and A first time limit circuit that detects the rising edge of the input signal based on the output of the waveform shaping circuit; a second time limit circuit that detects the falling edge of the input signal based on the output of the waveform shaping circuit;
First switch circuit that is closed by the output of the time limit circuit, a second switch circuit that is closed by the output of the waveform shaping circuit, and a third switch circuit that is closed by the output of the second time limit circuit. And the first switch circuit,
A first setting command circuit connected to the second switch circuit via a first diode; and a second setting command circuit connected to the second switch circuit via a second diode; A reactor load control power supply, comprising a third setting command circuit connected to the third switch circuit and an arithmetic circuit for adding outputs of the second and third switch circuits. 2. The first time-limit circuit is composed of a first monostable multi-circuit operating at a falling edge of an output of a waveform shaping circuit and a first comparator, and the second time-limit circuit is constituted by the waveform. A second monostable multi-circuit that operates at the rising edge of the output of the shaping circuit and a second comparator, and the first, second, and third switch circuits are field-effect transistors. The control power supply for the reactor load according to claim 1.