JP2540178B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Outline Industrial field of use Conventional technology Problems to be solved by the invention Means for solving problems Problems Working Examples Working examples of the present invention (Figs. 1 to 3) [Advantages of the Invention] [Outline] Regarding a semiconductor integrated circuit, it is intended to provide a semiconductor integrated circuit in which load capacitance is reduced to improve packaging density, and wiring resistance is reduced to increase response speed. For the purpose of, a plurality of logical operation blocks and one clock buffer are provided, and each of the logical operation blocks includes an input gate unit, an output buffer, a one conductivity type transfer transistor and another conductivity type precharge transistor. The input gate unit logically operates a plurality of input signals to generate a predetermined selection signal, and the transfer transistor receives the selection signal at its gate and One of a source and a drain receives a clock signal output from the clock buffer, and the other of the source and the drain is connected to an input side of the output buffer, and the precharge transistor has a gate which is an inverse of the clock signal. A phase signal is received, a drain is connected to a power supply potential equivalent to H level, a source is connected to an input side of the output buffer, and the output buffer is a signal having the same logic as the selection signal in synchronization with the clock signal. Is output.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a repetitive circuit configured by repeating a large number of simple circuit patterns, such as a gate array or a programmable logic circuit.
The present invention relates to a semiconductor integrated circuit such as an array.

In recent years, so-called digital integrated circuits that handle digital values that are easy to integrate have become the mainstream of semiconductor integrated circuits, and higher processing speeds are required as the amount of data to be handled increases. For example, in semiconductor memory devices, so-called memories, the capacity is in the megabit era, and the time required for data input / output cannot be ignored. In this case, the number of gate elements forming the address decoder for selecting a predetermined memory cell is also increasing, and the ratio of the gate element to the chip area of the semiconductor integrated circuit is increasing, and the processing speed due to the wiring resistance and distributed capacitance on the chip is increased. May decrease. Such a semiconductor integrated circuit having a high integration density is realized by repeating a simple circuit pattern, and various array logics such as a gate array and a programmable logic array have been put to practical use in addition to a memory.

In addition, digital signal processing is generally performed based on a clock signal that indicates a reference timing. In the above address decoder, after the external address data is determined, a predetermined memory cell is selected according to the timing of the clock signal. ing. The timing of such a clock signal is more important as the digital signal processing system becomes more complicated and faster, and even if there is a slight timing deviation, that is, a delay due to wiring resistance, capacitive load, etc., it has a great influence on the processing system. , In some cases, normal processing may not be performed. Therefore, some efforts have been made to reduce the wiring resistance, the capacitive load, and the like that cause a delay in the timing of the clock signal.

In addition, a so-called dynamic logic that holds an output logic level only for a limited time, for example, a period when a clock signal is at an H level, is also used in a logic that configures a semiconductor integrated circuit. Since the digital processing is performed following the speed of, the logic circuit must promptly respond to the clock signal in order to improve the processing speed.

[Conventional technology]

As a conventional semiconductor integrated circuit of this type, for example, there is an address decoder for selecting a memory cell as described above. A clock signal for instructing the timing of selecting a memory cell is input to this address decoder, and the clock signal is guided to the input terminal of each gate element forming the address decoder. That is, one clock signal is input to many gate elements, and in the case of a gate composed of MOS transistors, the input capacitance is large, so the load capacitance of the circuit that drives the clock signal (hereinafter referred to as the clock driver) Increase. Therefore, when high-speed operation is required, a high-speed MOS transistor that can handle a large load current by increasing the gate width is used, and the distance from the clock driver to each gate element should be as even and minimum as possible in layout. It is designed with consideration.

[Problems to be solved by the invention]

However, in such a conventional semiconductor integrated circuit, when high-speed operation is required, a high-speed MOS transistor with a large gate width is used, so that the packaging density is further increased to reduce wiring resistance and capacitive load. There was a problem that it was difficult to do.

That is, increasing the gate width and operating at high speed means increasing the area of the device itself. Further, there are many restrictions on the layout, and in some cases, the chip area cannot be effectively used, and there is a limit to the improvement of the packaging density.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit in which the load capacitance is reduced to improve the packaging density and the wiring resistance is reduced to increase the response speed.

[Means for solving the problem]

The semiconductor integrated circuit according to the present invention achieves the above object,
The logic operation block includes a plurality of logic operation blocks and one clock buffer, each of the logic operation blocks includes an input gate unit, an output buffer, a transfer transistor of one conductivity type, and a precharge transistor of another conductivity type. The unit logically operates a plurality of input signals to generate a predetermined selection signal, and the transfer transistor receives the selection signal at a gate and receives a clock signal output from the clock buffer at one of a source and a drain. The precharge transistor receives the other of the source and the drain to the input side of the output buffer, receives the reverse phase signal of the clock signal at the gate, and connects the drain to the power supply potential corresponding to the H level. , The source is connected to the input side of the output buffer, and the output buffer is In synchronization with the click signal and outputs a signal of the selection signal the same logic. Alternatively, it has a plurality of logical operation blocks and one clock buffer, each of the logical operation blocks includes an input gate unit, an output buffer, a transfer transistor of one conductivity type and a pre-discharge transistor of another conductivity type, The input gate unit logically operates a plurality of input signals to generate a predetermined selection signal, and the transfer transistor receives the selection signal at a gate and outputs a clock output from the clock buffer to one of a source and a drain. A signal is received, and the other one of the source and the drain is connected to the input side of the output buffer, the pre-discharge transistor receives the signal in reverse phase of the clock signal at the gate, and the drain is connected to the power supply potential corresponding to the L level. And connect the source to the input side of the output buffer,
The output buffer outputs a signal having the same logic as the selection signal in synchronization with the clock signal.

(Operation)

In such a configuration, first, focusing on the operation of one logical operation block, since the precharge transistor is turned on during the H level period of the clock signal, the input side of the output buffer is precharged to the power supply potential equivalent to the H level. , H level. Now, assuming that a selection signal is generated in the input gate unit, the transmission transistor is turned on upon receiving this selection signal, and the level (H level) of the clock signal is about to be transmitted to the input side of the output buffer.
Since the input side is already precharged to the H level, the current from the transfer transistor to the input side, that is, the drive current from the clock buffer does not flow. This state is the same for all logical operation blocks.

On the other hand, during the L level period of the clock signal, all the precharge transistors or the predischarge transistors are turned off. Now, assuming that a selection signal is generated by one input gate unit, the transmission transistor is turned on in response to this selection signal, but the current clock signal is L
Since this is a level, the charge on the input side of the output buffer is extracted toward this L level. That is, the discharge current flows from the input side of the output buffer toward the clock buffer. Since this discharge current is the load current of the clock buffer, the input side (load capacity) of the output buffer is eventually driven by the clock buffer. Here, the driving load of the clock buffer is determined by the number of transfer transistors in the ON state, and the number is always 1
Since they are individual, the driving load is a very small value. Therefore, according to the present invention, since the driving load of the clock buffer is extremely small, the size of the clock buffer can be reduced without sacrificing the operating speed. Or
With the same size, a higher speed operation can be achieved.

〔Example〕

Hereinafter, the present invention will be described with reference to the drawings. For convenience of description, first, the basic logic used in this embodiment will be described with reference to FIG. In FIG. 1, (a) in the figure
Is a basic logic for transmitting the L level, and is shown in FIG.
Is a basic logic for transmitting H level. This is because it is desirable to have a configuration suitable for each of the L level and H level transmissions in consideration of the characteristics of the MOS transistor forming the basic logic, which will be described later in detail.

FIG. 1 (a) shows the basic logic, in which the data signal IN is connected to the gate of an N-channel (hereinafter simply referred to as Nch) MOS transistor (hereinafter simply referred to as Tr) 1,
The clock signal CK1 is input to the source of Tr1. The output signal OUT is taken out from the drain of Tr1, and the source of Tr2 of P channel (hereinafter simply referred to as Pch) is connected to the drain of Tr1. A high level power supply voltage Vcc is applied to the drain of Tr2, and a clock signal ▲ is applied to the gate of Tr2.
▼ is entered. The output signal OUT drives the gate capacitance of the Tr at the latter stage, but the Tr at the latter stage is omitted in the figure. Tr2 is a clock signal ▲ ▼
Becomes conductive during the L level, and the gate capacitance of the subsequent Tr is precharged to set the output signal OUT to the H level, that is, the power supply voltage Vcc.

Now, when the data signal IN is at the H level and the clock signal CK1 becomes the L level, the Tr1 becomes conductive, and the charges precharged in the Tr at the subsequent stage are discharged to the driver of the clock signal CK1 through the channel of the Tr1. That is, the Tr gate capacitance in the subsequent stage becomes the load of the clock signal CK1 only when Tr1 is conductive, and the output signal OUT becomes L level only while the clock signal CK1 is L level. On the other hand, when Tr1 is in the insulated state, the clock signal CK1 and the output signal OUT are cut off, and the gate capacitance of the subsequent Tr does not become a load of the clock signal CK1. That is, when Tr1 becomes conductive, in other words, the data signal IN is at H level and the clock signal CK1 is at L level.
Only when the level becomes the level, the Tr in the latter stage receives the clock signal CK1.
Becomes a load of. Therefore, when it is not necessary to transmit the data signal IN at the L level to the subsequent stage, the gate capacitance of the subsequent Tr does not become a load of the clock signal CK1. That is, since the load is added to the clock signal CK1 only when the signal data needs to be transmitted to the H level and transmitted to the subsequent stage, the load on the circuit that drives the clock signal CK1 (hereinafter, simply referred to as the clock driver) can be reduced. it can. As a result, it is not necessary to particularly increase the size of the Tr forming the clock driver, the area occupied by the chip can be reduced, and the degree of freedom in layout can be increased. That is, it is intended to improve the packaging density while performing a high speed operation.

1 (b) is a logic for transmitting L level, whereas FIG. 1 (a) is for transmitting H level, and the basic idea is the same. However, in the figure (a), Tr1 is an Nch transistor (hereinafter referred to as a transfer transistor: TFTr) that transmits the data signal IN based on the clock signal CK1, whereas in the figure (b), T1
Pch Tr11 is provided as the FTr. Further, in FIG. 4A, Tr2 is a Pch transistor (hereinafter,
Although it was a pre-charge transistor: PCTr), the output signal OUT was previously set to L level (GND) in the same figure (b).
An Nch Tr12 is provided as a pre-discharge transistor (hereinafter referred to as PDTr) set to a potential). In this case, when the clock signal CK2 is at the H level, pre-discharge is performed, and when the data signal ▼ is at the L level and the clock signal ▲ is at the H level, the output signal OUT is at the H level. That is, the gate capacitance of the Tr in the latter stage with respect to the clock signal CK1 becomes a load only when Tr11 is conductive, and does not become a load when Tr11 is in the cutoff state. Therefore, the same effect as that of FIG.

 An embodiment using the above basic logic will be described below.

FIG. 2 is a diagram showing an embodiment of a semiconductor integrated circuit according to the present invention, in which the basic logic is applied to an address decoder of a memory cell.

First, the configuration will be described. In FIG. 2 (a), 21 is
This is a NAND type address decoder, and the NAND type address decoder 21 is composed of a large number of decoders (logical operation blocks) 22a to 22n. The decoder 22a includes a 2-input AND gate (input gate section) 23a, an Nch MOS transistor (one conductivity type transfer transistor; hereinafter abbreviated as TFTr) 24a, a Pch MOS transistor (other conductivity type precharge transistor; 25a and an output buffer 26a.
An address signal is input to the input of the AND gate 23a, and the output of the AND gate 23a becomes H level only when each address signal becomes H level. The output of the AND gate 23a is connected to the gate of TFTr24a, and the input terminal of the output buffer 26a is connected to the drain of TFTr24a. The source of PCTr25a is connected to the input terminal of the output buffer 26a, and the power supply voltage Vcc is applied to the drain of PCTr25a.
Note that the other decoders 22b to 22n have the same internal configuration,
Regarding the decoder 22n, the internal elements are represented by the numbers 23n to 26n. Each of the decoders 22a to 22n outputs the decoded data according to ▲ ▼, and the clock signal CL
K1 is output from the clock driver (clock buffer) 27. The clock driver 27 inverts the clock signal CLK1 and inputs it to the sources of the TFTrs 24a to 24n of the decoders 22a to 22n. That is, the clock driver 27 has a large number of TFTr24s.
Connected to a to 24n. Also, the clock signal ▲ ▼
Is input to the gates of the PCTrs 25a to 25n of the decoders 22a to 22n. Note that this signal may be branched from the input side of the clock driver 27 and given, as indicated by the broken line in the figure.

Next, the operation will be described. The NAND type address decoder 22 selects a corresponding memory cell when the external address data is set. Here, for convenience of explanation, the operation of the decoder 22a will be described first.
When all the address signals input to a become H level, the output of the output buffer 26a becomes H level. At this time, the output of the AND gate 23a is at H level, and TFTr
The gate of 24a is also at H level.

Now, assuming that the clock signal CLK1 is at L level,
The PCTr25a becomes conductive and the input capacitance of the output buffer 26 is changed to the power supply voltage V
Precharge up to cc. At this time, the clock signal CLK1
Is at the H level, the TFTr24a is in the cutoff state. Therefore, the input side of the output buffer 26a is H
The output of the decoder 22a is at the L level.
When the clock signal CLK1 becomes H level, the PCTr25a is cut off, and the TFTr24a becomes conductive by applying the precharge voltage (Vcc) on the input side of the output buffer 26a between the drain and the source. Therefore, from the input side of the output buffer 26a, the TFT
Current flows to the output side of the clock driver 27 through the channel of r24a. At this time, a load is applied to the clock driver 27. On the other hand, even if a precharge voltage is applied between the drain and source of the TFTr24a, the TFTr24a does not conduct unless the gate of the TFTr24a is at the H level. Therefore, the precharge voltage on the input side of the output buffer 26a is not discharged and the clock driver 27 is not loaded. That is, as shown in the basic principle, the output of the AND gate 23a is at the H level, in other words, only the output buffer 26a of the decoder 22a which needs to select the memory cell becomes the load of the clock driver 27. Incidentally, a conventional NAND type address decoder has a clock driver for clock signal CLK1 (composed of inverters 28a and 28b) as shown in FIG.
Since 28 is configured to drive all the NAND gates 29a to 29n, the load of the clock driver 28 is always the value represented by the product of the input capacitance of each NAND gate 29a to 29n and the number of NAND gates 29a to 29n. I was joining. Therefore, in order to ensure high-speed response, it is necessary to increase the size of the Tr that constitutes the output stage of the clock driver 28, which causes restrictions on layout and a reduction in packaging density.

The above problem will be specifically described as follows. That is, when the load capacitance is large, the delay time constant determined by the product of the sum of the wiring resistance and the output impedance of the clock driver 28 and the load capacitance is large. Needs to be small. For example, in order to reduce the wiring resistance, the pattern may be thickened or the distance may be shortened, but it is generally desirable to design the pattern to be thin and short from the viewpoint of improving the mounting density. In addition, the clock driver 28 connects each NAND gate 29a-2
Since it is necessary to make the distances up to 9n as equal as possible, there is a limit to reducing the pattern distance. Further, in order to reduce the output impedance of the clock driver 28, it is common to design the gate width to be large so that the MOS transistor forming the output stage of the clock driver 28 can handle a large current. Since the device area of the device becomes large, it becomes a factor that makes it difficult to achieve high density.

On the other hand, in the present embodiment, the clock driver 27 is configured to be loaded only when all the input addresses of a certain decoder 22a become H level, so that all gate capacitances are always loaded as in the conventional case. The load capacity can be significantly reduced as compared to such a case. Therefore, while ensuring high-speed response, the clock driver 27 can be configured with a minimum required chip area, and the degree of freedom in layout of the clock driver 27 can be greatly expanded.

Although the basic logic for transmitting the H level is applied to the NAND type address decoder, the case where the basic logic for transmitting the L level is applied to the NOR type address decoder will be described next.

In FIG. 3 (a), reference numeral 31 is a NOR type address decoder. The same components as those of the NAND type address decoder shown in FIG. 2 (a) are designated by the same reference numerals and the description thereof will be omitted. The NOR type address decoder 31 is composed of a large number of decoders (a plurality of logical operation blocks) 32a to 32n.
32a is a 2-input OR gate (input gate section) 33a, Pch MOS
Transistor (single conductivity type transfer transistor; hereinafter TF
34a, Nch MOS transistor (other conductivity type pre-discharge transistor; hereinafter abbreviated as PDTr) 35a
a and output buffer 26a. The decoder 32a outputs decoded data according to the timing of the clock signal CLK1, and the clock signal CLK1 is input to the clock driver 27. The output of the clock driver 27 is connected to the drain of TFTr34a, and the clock signal CLK1 is connected to the gate of PDTr35a. The other decoders 32b to 32n have the same internal configuration, and the decoders 32n are represented by the internal elements numbered 33n to 35n and 26n.

By the way, the conventional NOR type address decoder is shown in FIG.
Since the clock driver 35 including the two-stage buffers 35a and 35b drives all the NOR gates 36a to 36n as shown in FIG.
The load of 35) (composed of 35a and 35b) was always large. Note that 37a to 37n are output buffers.

Therefore, as in the case of the conventional NAND type address decoder, it has been a cause of layout restrictions and reduction of packaging density.

On the other hand, in the present embodiment, since the clock driver 27 is loaded only when a certain decoder 32a is not selected, the load capacity of the clock driver 27 can be greatly reduced. Therefore, the clock driver 27 can be configured with the minimum required chip area while ensuring high-speed response, and the degree of freedom in layout of the clock driver 27 can be greatly expanded.

[Effect]

According to the present invention, since the driving load of the clock buffer is extremely small, the size of the clock buffer can be reduced without sacrificing the operating speed. Alternatively, if the size is the same, a higher speed operation can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram of the basic logic of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of another embodiment of the present invention. 22a-22n: Many decoders (logical operation blocks), 23a: 2
Input AND gate (input gate part), 24a: Nch MOS transistor (one conductivity type transfer transistor), 25a: Pch M
OS transistor (other conductivity type precharge transistor), 26a: output buffer, 32a to 32n: multiple decoders (multiple logic operation blocks), 33a: 2-input OR gate (input gate section), 34a: Pch MOS Transistor (one conductivity type transfer transistor), 35a: Nch MOS transistor (other conductivity type pre-discharge transistor).

Claims (2)

(57) [Claims] 1. A plurality of logical operation blocks and one clock buffer, each of the logical operation blocks including an input gate unit, an output buffer, a transfer transistor of one conductivity type and a precharge transistor of another conductivity type. The input gate unit logically operates a plurality of input signals to generate a predetermined selection signal, and the transfer transistor receives the selection signal at a gate and outputs from the clock buffer to one of a source and a drain. The precharge transistor is connected to the input side of the output buffer, the gate of the precharge transistor receives a reverse phase signal of the clock signal, and the drain of the precharge transistor has a power supply equivalent to an H level. The output buffer is connected to the potential and the source is connected to the input side of the output buffer. § The semiconductor integrated circuit, characterized in that in synchronization with the clock signal and outputs a signal of the selection signal the same logic. 2. A plurality of logical operation blocks and one clock buffer are provided, and each of the logical operation blocks includes an input gate unit, an output buffer, a transfer transistor of one conductivity type, and a pre-discharge transistor of another conductivity type. The input gate unit logically operates a plurality of input signals to generate a predetermined selection signal, and the transfer transistor receives the selection signal at a gate and outputs from the clock buffer to one of a source and a drain. The pre-discharge transistor receives the clock signal of the opposite phase to the clock signal and the drain of which is connected to the input side of the output buffer. A source is connected to the input side of the output buffer while being connected to a potential Serial output buffer, a semiconductor integrated circuit and outputs a signal of the selection signal the same logic in synchronization with the clock signal.