JP2539523B2 - Method for manufacturing vertical field effect transistor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical field effect transistor, and more particularly to a method for manufacturing a vertical field effect transistor whose operating speed is increased.

[Conventional technology]

As related art, IEE Transactions on Electron Devices, Vol. 33, 3 (1986), 322-326 [IEE
E Transactions on Electron Devices, Vol.ED−33, No.3
(1986), p322-p326], there is a vertical field effect transistor having a CoSi ₂ gate electrode between the source and drain electrodes.

[Problems to be Solved by the Invention]

Cutoff frequency Ft which is an index representing the operation speed of the transistor element is written as _{F t = Gm / (2πC t} ). Here, Gm is the transconductance, C _t is the element-specific capacitance. In the above conventional device, the transconductance Gm is increased by increasing the impurity concentration in the channel region in order to increase the speed of the device. When the impurity concentration in the channel region is increased, the capacitance C _t is also increased at the same time, but since the increase in Gm exceeds the increase in C _t , the increase in F _t , that is, the speedup of the device can be achieved. However, if the impurity doping concentration is increased, the tunnel current at the Schottky metal-semiconductor interface increases, the device characteristics deteriorate, and the device stops operating. For this reason, speeding up is limited, and the maximum F _t was predicted to be around 40 GHz.

It is an object of the present invention to provide a method for manufacturing a vertical field effect transistor capable of increasing the speed by increasing the transconductance without increasing the impurity concentration in the channel.

[Means for solving the problem]

To achieve the above object, in the present invention, in a vertical field effect transistor having a source electrode, a drain electrode, and a gate provided between these electrodes, the distance between the source electrode and the drain electrode is such that no electrons are present. The first gate electrode, the second gate electrode, and the third gate electrode, which are formed to have an elastic scattering length or less and which use Schottky metal as the gate, have a current region of 2 or more.
The second and third gate electrodes are arranged so that the currents divided into two are gathered again in one current region, and the first, second and third gate electrodes are independently provided. The wiring structure allows voltage application.

[Action]

The first gate electrode of the transistor of the present invention divides the flow of electrons (current) from the source to the drain into two, a first electron flow and a second electron flow, and the second and third gate electrodes re-electron. It works to collect the streams together. Since the distance between the source electrode and the drain electrode is smaller than the inelastic scattering length of electrons, by applying an appropriate voltage to the second and third gate electrodes, the first electron flow and the second electron flow can be separated. It is possible to control the phase difference of. That is, if the electron wave function is approximated by a plane wave, and the electron wave function incident from the source is written as exp (-ikx), the first electron flow is exp {-i ( k + Δk ₁ ) x}. Here, k is a constant and x is a position coordinate.
On the other hand, the second electron flow is expressed as exp {-i (k + Δk ₂ ) x} due to the potential due to the third gate electrode, and finally the wave function F of the electron flow collected into one electron flow is F = exp {-i (k + Δk 1) x} + exp {-i (k + Δk 2) x} = exp {-i (k + Δk 1) x} _{[1 + exp {i (Δk 1} -Δk 2) x} ] and write Get burned. Therefore, exp {(i (Δk ₁ −Δk ₂ )
When x} is -1, F = 0, and no current flows in the drain. That is, the pinch-off state is set. Actually, if the statistical average is calculated by the distribution of the wave number k, F =
Although it does not become 0, the drain current can be reduced to about ⅕ as compared with the case where the gate voltage control is not performed, by controlling the gate voltage at about several millivolts. The value of the transconductance Gm in this case is 10 times or more that of the conventional element, and thus a higher-speed element can be provided without changing the channel concentration.

〔Example〕

 Examples of the present invention will be described below.

Example 1. FIG. 1 is a plan view showing a manufacturing process of a vertical field effect transistor of Example 1 and its XX sectional view, and FIG. 2 is a diagram showing operating characteristics of the example transistor. Fig. 1 (a)
In (g), n ⁺ − whose surface is cleaned in ultrahigh vacuum
On the Si (111) substrate 11, the molecular beam epitaxy (MBE) method was used at a substrate temperature of 700 ° C. for the n-type dopant Sb and the semiconductor S.
i is vapor-deposited at the same time to grow an n-Si layer 12 having a dopant concentration of about 1 × 10 ¹⁶ pieces / cm ³ by 400 Å. This substrate was taken out into the atmosphere and subjected to electron beam lithography and dry etching for 200
Etching is performed to a depth of Å [Fig. 1 (b) (h)].
Next, the surface is cleaned, and Co and Si are simultaneously vapor-deposited on the substrate so that the atomic ratio is 1: 2, that is, chemical equivalent, and only the top and bottom surfaces of the irregularities formed on the Si substrate by etching are deposited. Single crystal CoSi ₂ (cobalt silicide) 13 5
0Å grows [Fig. 1 (c) (i)]. In this case, the important point is that the deviation from the chemical equivalent must be kept within ± 1%. For example, when Co is excessive, CoSi ₂
Therefore, Si is sucked from the substrate, while when Si is excessive, problems such as the appearance of Si precipitates in CoSi ₂ occur. Also, the CoSi ₂ growth temperature must be 400-500 ° C. This is because the difference in lattice constant between Si and CoSi ₂ is above 500 ° C.
This is because it is 1.2%, so that strain relaxation occurs and the surface of CoSi ₂ becomes rough or becomes an island structure. For this reason,
It has to grow in a metastable state at about 500 ° C or less. Further, at 400 ° C. or lower, CoSi ₂ grows not only on the top and bottom surfaces of the irregularities on the Si substrate but also on the side walls. The interface energy between single crystal CoSi ₂ and Si substrate is the smallest on Si (111), and the interface energy on the side wall is always larger than on Si (111), so the temperature grows on the side wall by keeping it at 400 ° C or higher. The CoSi ₂ thus formed moves, and it becomes possible to grow single-crystal CoSi ₂ only on the top and bottom surfaces of the unevenness, that is, on the Si (111) surface.

Next, the substrate temperature is set to 300 to 400 ° C. and the i-Si layer 14 is set to 50 Å
Growth (Figs. 1 (d) and (j)), and further, by simultaneous vapor deposition of Si and Sb, a dopant concentration of about 1 x 10 ¹⁵ n / cm ³ n-
The Si layer 15 is grown by 550Å. At this time, it is necessary to grow at about 600 ° C. in order to obtain good crystallinity, but since the lattice constant difference between Si and CoSi ₂ is 1.2%, strain relaxation at 600 ° C. Surface roughness of CoSi ₂ occurs during Si crystal growth. In order to prevent this roughness, the i-Si layer 14 is once
It grows at a low temperature of ~ 400 ℃. This Si layer prevents the movement of atoms in CoSi ₂ when the n-Si layer is grown at 600 ° C., and thus prevents the surface of CoSi ₂ from becoming rough. Therefore, when using CoSi ₂ for the gate electrode layer and obtaining a Si / CoSi ₂ / Si double heterostructure where the interface is steep on the atomic order and has good Schottky characteristics, this Si layer is indispensable. . Next, the n ⁺ -Si layer 16 is grown to 1600Å, the substrate is taken out into the atmosphere, and etching is performed by using an electron beam drawing method and a dry etching method [FIG. 1 (e) (k)]. Furthermore, a SiO ₂ film 17 is grown at 400 ° C. by a chemical deposition method (CVD) and patterned by using photolithography,
By depositing aluminum and patterning again using photolithography, the second gate electrode wiring 1
8, the third gate electrode wiring 19, the source electrode wiring 20, and the first gate electrode wiring 21 were formed to fabricate a vertical field effect transistor [FIG. 1 (f) (l)].

FIG. 2 (a) shows a conceptual diagram of the operation of this device. In the figure, 1 is a source electrode, 2 is a drain electrode, 3 is a first gate electrode, 4 is a second gate electrode, and 5 is a third gate electrode. FIG. 2 (b) shows a drain current countermeasure when the first gate electrode and the second gate electrode are short-circuited.
The relationship of gate voltage is shown. In this way, the third gate voltage
The current is about 1/4 due to the change from 0 mV to 1.0 mV. Also,
When a voltage is further applied, as shown in the figure, vibration due to electron interference is observed.

Example 2 FIG. 3 is a cross-sectional view showing the transistor manufacturing process of Example 2. N ⁺ -GaAs (100) substrate with cleaned surface 22
N-GaAs with an n-type dopant concentration of about 1 × 10 ¹⁶ / cm ³
Layer 23 was grown at a growth temperature of 7 using metal organic pyrolysis (MOCVD).
400Å growth at around 00 ° C [Fig. 3 (a)], then take out the substrate from the MOCVD reaction tube and process it by electron beam (EB) drawing method and dry etching method as shown in Fig. 3 (b). To do. Subsequently, 50 Å of tungsten 24 is vapor-deposited [Fig. 3 (c)]. In this case, due to the shape of the etched GaAs layer, it does not adhere to the uneven side wall. Then, after cleaning the surface, the MOCVD method is used to grow n-GaAs 25 to about 600 liters again (FIG. 3 (d)). Tungsten is not a single crystal, but GaAs grows so as to wrap the tungsten and it is possible to embed tungsten in the single crystal GaAs. Next, the n ⁺ -GaAs layer 26 is grown to 1000 Å, taken out from the MOCVD reaction tube, and the growth of CVD SiO ₂ 27, patterning, vapor deposition of aluminum, and patterning are sequentially performed, and the second gate electrode wiring 28 and the third The gate electrode wiring 29 and the source electrode wiring 30 were formed to fabricate the device of FIG. 3 (e).

Also in the device manufactured on the GaAs substrate according to the second embodiment, the gate voltage is 0 mV → 1.0 mV in the same manner as the relationship obtained in the device manufactured on the Si substrate according to the first embodiment in FIG. 2B.
The current decreases sharply due to the change of, and the oscillation phenomenon caused by the electron interference by further applying the gate voltage was observed, and it was confirmed that the device operating at high speed as described in the section of'action 'can be realized. It was

〔The invention's effect〕

According to the present invention, unlike the conventional field effect transistor for high speed, the transconductance can be made 10 times or more without increasing the doping concentration of the channel, and thus a higher speed device can be obtained. It has become possible to increase the operating speed by about 3 times.

[Brief description of drawings]

1 (a) to 1 (l) are plan views and XX cross-sectional views showing respective steps of manufacturing a transistor of Example 1 of the present invention, and FIGS. 2 (a) and 2 (b) are Example 1 And FIG. 3A to FIG. 3E are cross-sectional views showing the manufacturing process of the transistor of Example 2 of the present invention. Explanation of symbols 11 …… n ⁺ −Si (111) substrate 12 …… n−Si layer 13 …… single crystal CoSi ₂ 14 …… i−Si layer 15 …… n−Si layer 16 …… n ⁺ −Si layer 17 …… CVD SiO ₂ film 18 …… Second gate electrode wiring 19 …… Third gate electrode wiring 20 …… Source electrode wiring 21 …… First gate electrode wiring 22 …… n ⁺ -GaAs (100) substrate 23 …… … N-GaAs layer 24 …… Tungsten 25 …… n-GaAs 26 …… n ⁺ -GaAs layer 27 …… CVD SiO ₂ film 28 …… Second gate electrode wiring 29 …… Third gate electrode wiring 30 …… Source Electrode wiring

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Taku Oshima 1-280 Higashi Koigokubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Eiichi Murakami 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. (56) References JP 64-19778 (JP, A) JP 63-7670 (JP, A) JP 1-120075 (JP, A) JP 60-201664 (JP , A) Actual development 63-132456 (JP, U) JP 54-757 (JP, B2) JP 57-9226 (JP, B2) JP 59-17547 (JP, B2)

Claims (1)

(57) [Claims] 1. A step of (1) growing a first n-type semiconductor layer on a substrate, (2) a projection of the first n-type semiconductor layer using an electron beam (EB) drawing method and a dry etching method. And (3) a step of vapor-depositing a gate electrode layer only on horizontal portions on the upper surface and the bottom surface of the convex portion of the processed first n-type semiconductor layer, (4) on the gate electrode layer. A step of growing a second n-type semiconductor layer in (5), a step of growing a third semiconductor layer on the second n-type semiconductor layer, and (6) a gate electrode layer on the bottom surface in the convex portion. The second n-type semiconductor layer and the third semiconductor layer so that the gate electrode layer on the upper surface sandwiched between the second n-type semiconductor layer and the third semiconductor layer is kept embedded. Etching step, (7) gate electrode layer obtained in the steps up to (6), second n-type half Body layer, and the third semiconductor layer chemical deposition method on the surface of growing a SiO ₂ film by (CVD), (8) using the photolithography of the gate electrode layer surface and the third semiconductor layer surface performs patterning of the SiO ₂ film to expose separated by the SiO ₂ film, aluminum was deposited further patterned surface, again joining the aluminum layer on the gate electrode layer using photolithography Vertical electric field effect, which comprises: a step of forming an electrode wiring by performing patterning so as to separate the gate electrode wiring portion formed into a gate electrode wiring portion and the source electrode wiring portion joined to the third semiconductor layer. Manufacturing method of transistor.