JPH08203897A - Semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device in which the resistivity of an embedded metallization layer composed of a super lattice intermetallic layer, which can be epitaxially grown thereon, is reduced. CONSTITUTION: A group III single atomic layer comprising an A1 or Ga single atomic layer 2 and an In single atomic layer 4, and an Ni single atomic layer 3 are laminated alternately on a compound semiconductor substrate 1 to form an NiAl molecular layer or an NiGa molecular layer which constitute a super lattice intermetallic layer together with an NiIn molecular layer. The super lattice intermetallic layer is employed as an embedded metallization layer and two times of the mean lattice constant of the super lattice intermetallic layer is set substantially equal to the lattice constant of the compound semiconductor substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a buried metal wiring layer used in a compound semiconductor device such as RHET (resonant tunneling hot electron transistor) and HBT (heterojunction bipolar transistor).

[0002]

2. Description of the Related Art In recent years, semiconductor devices using compound semiconductors such as GaAs have been put into practical use in order to increase the speed or increase the functionality of semiconductor devices, and the degree of integration is also improved in these compound semiconductor devices. Has been requested.

Conventionally, even when such a compound semiconductor device is integrated, all electrodes are taken out from the surface side by using lead electrodes or the like as in the silicon semiconductor integrated circuit device. Therefore, there was a limit to the improvement of the degree of integration depending on the accuracy of the photolithography technology.

In order to solve such a problem, the present inventors have used a buried intermetallic compound layer lattice-matched with a compound semiconductor as a wiring layer for a collector layer and the like, and a compound on the intermetallic compound layer. It has already been proposed that a semiconductor layer is epitaxially grown and a quantum effect memory device having a RHET structure is formed on the epitaxial growth layer to improve the degree of integration (Japanese Patent Application No. 6-200726).

6 to 8 are views for explaining a conventional quantum effect memory device according to the above proposal, FIG. 6 is an explanatory view of a laminated structure of a conventional quantum effect memory device, and FIG. 7 is a conventional quantum effect memory. FIG. 8 is an explanatory view of the structure of an intermetallic compound layer of the device, and FIG. 8 is a perspective view of a conventional quantum effect memory device.

First, refer to FIG. 6A. First, on a semi-insulating InP substrate 5, a 200 nm InGaAs buffer layer (In
_0.53 Ga _0.47 As layer) 6 and a 10 nm InAlAs buffer layer (In _0.52 Al _0.48 As layer) 7 are deposited by the MBE method, and then Ni cell, In cell and Al are deposited.
While raising the temperature of the cell or Ga cell to a predetermined temperature,
NiIn _0.24 Al _0.76 or NiIn _{0.23 which} is substantially lattice-matched with the InP substrate with the substrate temperature set at 250 ° C.
An intermetallic compound layer 26 having a composition ratio of Ga _0.77 is deposited to 100 nm.

The composition of the intermetallic compound layer 26 has a lattice constant.
Number of 2.886Å with NiAl system
In this case, twice this value and InP lattice constant of 5.86
The lattice mismatch with 9Å is -1.65%, so the lattice matching
For NiIn_0.24Al _0.76Must be
In addition, N using NiGa having a lattice constant of 2.887Å
NiIn for iGa system_0.23Ga_0.77Need to
is there.

I in the intermetallic compound layer 26
Tolerance of composition ratio for lattice matching to nP is ±
0.04, that is, a difference of about 0.2% when converted to lattice irregularity
And the thickness of the intermetallic compound layer 26 is set to 40 nm.
Also enables good growth, and the composition ratio tolerance
Is ± 0.02, that is, approximately 0.1% or less when converted to lattice irregularity.
Inside, the thickness of the intermetallic compound layer 26 becomes 100 nm.
However, good growth is possible. In addition, in the following explanation
InGaAs is In unless unless otherwise specified.
_0.53Ga_0.47InAlAs represents the composition of As.
In_0.52Al_0.48The composition of As is shown.

Then, 2n is formed on the intermetallic compound layer 26.
m n ⁺⁺ type InAlAs seed layer 12, 100 nm n
⁺⁺ type InGaAs layer 13, 100 nm n ⁺ type InGa
As collector layer 14, 60 nm i-type InAlGaAs
Barrier layer 15, 100 nm n ⁺ type InGaAs base layer 16, 4 nm i type InAlAs barrier layer 17, 4n
m i-type InGaAs well layer 18, 4 nm i-type In
AlAs barrier layer 19, 300 nm n ⁺ type InGaA
The s emitter layer 20 and the 50 nm thick n ⁺⁺ type InGaAs contact layer 21 are sequentially epitaxially grown using the MBE method.

FIG. 6B shows an energy band diagram on the conduction band side along the laminated structure of FIG. 6A. In this case, the i-type InAlAs barrier layer 17, i-type InGaAs
The well layer 18 and the i-type InAlAs barrier layer 19 form a resonance tunnel barrier structure.
Electrons are resonantly tunnel-injected through the quantum levels 27 formed in the GaAs well layer 18.

FIG. 7 is an enlarged view of the intermetallic compound layer 26.
P substrate, InGaAs buffer layer, and InAlAs
On the compound semiconductor substrate 28 including the buffer layer, In
_{The structure is such that 0.24} Al _0.76 monoatomic layers or In _0.23 Ga _0.77 monoatomic layers 29 and Ni monoatomic layers 30 are alternately provided. The intermetallic compound layer 26, even when deposited alternately an In _0.24 Al _0.76 monolayer or In _0.23 Ga _{0. 77} monoatomic layer 29 and the Ni monoatomic layer 30, also, NiI
Even when n _0.24 Al _0.76 or NiIn _0.23 Ga _0.77 itself is directly deposited, a substantially similar superlattice-like structure can be obtained.

It is because an intermetallic compound of Ni and a Group III element constitutes a tetragonal crystal structure only by Ni,
Moreover, since a tetragonal crystal structure is composed only of Group III elements and the other atom is incorporated into the center of the crystal structure of each other in a body-centered cubic system, a compound is formed. This is because the layers and the monatomic layers composed of the group III element are arranged alternately, and inevitably have a superlattice-like structure.

Since In and Ga or Al, which are group III elements, form a solid solution with each other, when In is mixed with NiGa or NiAl, which is an intermetallic compound for lattice matching, In is a Ga site of NiGa. Or NiAl
Preferentially substituting the Al site of
Ga monoatomic layers or InAl monoatomic layers are alternately arranged, and one Ni monoatomic layer and one InGa monoatomic layer or one InAl monoatomic layer form one NiIn layer.
_x Ga _1-x ternary molecular layer or single layer of NiIn _x Al _1-x
This will constitute a ternary molecular layer.

Next, referring to FIG. 8, the emitter mesa 22 and the base / collector mesa 2 will be described.
3 is formed by a wet etching method, the intermetallic compound layer 26 is sputter-etched to form a row address signal wiring layer.

Finally, through the contact hole provided in the protective insulating layer (not shown), n ^{+ +} type InGa on the emitter side is formed.
A quantum-effect memory device having a double-emitter structure having an electrode 25 connected to the As contact layer 21 to form a column address signal wiring layer extending in a direction substantially orthogonal to the row address signal wiring layer and exhibiting a differential negative characteristic. Is completed. A quantum-effect memory device having a double-emitter structure that exhibits differential negative characteristics is described in JP-A-6-112426.

[0016]

However, NiIn _0.24
Since the intermetallic compound layer made of Al _0.76 or NiIn _0.23 Ga _0.77 is a ternary intermetallic compound, it is inferior to the conventionally studied binary intermetallic compound in terms of resistivity. That is, NiIn _0.24 Al _0.76 or Ni
Since the distribution of In in In _0.24 Al _0.76 monolayer or In _0.23 Ga _0.77 monolayer constituting the In _0.23 Ga _0.77 is random, alloy scattering becomes dominant compared to binary intermetallic compounds, resistivity There was an increasing problem.

When an intermetallic compound layer made of such a ternary intermetallic compound is used as a buried wiring layer, it is necessary to increase the film thickness in order to reduce the resistance, but the film thickness is increased. If this is done, the characteristics of the epitaxial growth layer provided thereon will deteriorate, and there is a limit to the increase in film thickness.

Therefore, it is an object of the present invention to further reduce the resistivity of a buried wiring layer made of a superlattice intermetallic compound on which epitaxial growth is possible.

[0019]

FIG. 1 is an explanatory view of the principle configuration of the present invention, and means for solving the problems in the present invention will be described with reference to FIG. See FIG. 1. The present invention comprises two kinds of binary intermetallic compound molecular layers in which monoatomic layers 2 and 4 made of a group III element and Ni monoatomic layers 3 are alternately laminated on a compound semiconductor substrate 1. In a semiconductor device using a superlattice intermetallic compound layer as a buried wiring layer, the binary intermetallic compound molecular layer is composed of one of Group III elements Al and Ga, a molecular layer made of Ni, and a NiIn molecular layer. The double lattice constant of the superlattice intermetallic compound layer and the lattice constant of the compound semiconductor substrate are substantially equal to each other.

In the present invention, the compound semiconductor substrate 1 is I
nP substrate and the superlattice intermetallic compound layer is {(N
iAl molecular layer) _3n / (NiIn molecular layer) _n } _m or {(NiGa molecular layer) _3n / (NiIn molecular layer) _n } _m , and n is 1 or 2 and m is an integer. Is characterized in that.

The present invention also provides InGa on an InP substrate.
At least one of the As layer and the InAlAs layer is provided as a buffer layer.

[0022]

[Function] By making the value of twice the average lattice constant of the superlattice intermetallic compound layer substantially equal to the lattice constant of the compound semiconductor substrate 1, effective lattice matching can be obtained, and the superlattice intermetallic compound layer can be formed. By using two kinds of binary intermetallic compound molecular layers, alloy scattering is suppressed and the resistivity decreases,
Since it is not necessary to increase the thickness of the embedded wiring layer,
The crystallinity of the epitaxial layer provided thereon can be improved. It should be noted that in this case, substantially equal means that the lattice mismatch with the compound semiconductor substrate is 0.2% or less.

Further, an InP substrate is used as the compound semiconductor substrate 1, and {(Ni
Al molecular layer) _3n / (NiIn molecular layer) _n } _m or {(N
By using any one of (iGa molecular layer) _3n / (NiIn molecular layer) _n } _m , very good lattice matching can be achieved.

Further, by providing at least one of the InGaAs layer and the InAlAs layer as a buffer layer on the InP substrate, particularly, by using the buffer layer of In _0.53 Ga _0.47 As composition and In _0.52 Al _0.48 As composition, it is more preferable. It is possible to grow a different epitaxial layer.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process of a quantum effect memory device according to a first embodiment of the present invention will be described with reference to FIGS. Note that FIG. 3C, FIG. 4E, and FIG. 5G are in the direction along the row address signal wiring layer, that is, AA ′ in FIG.
FIG. 3 is a cross-sectional view taken along the direction of FIG.
5F and FIG. 5H are cross-sectional views in the direction along the column address signal wiring layer, that is, in the direction along BB ′ in FIG.

Referring to FIG. 2 (a), the (001) -faced InP substrate 5, which has been subjected to degreasing treatment with an organic solvent and surface etching treatment, is fixed to a Mo block (not shown) and placed in an ultrahigh vacuum chamber. Introduced,
Thermal cleaning is performed in an As atmosphere of 3 × 10 ⁻⁶ Torr to remove the oxide film on the surface, and then 100 nm of InGa lattice-matched with the InP substrate 5 is formed.
As buffer layer (In _0.53 Ga _0.47 As layer) 6 and 10
nm InAlAs buffer layer (In _0.52 Al _0.48 As
Layer 7 is deposited by the MBE method.

At this time, RHEED (Reflectiv
e High Energy Electron Di
ffraction) pattern is reconstructed (Recon
arsenic stabilization surface of 2 × 4
Structure, that is, the lattice spacing in the X direction is the ideal lattice constant of 2
In the RHEED pattern, the lattice spacing in the Y direction is four times the ideal lattice constant, and in this RHEED pattern, the streak pattern is usually seen, and the radiation showing the better crystallinity is obtained. Kikuchi line and 0
The following Laueling was observed.

The InGaAs buffer layer and I
The nAlAs buffer layer is provided for facilitating the deposition of the superlattice intermetallic compound layer, but it does not necessarily have to be two layers as in the embodiment, and only one of them may be provided. In order to make the interface between the intermetallic compound and the semiconductor steep, InAlA is used for Ni (InAl).
The s layer is also InGaA for Ni (InGa).
The s layer is preferred.

In the examples of the present invention, unless otherwise specified, InGaAs is In _0.53 Ga _0.47.
Represents a composition of As, InAlAs is In _0.52 Al
The composition is _0.48 As, but is not limited to this composition.

Next, the background arsenic causes N
In order to prevent iAs from being formed, after the buffer layer was grown, the shutter of the As cell was closed and the temperature of the As cell was lowered to room temperature.
With the temperature of the Al cell raised to 20 ° C. and the temperature of the Al cell raised to 920 ° C. and the substrate temperature set to 250 ° C., In is supplied once every four cycles so that the Al monoatomic layer 8 or I
The n monoatomic layers 10 and the Ni monoatomic layers 9 are alternately deposited to effectively form a periodic structure composed of three NiAl molecular layers and one NiIn molecular layer, and the entire 200 molecular layers (approximately A superlattice intermetallic compound layer 11 of 60 nm) is formed.

The growth time of each monoatomic layer in this case is determined on the basis of the previously measured growth rate of the Ni layer in the case of the Ni monoatomic layer, and in advance for the In monoatomic layer and the Al monoatomic layer. Measured R for InAs and AlAs growth
As determined from HEED oscillations, there was a 2 second pause between each monolayer growth.

Further, in the RHEED pattern at this time, a sharp streak pattern is observed, showing that the crystallinity is relatively good, and the resistivity of the superlattice intermetallic compound layer 11 is 15 to 30 μΩ. -Cm, which is the resistivity of a conventional ternary intermetallic compound, 20 to 60
It was confirmed that the resistivity was lower than μΩ · cm.

The superlattice intermetallic compound layer 11 is a NiAl molecular layer formed by the Al monoatomic layer 8 and the Ni monoatomic layer 9 and I.
The structure in which the n monoatomic layer 10 and the NiIn molecular layer formed by the Ni monoatomic layer 9 are periodically arranged at a ratio of 3: 1, that is,
Although it has a superlattice structure represented by {(NiAl molecular layer) ₃ / (NiIn molecular layer) ₁ } ₅₀ , it is not necessarily limited to such a layer structure.

That is, the superlattice intermetallic compound layer 11 is
The general formula {(NiAl molecular layer) _3n / (NiIn molecule) is NiIn _0.25 Al _0.75 satisfying the condition of x = 0.24 ± 0.04, which is the condition of lattice matching with InP having an average composition of NiIn _x Al _1-x. Layer) _n } _m (n and m are integers)
The embedded wiring layer having a certain thickness can be formed with this structure.

Further, by setting n to an integer of 2 or less, that is, 1 or 2, the film thickness can be kept below the critical film thickness at which misfit dislocations do not occur even in each layer molecular layer. Incidentally, the lattice mismatch of NiAl with respect to InP is 1.65% and its critical film thickness is about 6 nm.
The lattice mismatch of iIn with InP is 5.3% and its critical film thickness is about 1 nm or less.

The process after that is the same as that of the conventional quantum effect memory device. First, 2 nm is formed on the superlattice intermetallic compound layer 11.
N ⁺⁺ type InAlAs seed layer 12, 100 nm n ⁺⁺
-Type InGaAs layer 13, 100 nm n ⁺ -type InGaA
s collector layer 14, 60 nm i-type InAlGaAs barrier layer 15, 100 nm n ⁺ -type InGaAs base layer 16, 4 nm i-type InAlAs barrier layer 17, 4 nm
I-type InGaAs well layer 18, 4 nm i-type InA
lAs barrier layer 19, 300 nm n ⁺ type InGaAs
The emitter layer 20 and the 50 nm thick n ⁺⁺ type InGaAs contact layer 21 are sequentially epitaxially grown using the MBE method.

In this case also, as in the conventional example, i-type InAl
A resonance tunnel barrier structure is formed by the As barrier layer 17, the i-type InGaAs well layer 18, and the i-type InAlAs barrier layer 19, and electrons are resonant tunneled through the quantum levels formed in the i-type InGaAs well layer 18. Will be injected.

[0038] The substrate temperature at the time of each layer of deposition in the case of n ⁺⁺ type InAlAs seed layer 12 at the 200 ° C., in the case of other layers is 500 ° C., also the n ⁺⁺ type In
The AlAs seed layer 12 is provided to enhance the steepness of the interface with the superlattice intermetallic compound layer 11.

Next, as shown in FIGS. 3C and 3D, n ⁺⁺ type InGa is formed by wet etching.
As contact layer 21 to i-type InAlAs barrier layer 1
7 is patterned to form a double emitter structure consisting of two emitter mesas 22.

4E and 4F, an n ⁺ type I is then formed by wet etching.
By patterning the nGaAs base layer 16 to the n ⁺⁺ type InAlAs seed layer 12 to form the base collector mesa 23, the quantum effect memory element constituting one memory unit is separated from other quantum effect memory elements.

5 (g) and 5 (h), the superlattice intermetallic compound layer 11 and the InAlAs buffer layer 7 are patterned into stripes extending in the arrangement direction of the two emitter mesas by sputter etching. After forming the row address signal wiring layer, Si
An insulating film 24 such as O ₂ is deposited, and n ^{++ of} each emitter mesa is deposited.
A contact hole for the InGaAs contact layer 21 is provided, and then a conductive layer of Au, Ge or the like is deposited and patterned to form two column address signal wiring layers that are substantially orthogonal to the row address signal wiring layer.
5, the quantum effect memory device is completed.

In this way, {(Ni
Since a low-resistivity superlattice intermetallic compound layer composed of Al molecular layer) _3n / (NiIn molecular layer) _n } _m is used, low resistance can be obtained without increasing the thickness of the embedded wiring layer. Since the epitaxial growth layer provided thereon is a good quality single crystal without misfit dislocations, the characteristics of the double emitter transistor formed in this epitaxial growth layer are also good.

Next, as an embedded wiring layer, {(NiGa
A second embodiment of the present invention using a low-resistivity superlattice intermetallic compound layer composed of (molecular layer) _3n / (NiIn molecular layer) _n } _m will be described. This second embodiment is exactly the same as the first embodiment except for the step of forming the superlattice intermetallic compound layer, so only the step of forming the superlattice intermetallic compound layer will be described.

100 nm I that is lattice-matched to the InP substrate
After forming the nGaAs buffer layer and the InAlAs buffer layer of 100 nm, the shutter of the As cell was closed and the temperature of the As cell was lowered to room temperature.
0 ° C., In cell at 520 ° C., and Ga cell at 86 ° C.
In addition to raising the temperature to 0 ° C. and setting the substrate temperature to 250 ° C., In is supplied once every four cycles.
a monoatomic layer or In monolayer and In monolayer are alternately deposited to form a total of 200 molecular layers (about 60 nm) {(NiGa molecular layer) ₃ / (NiIn molecular layer) ₁ } ₅₀
A superlattice intermetallic compound layer is formed.

Also in the case of this superlattice intermetallic compound layer, the average
The composition is NiIn_xGa_1-xLattice matching of InP
Ni that satisfies the condition of x = 0.23 ± 0.04
In _0.25Ga_0.75General formula {(NiGa molecular layer)_3n
/ (NiIn molecular layer)_n｝_m(N and m are integers)
This is a good thing, and with this configuration
It becomes possible to form a wiring layer.

Also in this case, n is an integer of 2 or less, that is,
By setting it to 1 or 2, the film thickness can be kept below the critical film thickness at which misfit dislocations do not occur even in each molecular layer. Incidentally, the lattice mismatch of NiGa with InP is 1.62% and its critical film thickness is about 6 nm, and the lattice mismatch of NiIn with InP is 5.3.
%, The critical film thickness is about 1 nm or less.

In this case, the average composition NiIn _0.25 Ga _0.75
Is 0.02 from the lattice matching condition x = 0.23, and is 0.01 from the viewpoint that the film thickness cannot be made too thick. {(NiAl molecular layer) _3n /
(NiIn molecular layer) _n } _m
Is cheaper and easier to handle than Ga, the second embodiment is superior in terms of manufacturing process.

If the steepness of the superlattice intermetallic compound / semiconductor interface is taken into consideration, Ni is used for InGaAs.
(InGa) system, but also Ni for InAlAs
The (InAl) system is preferable.

Subsequent steps are exactly the same as those in the first embodiment to form a quantum effect memory device.

Although the quantum effect memory device has been described in the above embodiments, it goes without saying that it can be applied to other compound semiconductor devices, for example, HBT (heterojunction bipolar transistor) and HET. (Hot electron transistor), RHET (resonance tunneling hot electron transistor), etc. are also targeted, and further, metal base transistors are also targeted.

[0051]

According to the present invention, a buried wiring layer lattice-matched with InP is formed of {(NiAl molecular layer) _3n / (NiI
n molecular layer) _n } _m or {(NiGa molecular layer) _3n / (N
By constructing the superlattice intermetallic compound layer composed of iIn molecular layer) _n } _m , it is possible to prevent an increase in resistivity due to alloy scattering, and therefore, it is not necessary to increase the film thickness of the embedded wiring layer. It is possible to improve the crystallinity of the epitaxial layer grown on it, which greatly contributes to the improvement of the integration degree of the compound semiconductor device.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory view of a manufacturing process up to the middle of the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process up to the middle of FIG. 2 and subsequent steps of the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a manufacturing process up to the middle of FIG. 3 and subsequent steps of the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of the manufacturing process of FIG. 4 and subsequent steps of the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a laminated structure of a conventional quantum effect memory device.

FIG. 7 is an explanatory diagram of a structure of an intermetallic compound layer of a conventional quantum effect memory device.

FIG. 8 is a perspective view of a conventional quantum effect memory device.

[Explanation of symbols]

1 Compound semiconductor substrate 2 Al or Ga monoatomic layer 3 Ni monoatomic layer 4 In monoatomic layer 5 InP substrate 6 InGaAs buffer layer 7 InAlAs buffer layer 8 Al monoatomic layer 9 Ni monoatomic layer 10 In monoatomic layer 11 Superlattice Intermetallic compound layer 12 n ⁺⁺ type InAlAs seed layer 13 n ⁺⁺ type InGaAs layer 14 n ⁺ type InGaAs collector layer 15 i type InAlGaAs barrier layer 16 n ⁺ type InGaAs base layer 17 i type InAlAs barrier layer 18 i type InGaAs well Layer 19 i-type InAlAs barrier layer 20 n ⁺ type InGaAs emitter layer 21 n ⁺⁺ type InGaAs contact layer 22 emitter mesa 23 base collector mesa 24 insulating film 25 electrode 26 intermetallic compound layer 27 quantum level 28 compound semiconductor substrate 29 In _0.24 Al _0.76 (In _0.23 Ga _0.77 ) _Monoatomic layer 30 Ni Monoatomic layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/73 H01L 29/205 29/72

Claims (3)

[Claims] 1. A superlattice intermetallic compound consisting of two kinds of binary intermetallic compound molecular layers formed by alternately laminating a monoatomic layer made of a group III element and a Ni monoatomic layer on a compound semiconductor substrate. In the semiconductor device using the layer as an embedded wiring layer, the binary intermetallic compound molecular layer includes a molecular layer made of one of Group III elements Al and Ga, Ni, and NiI.
2. A semiconductor device comprising an n-molecular layer, wherein the average lattice constant of the superlattice intermetallic compound layer is twice the lattice constant of the compound semiconductor substrate. 2. The compound semiconductor substrate is an InP substrate, and the superlattice intermetallic compound layer is {(NiAl molecular layer) _3n / (NiIn molecular layer) _n } _m or {(NiGa.
2. The semiconductor device according to claim 1, wherein the molecular layer is _3n / (NiIn molecular layer) _n } _m , and n is 1 or 2, and m is an integer. 3. The semiconductor device according to claim 2, wherein at least one of an InGaAs layer and an InAlAs layer is provided as a buffer layer on the InP substrate.