JP2536404B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device which enables a high frequency test by a prober on a wafer.

[0002]

2. Description of the Related Art In recent years, integration of semiconductor integrated circuit devices has progressed, and it has become difficult to perform a high frequency test on a wafer by a prober. Therefore, a semiconductor integrated circuit device incorporating a ring oscillator and a frequency divider is known (see Japanese Patent Laid-Open No. 59-181548). That is, as shown in FIG. 3, a ring oscillator 2 composed of an odd number of inverting gates is connected to the input of the circuit under test (logic circuit) 1 through a fuse 4 and is connected to the output of the circuit under test 1. Is the frequency divider 3
And the frequency of the output of the circuit under test 1 is divided to a measurable frequency. The delay time of the circuit under test 1 can be calculated by measuring the output frequency of the frequency divider 3 with a prober. After the test, fuses 4 and 5
To melt down.

Another semiconductor integrated circuit device capable of high-frequency testing on a wafer by a prober is shown in FIG. 4 (see Japanese Patent Laid-Open No. 60-89937). The device shown in FIG. 4 evaluates the delay time of the basic gate of the circuit under test (gate array etc.) and is incorporated in the circuit under test. Reset circuit 6 and counter circuit 7
And an output circuit 8 is added. Referring to the operation timing of FIG. 5, the reset circuit 6 generates the reset signal RST shown in FIG. 5C in response to the external reset clock IRESET of FIG. 5B, and as a result, the frequency divider 3
The counter circuit 7 is reset (initialized), and the oscillation of the ring oscillator 2 is stopped. Next, when the external reference clock ICLK shown in FIG. 5A becomes high level (“1”), the oscillation of the ring oscillator 2 starts as shown in FIG. 5D. At the same time, since the count enable terminal (CE) of the counter circuit 7 becomes high level ("1"), the counter circuit is released from reset and the count input terminal (C) of FIG. Start counting the clocks shown in. This counting operation continues only while the reference clock ICLK is at high level (“1”),
When CLK becomes low level (“0”), the ring oscillator 2 stops oscillation because the loop is opened. In this way, the number of pulses of the internal clock when the reference clock ICLK is at the high level is held in the counter circuit 7,
The value is output by the output circuit 8, and as a result, the delay time of the basic gate of the ring oscillator 2 can be obtained.

[0004]

However, as shown in FIG.
In the semiconductor integrated circuit device shown in FIG. 1, although it is lower than the operating frequency of the circuit under test 1, frequency measurement is directly required, and as a result, a special test device is required, and a professional
There is a problem that measurement accuracy and reproducibility are poor due to contact resistance with the bar. Further, in the semiconductor integrated circuit device shown in FIG. 4, since the number of pulses in the reference clock ICLK is counted, the generation of the reference clock ICLK and the signal IRES
It requires correct phase adjustment with ET, and therefore also requires a special test device, and since the delay time is obtained by the digital and DC output of the counter circuit 7, the actual operating frequency cannot always be obtained. There are challenges. Therefore, an object of the present invention is to provide a semiconductor integrated circuit device capable of performing a high frequency test by a prober on a wafer that does not require a special test device, has high measurement accuracy, good reproducibility, and can obtain an actual operating frequency. To provide.

[0005]

In order to solve the above problems, the present invention provides an oscillator circuit for generating a signal of a predetermined frequency in a circuit under test, a delay circuit for delaying an output signal from the circuit under test, and a delay circuit. delayed signal and multiplying circuit for multiplying the output signal from the circuit under test from the integrating circuit for integrating the output of the multiplication circuit is provided, professional output of the integration circuit
I measured it with a server.

According to the above means, the delay circuit, the multiplication circuit and the integration circuit act as a frequency / voltage conversion circuit ,
The analog DC output of the circuit, that is, the frequency / voltage conversion circuit
The operating frequency of the circuit under test is measured by the output of the circuit .

[0006]

1 is a circuit diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. In FIG. 1, the circuit under test 1 is, for example, a prescaler circuit and has an input terminal I.
It has N and output terminals OUT1 and OUT2. in this case,
The output terminals OUT1 and OUT2 have the same frequency, and thus may be the same terminal, and the output terminals OUT1 and O2 may be the same.
UT2 may be replaced by a hybrid circuit. The ring oscillator 1 generates a signal having a frequency equal to or higher than the operating frequency of the circuit under test 1. Reference numeral 9 is a delay circuit, 10 is a multiplication circuit, which is a mixer circuit in analog, an exclusive OR circuit in digital, and 11 is an integrating circuit.

The above delay circuit 9, multiplication circuit 10 and integration circuit 11 constitute a frequency / voltage conversion circuit. That is, the signal at the output terminal OUT1 of the circuit under test 1 is input to one input of the multiplication circuit 10 via the delay circuit 9, and the signal at the output terminal OUT2 of the circuit under test 1 is input to the other input of the multiplication circuit 10. It is entered directly. At this time, if the two signal voltages input to the multiplication circuit 10 are v ₁ and v _2, and the operating angular frequency of the circuit under test 1 is ω, then v ₁ = V ₁ · sin (ωt−θ) − (1 ) V ₂ = V ₂ · sin ωt (2) where V ₁ and V ₂ are constants, and θ is the delay phase of the delay circuit 9. Here, if the electrical length of the delay circuit 9 is L, and the frequency and wavelength of the input signal to the delay circuit 9 are f and λ, then θ = (L / λ−n) · 2π = 2πf · L−2πn = ωL -2πn- (3) where n is a constant. Therefore, the delay phase θ of the delay circuit 9 and the input frequency f (ω) are in a proportional relationship.

When the multiplication circuit 10 is composed of a mixer circuit, the output voltage v ₀ of the multiplication circuit 10 is
From equations (1) and (2), v ₀ = V ₁ · V ₂ = V ₁ · V ₂ · sin (ωt−θ) · sin ωt = (½) · V ₁ · V ₂ · (cos θ-cos (2ωt−θ)) − (4). Since the AC component of the second term of the equation (4) is removed by the integrating circuit 11, the output voltage v ₀ 'of the integrating circuit 11
Is a direct current component with v ₀ '= (1/2) · V ₁ · V ₂ · cos θ ─ (5). Output voltage v of this integration circuit 11
_{0'is available} at the external output terminal 12.

As described above, the delay phase θ and the frequency f have a proportional relationship. Therefore, the relationship between the frequency f and the output voltage v ₀ 'is obtained from the equation (5) as shown in FIG. Therefore, the frequency f can be known from the output voltage v ₀ '. It should be noted that the delay circuit 9 shown in FIG. 1 may be provided with a circuit having a desired delay such as a phase modulator, thereby changing the frequency detection range.

[0010]

As described above, according to the present invention, since an analog DC voltage is obtained by frequency / voltage conversion characteristics without directly measuring a high frequency signal, a special test device is not required, A high frequency test can be performed by a prober, and an actual operating frequency with high measurement accuracy and good reproducibility can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a graph showing frequency / voltage characteristics of FIG.

FIG. 3 is a block circuit diagram showing a conventional semiconductor integrated circuit device.

FIG. 4 is a block circuit diagram showing another conventional semiconductor integrated circuit device.

5 is a timing diagram illustrating the operation of the apparatus of FIG.

[Explanation of symbols]

 1-Circuit under test 2-Ring oscillator 3-Frequency divider 4, 5-Fuse 6-Reset circuit 7-Counter circuit 8-Output circuit 9-Delay circuit 10-Multiplier circuit 11-Integrator circuit 12-External terminal

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit device having a circuit under test (1), an oscillation circuit (2) for generating a signal of a predetermined frequency in the circuit under test, and a delay for delaying an output signal from the circuit under test. A circuit (9), a multiplication circuit (10) for multiplying the delayed signal from the delay circuit and an output signal from the circuit under test, and an integration circuit (11) for integrating the output of the multiplication circuit The analog DC output of the integrating circuit is measured by a prober.
The semiconductor integrated circuit device according to feature that it has to measure the operating frequency of the circuit under test by a constant. 2. The semiconductor integrated circuit device according to claim 1, wherein the delay circuit has a built-in phase modulator.