JP3352793B2 - Temperature measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance of a thermistor or the like.
The present invention relates to an apparatus for measuring a temperature using a temperature element.

[0002]

2. Description of the Related Art As a circuit for measuring a temperature using a resistance temperature element such as a thermistor, for example, a circuit using a bridge circuit and a circuit using an oscillation circuit are known.

[0003]

However, in a bridge circuit or the like, the circuit is complicated and easily affected by self-heating, and it is difficult to obtain a digital signal. Consumption and accuracy were insufficient.

An object of the present invention is to provide a high-accuracy, low-cost, low-power-consumption temperature measuring device in view of the above points.

[0005]

According to the present invention, there is provided a pulse generator having a resistance temperature element and a reference resistor connected to one end of a capacitor, and first and second output terminals for generating a predetermined pulse signal for measurement. Means and through the resistance temperature element
A first 3-state buffer having an output terminal connected to the capacitor, an input terminal connected to a first output terminal of the measuring pulse generating means, and a control terminal connected to a second output terminal of the pulse generating means . And an output terminal connected to the capacitor via the reference resistor, an input terminal connected to the second output terminal of the pulse generation means, and a control terminal connected to the first output terminal of the pulse generation means. And a predetermined voltage level when the first and second 3-state buffers are turned on / off to charge or discharge a capacitor via the resistance temperature element or the reference resistance. And a measuring means for measuring the time to be calculated and calculating the temperature from the ratio.

[0006]

FIG. 1 is a structural explanatory view showing an embodiment using the discharge characteristics of the present invention.

In the figure, A is a detection unit, and B is a processing unit such as a microcomputer (CPU). Detector A
Is one end 1a of a capacitor 1 having a capacitance Co with the ground.
A resistance temperature element 21 such as a thermistor having a resistance value Rt and a reference resistance 22 having a resistance value Ro are connected to the first and second pulse generating means 4 for generating a pulse signal for measurement of the processing section B.
Output terminals 4a and 4b, resistance temperature element 21 , reference resistance 2
First between the 2, second 3-State Buffer (3-state gate as a switching means) 31 and 32, provided, and the third 3-State Buffer 33 is provided at one end 1a of the capacitor 1 ing. That is, the output terminal of the first 3-state buffer 31 is connected via the resistance temperature element 21.
Connected to one end 1a of the capacitor 1 and its input terminal is connected to the first output terminal 4a of the pulse generating means 4, a control terminal is connected to the second output terminal 4b of the pulse generating means 4 . Similarly, the second 3-state buffer 32
Is connected to one end of the capacitor 1 via the reference resistor 22.
1a and its input terminal is connected to the second
The control terminal is connected to the output terminal 4b and the pulse generation means 4
Is connected to the first output terminal 4a. The third 3-state buffer 33 has its control terminal grounded and is always at L level.
Since the level is enabled, an H-level output is generated when the potential at one end 1a of the capacitor 1 connected to the input terminal is equal to or higher than a predetermined threshold level Vth. This signal is inverted by the inverter 5 of the processing means B and supplied to the first and second AND means 71 and 72. First AND means 71
Is the output P1 of the first output terminal 4a of the pulse generation means 4.
The gate of the third 3-state buffer 33 is closed by the output of the third 3-state buffer 33, and the number of pulses corresponding to the charging time during this period is counted by the resistance temperature element side counter 81. Further, the second AND means 72 allows the pulse of the clock pulse generating means 6 to pass through the output P2 of the second output terminal 4b of the pulse generating means 4, and closes the gate by the output of the third 3-state buffer 33. The number of pulses corresponding to the charging time during this period is counted by the reference resistance side counter 82. The output count values of the counters 81 and 82 are
Then, the ratio is calculated and the temperature is calculated. Processing unit B
The whole can be configured as software as a CPU and realized.

Next, the operation will be described with reference to FIG. At the beginning of the interval I, since no output is generated from any of the output terminals 4a and 4b of the pulse generating means 4, the first and second signals are output.
The L-level is applied to the control terminals of the 3-state buffers 31 and 32, and the input is at the L-level. Therefore, the output is at the L-level and the charge of the capacitor 1 is discharged. The input of the third 3-state buffer 33 is the threshold Vth. Therefore, the output is at the L level.

In the section II, the first of the pulse generating means 4
When only the output P1 of the output terminal 4a goes high, the first
The output of the 3-state buffer becomes H level, the capacitor 1 starts charging at this H level voltage via the resistance temperature element 21, and the control terminal of the second 3-state buffer 32 becomes H level. Its output becomes high impedance, and the output of the third 3-state buffer 33 is at L level and the output of the inverter 5 is H because its input is equal to or lower than the threshold value Vth. The H level of the output terminal 4a of the pulse generation means 4 is input to the first AND means 71,
Since the output of the inverter 5 is also H, the pulse of the frequency fo of the clock pulse generator 6 passes, and the resistance temperature element side counter 81 starts counting. When the voltage of the pulse generating means 4 continues to be charged in the capacitor 1 and the voltage exceeds a predetermined voltage level threshold Vth of the third 3-state buffer 33, the output goes from L to H level, Changes from H to L, the AND means 71 does not pass the pulse of the clock pulse generating means 6, and the counter 81 stops counting. The time corresponding to the charging time ta of the capacitor 1 is counted by the counter 81. This section II may be shifted to the next section as soon as the counting process is completed, or the pulse generating means 4 may generate a predetermined pulse width for this period.

In section III, the outputs P1 and P2 of the first and second output terminals 4a and 4b of the pulse generating means 4 are both at L level, and the first and second 3-state buffers 3 and
The electric charge of the capacitor 1 is discharged via the first and second terminals 32 and becomes zero level.

In the period IV, the output PI of the first output terminal 4a of the pulse generation means 4 is at L level,
The output PI of b is at the H level, the charging of the capacitor 1 is started via the reference resistor 22, and the output of the first 3-state buffer 31 is high impedance. The output of the third 3-state buffer 33 is at L level, the output of the inverter 5 is at H level and input to the second AND means 72, and the H level of the output terminal 4b of the pulse generating means 4 is also input. 6 and the reference resistance counter 82 starts counting. When the charging of the capacitor 1 progresses and becomes higher than the threshold value Vth of the third 3-state buffer, the output thereof becomes H level, the output of the inverter 5 becomes L level, and the second AND 72 does not pass the pulse. , The counter 82 stops counting. The charging time during this period is defined as tb, and the temperature is measured from the ratio of the count values of the counters 81 and 82 corresponding to the times ta and tb. Next, in the section V, as in the section I, the output of the pulse generation means 4 is at the L level for both P1 and P2, the electric charge of the capacitor 1 is discharged, and the operation from the section II onward is repeated.

The principle of measurement is as follows. Now, assuming that the H level of the voltage Vcc in FIG. 1 is supplied to a time constant circuit (charge / discharge circuit) of the resistance Rt of the resistance temperature element 21 and the capacitance Co of the capacitor 1, the voltage output V1 of the capacitor 1 becomes It becomes an expression.

V1 = Vcc {1−exp (−t / CoRt)} (1) Assuming that the charging time until this output reaches the threshold value of the 3-state buffer 33 is ta, the following equation is obtained.

Vth = Vcc {1−exp (−ta / CoRt)} (2) When this is arranged, the following equation is obtained.

Ta = CoRtln (Vcc / (Va−Vth)) (3) The charging time is similarly set to t for the reference resistor 22 of the resistor Ro.
If b is obtained, the following equation is obtained.

Tb = CoRoln (Vcc / (Vcc−Vth)) (4) If the ratio of both sides of the equations (3) and (4) is taken, then ta / tb = Rt / Ro (5)

Each of the count values M1,
Since M2 is: M1 = fo · ta, M2 = fo · tb (6), the ratio is M1 / M2 = ta / tb (7), and M1 / M2 = ta / tb = Rt / Ro (8) The count ratio M / M2 is determined by the resistance temperature element 21
Is proportional to the resistance value Rt corresponding to the temperature, and the temperature is obtained from the ratio of the count values.

FIG. 3 shows another embodiment of the present invention.
The one using the charging characteristics in FIG. 1 uses the discharging characteristics, and the same reference numerals as those in FIG. 1 denote the same components.

The difference from FIG. 1 is that in the 3-state buffers 31, 32, and 33, the signal at the input terminal at the H level at the control terminal appears at the output terminal as it is. Also, since the H level which is the positive voltage Vcc is supplied to the control terminal of the third state buffer 33, it is always in the operating state.
When the voltage falls below the threshold value Vch, the output becomes L. Also, 3
-The output of the state buffer 33 is supplied to the AND gates 71 and 72 as it is, while the output of the pulse generation means 4 is supplied to the AND means 71 and 7 via the inverters 51 and 52.
2 is supplied. This means that the processing unit B
Can be similarly configured by software using a microcomputer or the like.

Referring to FIG. 4, the schematic operation will be described. In section I, the outputs of the output terminals 4a and 4b of the pulse generating means 4 are at H level, and the first and second 3-state buffers 3
The control terminals 1 and 32 are at the H level, the output of each of them is at the H level, and the saturation voltage is supplied to the capacitor 1.

In the section II, the output of the first output terminal 4a of the pulse generating means 4 is at L level, and the control terminal of the first 3-state buffer 31 is at H level from the second output terminal 4b. The output of the 3-state buffer 31 becomes L level, and the electric charge charged in the capacitor 1 is discharged through the temperature resistance element Rt. At this time, the output of the third 3-state buffer is at H level, and the L level of the first output terminal 4a is set to H by the inverter 51. The output is input to the first AND means 71 and passes through the frequency fo of the clock pulse generating means 6. Start counting. Since the control terminal of the second 3-state buffer 32 is at L level, its output is high impedance. When the discharge continues and the voltage of the capacitor 1 falls below the threshold value Vth of the third-state buffer 33, the output becomes L, the AND means 71 closes, and the resistance temperature element side counter 8
1 performs counting corresponding to the charging time ta.

In the section III, the outputs of the first and second output terminals 4a and 4b of the pulse generating means 4 are both at H level and the outputs of the first and second 3-state buffers 31 and 32 are at H level and the capacitors are at H level. 1 is charged.

In the section IV, the second output terminal 4b of the pulse generating means 4 becomes L level, the electric charge of the capacitor 1 is discharged via the second 3-state buffer 32 and the reference resistor 22, and Time tb to Vch or less
Is counted by the reference resistance side t counter 82.

The section V is the same as the section I, and the same operation is repeated.

[0025] In this case the discharge, the voltage on the resistor temperature element <br/> terminal 21 of the capacitor 1 of the capacitance Co of Figure 3 of the resistance value Rt V
1 is represented by the following equation as the supply voltage Vcc and the time t.

V1 = Vcc · exp (−t / CoRt) (9) This output is the threshold Vth of the 3-state buffer 33
If the time at which is becomes ta, the following equation is obtained.

Vth = Vcc · exp (−ta / CoRo) (10) When this is arranged, the following equation is obtained.

Ta = CoRtln (Vcc / Vth) (11) Assuming that the time of the resistor Ro with respect to the reference resistor 22 is tb, the following equation is similarly obtained.

Tb = CoRoln (Vcc / Vth) (12) When the ratio of the expressions (8) and (9) is taken, ta / tb = Rt / Ro (13), which is the same as the expression (5). The count values M1 and M2 of the counts 81 and 82 are M1 = fo · fa and M2 = fo · tb (14), and the ratio is M1 / M2 = ta / tb (15). M2 = ta / tb = Rt / Ro (16) holds, and the temperature can be measured in the same manner from the equation (16).

The above-mentioned 3-state buffer 31,
If the elements 32 and 33 are composed of C-MOS, the size can be reduced.

Although the example in which the capacitor 1 is connected to the ground is shown, the same effect can be obtained by connecting the capacitor 1 between the input terminal and the output terminal of the third 3-state buffer 33. Further, two capacitors are used, one is connected to the ground as shown in FIGS. 1 and 3, and the other is connected between the input terminal and the output terminal of the 3-state buffer 33. You may do so.

[0032]

The measurement pulse for charging or discharging the time constant circuit composed of the capacitor and the resistor and the signal for the control terminal of the buffer (gate) are shared.
The number of parts and connections are minimized and the measurement procedure is easy. At the time of non-measurement, since all buffers are enabled, their input and output levels can be fixed, and no discharging or charging means for fixing potential is required, and the input level of a buffer such as a C-MOS becomes unstable. Not to be destroyed. Since measurement is performed using pulse output, power consumption is small, errors due to self-heating of a resistance temperature element such as a thermistor are small, and high-precision measurement is possible. Since the ratio calculation is performed using the resistance temperature element and the reference resistance, the value of the pulse voltage for measurement and the capacitance of the capacitor can be ignored and are not affected by the fluctuation. Since both resistances are measured by the same method of charging or discharging, a count ratio = resistance ratio can be obtained without being affected by individual differences in the level of the threshold value, and highly accurate measurement can be performed. The circuit configuration is simple, inexpensive, and highly reliable.

[Brief description of the drawings]

FIG. 1 is a configuration explanatory view showing one embodiment of the present invention.

FIG. 2 is an operation explanatory diagram showing one embodiment of the present invention.

FIG. 3 is a configuration explanatory view showing another embodiment of the present invention.

FIG. 4 is an operation explanatory view showing another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Capacitor 21 Resistance temperature element 22 Reference resistance 31, 32, 33 3-State buffer 4 Pulse generation means 5, 51, 52 Inverter 6 Clock pulse generation means 71, 72 AND means 81, 82 Counter 9 Measurement means

Claims (1)

(57) [Claims] A pulse temperature generator having a resistance temperature element and a reference resistance connected to one end of a capacitor, first and second output terminals for generating a predetermined pulse signal for measurement,
The output terminal is connected to the capacitor via the resistance temperature element, and the input terminal is connected to the first of the measurement pulse generating means.
The output terminal is connected to the control terminal of the second pulse generating means .
A first 3-state buffer connected to the output terminal of
A second capacitor having an output terminal connected to the capacitor via the reference resistor, an input terminal connected to a second output terminal of the pulse generating means, and a control terminal connected to a first output terminal of the pulse generating means; A state buffer, and a time when the first and second 3-state buffers are turned on / off and a capacitor is charged or discharged via the resistance temperature element or the reference resistance to a predetermined voltage level. And a measuring means for calculating the temperature from the ratio.