JP2535058B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2535058B2 JP2535058B2 JP18997988A JP18997988A JP2535058B2 JP 2535058 B2 JP2535058 B2 JP 2535058B2 JP 18997988 A JP18997988 A JP 18997988A JP 18997988 A JP18997988 A JP 18997988A JP 2535058 B2 JP2535058 B2 JP 2535058B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- lead frame
- magazine
- high frequency
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の概要〕 半導体装置の製造方法、特に半導体チップを搭載した
リードフレームへの絶縁膜形成方法に関し、 チップ搭載リードフレームへの高いスループットを持
った絶縁膜形成法を提供することを目的とし、 半導体チップを搭載したリードフレームの側縁を差し
込む溝を１溝おきに接続して、隣り合うリードフレーム
間に高周波電圧を印加可能としたマガジンを用い、該マ
ガジンに前記リードフレームを複数枚差し込んで、絶縁
膜形成ガスを導入される反応炉に入れ、隣り合うリード
フレームに高周波電圧を加えてプラズマ放電を起させ、
該チップ搭載リードフレームの表面に絶縁膜を被着する
工程を有するよう構成する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an insulating film on a lead frame on which a semiconductor chip is mounted. For the purpose of providing a semiconductor device, a magazine in which side edges of a lead frame having a semiconductor chip are inserted every other groove and a high frequency voltage can be applied between adjacent lead frames is used. Insert a plurality of leadframes, put them in a reaction furnace where an insulating film forming gas is introduced, apply a high frequency voltage to adjacent leadframes to cause plasma discharge,
It is configured to have a step of depositing an insulating film on the surface of the chip mounting lead frame.
本発明は半導体装置の製造方法、特に半導体チップを
搭載したリードフレームへの絶縁膜形成方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an insulating film on a lead frame on which a semiconductor chip is mounted.
半導体装置の高集積化に伴って、素子の信頼性を向上
させるために、半導体チップをリードフレームに搭載
し、ボンディングを行なった段階で、これらの表面を絶
縁膜で覆って保護することが望まれる。本発明はこの絶
縁膜の形成方法に係るものである。As semiconductor devices become highly integrated, in order to improve the reliability of elements, it is desirable to mount a semiconductor chip on a lead frame and protect these surfaces with an insulating film at the stage of bonding. Be done. The present invention relates to the method for forming this insulating film.
半導体チップをリードフレームに搭載し、ワイヤボン
ディングした段階で表面に絶縁膜を被着、形成すること
はまだ行なわれていない。しかしこの絶縁膜形成は有効
である。即ちチップ表面にはカバー膜が形成され、防水
等の対策はとられているが、ボンディングのためパッド
部は露出しており、これにより浸水してパッドコロージ
ョンを起す恐れがある。ワイヤボンディング後、二酸化
シリコンあるいは窒化シリコン膜で覆うと、かゝる事故
は阻止し得ることが期待できる。A semiconductor chip is mounted on a lead frame, and an insulating film is not yet deposited and formed on the surface at the stage of wire bonding. However, this insulating film formation is effective. That is, although a cover film is formed on the surface of the chip and measures such as waterproofing are taken, the pad portion is exposed for bonding, which may cause water to enter and cause pad corrosion. It is expected that such an accident can be prevented by covering with a silicon dioxide or silicon nitride film after wire bonding.
チップを搭載し、ワイヤボンディングしたリードフレ
ームに絶縁膜を形成するには、かゝるリードフレームを
１枚、１枚、反応炉に並べてプラズマCVDを行なうこと
が考えられるが、これでは前後の工程に比べてスループ
ットが低くなり、量産工程のネックになる恐れがある。In order to form an insulating film on a lead frame on which chips are mounted and wire-bonded, it is conceivable that one such lead frame is placed side by side in a reaction furnace and plasma CVD is performed. The throughput is lower than that of, and there is a risk of becoming a bottleneck in the mass production process.
本発明は、チップ搭載リードフレームへの高いスルー
プットを持った絶縁膜形成法を提供することを目的とす
るものである。An object of the present invention is to provide a method for forming an insulating film having high throughput on a lead frame mounted with a chip.
第１図に示すように本発明では半導体チップ10の複数
個を搭載したリードフレーム20をマガジン30の溝に差し
込み、こうしてマガジンに複数枚のリードフレームを格
納した状態で、これらのリードフレームに高周波電源40
より電圧を印加してリードフレーム間に高周波電界が発
生し得るようにする。即ち、マガジン30の上、下面の、
リードフレーム20を差し込む溝に配線し、リードフレー
ムの左端より１番目と２番目、２番目と３番目、……に
電源40の一端と他端の電圧が加わるようにする。As shown in FIG. 1, according to the present invention, a lead frame 20 on which a plurality of semiconductor chips 10 are mounted is inserted into a groove of a magazine 30, and a plurality of lead frames are stored in the magazine in this manner. Power 40
A higher voltage is applied so that a high frequency electric field can be generated between the lead frames. That is, above and below the magazine 30,
The lead frame 20 is wired in the groove to be inserted so that the voltage at one end and the other end of the power supply 40 is applied to the first, second, second, third, ... From the left end of the lead frame.
リードフレーム20は既知のように半導体チップを取付
ける台座部と、該チップのパッド（複数）とワイヤボン
ディングされ該チップの端子ピンとなるリード（複数）
を備える。ワイヤボンディングし、モールドしたのち所
要部を切断して個々のICにする。As is well known, the lead frame 20 is a pedestal to which a semiconductor chip is attached, and leads (plural) which are wire-bonded to the pads (plural) of the chip and serve as terminal pins of the chip.
Is provided. After wire bonding and molding, required parts are cut into individual ICs.
チップ搭載リードフレームの複数枚をマガジン30に差
し込んだ状態で、二酸化シリコンまたは窒化シリコンな
ど絶縁膜を気相成長する反応炉（プラズマCVD炉）に入
れ、電源40によりリードフレーム間に高周波電圧を加
え、炉内に反応ガスを導入し、プラズマCVDを行なう。With a plurality of lead frames with chips inserted in the magazine 30, put them in a reaction furnace (plasma CVD furnace) that vapor-deposits an insulating film such as silicon dioxide or silicon nitride, and apply a high-frequency voltage between the lead frames with a power supply 40. Introduce a reaction gas into the furnace and perform plasma CVD.
また第２図に示すように第２の本発明では、マガジン
30の上，下板または左，右側板を電極とし、これらの電
極間に高周波電源40により電圧を加え、電極間に高周波
電界を発生させる。（ａ）は左，右側板を電極とする
例、（ｃ）は上，下板を側壁とする例である。個々のリ
ードフレーム20の相互間に電圧を加えることはせず、従
ってこれを差し込む溝に配線することはしない。Further, as shown in FIG. 2, in the second invention, the magazine
The upper and lower plates or the left and right plates of 30 are used as electrodes, and a high frequency power supply 40 applies a voltage between these electrodes to generate a high frequency electric field between the electrodes. (A) is an example in which the left and right plates are electrodes, and (c) is an example in which the upper and lower plates are side walls. No voltage is applied between the individual leadframes 20, and thus no wiring is provided in the groove into which they are inserted.
複数個の半導体チップ10を搭載したリードフレーム20
の複数枚をマガジン30に差し込み、該マガジンを前記反
応炉に入れ、電源40により電極（マガジンの左，右側板
または上，下板）に電圧を加えて電極間（マガジン内）
に高周波電界を発生させ、炉内に反応ガスを導入して、
プラズマCVDを行なう。Lead frame 20 with multiple semiconductor chips 10
Between the electrodes (inside the magazine) by applying a voltage to the electrodes (left, right side plate or upper, lower plate of the magazine) from the power source 40 by inserting a plurality of sheets of the above into the magazine 30.
A high-frequency electric field is generated in the
Perform plasma CVD.
本発明では第１図に示すように、半導体チップ搭載リ
ードフレームの複数枚をマガジンに差し込んで、１枚お
きに同電位として隣り合ったリードフレーム間で高周波
をかけ、マガジンを減圧下にある反応炉に入れて絶縁膜
形成ガスを導入するので、チップおよびリードフレーム
の表面にプラズマCVDにより絶縁膜が成長し、露出して
いるボンディングパッドなどを含めて全面を防水及び電
気的絶縁等することができる。According to the present invention, as shown in FIG. 1, a plurality of lead frames mounted with semiconductor chips are inserted into a magazine, a high frequency is applied between adjacent lead frames with the same potential for every other chip, and the magazine is subjected to a reaction under reduced pressure. Since the insulating film forming gas is introduced into the furnace, the insulating film grows on the surface of the chip and the lead frame by plasma CVD, and the entire surface including the exposed bonding pads can be waterproofed and electrically insulated. it can.
第２図の場合も同様で、半導体チップ搭載リードフレ
ームの複数枚をマガジンに差し込んで減圧下にある反応
炉に入れ、該炉に絶縁膜形成ガスを導入し、マガジンの
左，右側板または上，下板に高周波をかけてプラズマを
発生させるので、チップおよびリードフレームの表面に
プラズマCVDにより絶縁膜が成長し、露出しているボン
ディングパッドなどを含めて全面を防水及び電気的絶縁
等することができる。In the case of FIG. 2 as well, a plurality of lead frames mounted with semiconductor chips are inserted into a magazine and placed in a reaction furnace under reduced pressure, an insulating film forming gas is introduced into the furnace, and the left, right side or upper plate of the magazine is introduced. ， Because a plasma is generated by applying a high frequency to the lower plate, an insulating film grows on the surface of the chip and the lead frame by plasma CVD, and the entire surface including exposed bonding pads should be waterproof and electrically insulated. You can
また第１図、第２図とも、マガジンのまゝ反応炉に入
れて絶縁膜形成するので、生産性が高く、前後の工程が
スループットと比べても遜色なく、生産工程のネックと
なるようなことはない。Further, in both FIG. 1 and FIG. 2, since the insulating film is formed by putting the magazine in the reaction furnace, the productivity is high and the preceding and succeeding steps are comparable to the throughput, which is a bottleneck in the production process. There is no such thing.
第３図には第１図の発明の実施例を示す。31はマガジ
ンの上板、32は同下板で、これらの内面にはリードフレ
ーム差し込み用の溝33,34が設けられる。これらの溝は
１おきに同電位とされる。即ち１つ置きにリードフレー
ムに対する接触部が設けられ、これらの接触部は配線さ
て電源40の一端に接続可能にされる。本例では上板31の
溝33の左端から奇数番のものに接触部が形成され、これ
らが結線されて電源40の一端に接続され、下板32の溝34
は左端から偶数番のものに接触部が形成され、これらが
結線されて電源40の他端に接続される。これにより、隣
り合うリードフレーム間に高周波電界が生じ、プラズマ
が発生する。FIG. 3 shows an embodiment of the invention shown in FIG. Reference numeral 31 is an upper plate of the magazine, 32 is a lower plate thereof, and grooves 33, 34 for inserting lead frames are provided on the inner surfaces of these. Every other groove is set to the same potential. That is, every other contact portion is provided for the lead frame, and these contact portions can be connected to one end of the power source 40 by wiring. In this example, contact portions are formed in the odd numbered ones from the left end of the groove 33 of the upper plate 31, which are connected and connected to one end of the power source 40, and the groove 34 of the lower plate 32.
Has a contact portion formed from the left end to an even-numbered one, which are connected and connected to the other end of the power supply 40. As a result, a high frequency electric field is generated between the adjacent lead frames, and plasma is generated.
マガジン30の左，右側板もリードフレームと同様に導
電体として高周波電源40へ接続し、これらの側板とこれ
に対向するリードフレームとの間にも高周波電界が生
じ、プラズマが発生するようにする。これにより、どの
リードフレームもその表裏面に絶縁膜が成長する。The left and right side plates of the magazine 30 are also connected to the high frequency power source 40 as conductors similarly to the lead frames so that a high frequency electric field is generated between these side plates and the lead frame facing the side plates to generate plasma. . As a result, an insulating film grows on the front and back surfaces of any lead frame.
第４図に第２図の発明の実施例を示す。（ａ）はマガ
ジン30の左，右側板35,36を電極とした例、（ｂ）は
上，下板31,32を電極とした例である。（ａ）では上、
下板31,32は絶縁板とし、（ｂ）では上、下板31、32は
導体とするがリードフレームとの接触部は絶縁する。
（ｂ）でも図示しないが左，右側板はあり、これは絶縁
体としまた金属体として上、下板との間は絶縁する。FIG. 4 shows an embodiment of the invention shown in FIG. (A) is an example in which the left and right plates 35, 36 of the magazine 30 are electrodes, and (b) is an example in which the upper and lower plates 31, 32 are electrodes. In (a) above,
The lower plates 31 and 32 are insulating plates, and the upper and lower plates 31 and 32 are conductors in (b), but the contact parts with the lead frame are insulated.
Although not shown in FIG. 9B, there are left and right side plates, which serve as insulators and metal bodies which insulate the upper and lower plates.
反応炉は図示しないが真空チャンバで、CVDを行なう
ときは例えば1.0Torrに減圧し、SiH4，NH3などのガスを
流す。プラズマCVDは熱分解型のCVDに比べて低温で絶縁
膜を成長させることができるから、チップを接着剤で取
付けているリードフレームなどには好適である。Although not shown, the reaction furnace is a vacuum chamber. When performing CVD, the pressure is reduced to, for example, 1.0 Torr, and a gas such as SiH 4 or NH 3 is flowed. Plasma CVD can grow an insulating film at a lower temperature than pyrolysis-type CVD, and is therefore suitable for lead frames and the like to which chips are attached with an adhesive.
以上説明したように本発明によれば、半導体装置の製
造工程において量産性を阻害することなく、リードフレ
ームにチップを搭載しワイヤボンディングした後に絶縁
膜を形成することができ、半導体装置の性能向上に寄与
する所が大きい。As described above, according to the present invention, an insulating film can be formed after a chip is mounted on a lead frame and wire bonding is performed without impairing mass productivity in the manufacturing process of the semiconductor device. There is a large contribution to.
第１図および第２図は本発明の原理説明図、 第３図および第４図は本発明の実施例を示す斜視図であ
る。 第１図、第２図で10はチップ、20はリードフレーム、30
はマガジン、40は高周波電源である。1 and 2 are explanatory views of the principle of the present invention, and FIGS. 3 and 4 are perspective views showing an embodiment of the present invention. 1 and 2, 10 is a chip, 20 is a lead frame, 30
Is a magazine and 40 is a high frequency power source.
Claims (2)
側縁を差し込む溝を１溝おきに接続して、隣り合うリー
ドフレーム間に高周波電圧を印加可能としたマガジンを
用い、 該マガジンに前記リードフレームを複数枚差し込んで、
絶縁膜形成ガスを導入される反応炉に入れ、隣り合うリ
ードフレームに高周波電圧を加えてプラズマ放電を起さ
せ、該チップ搭載リードフレームの表面に絶縁膜を被着
する工程を有することを特徴とした半導体装置の製造方
法。1. A lead frame having a semiconductor chip mounted therein, wherein every other groove is inserted into a side edge of the lead frame so that a high frequency voltage can be applied between adjacent lead frames. Insert multiple sheets,
The method further comprises a step of putting an insulating film forming gas into a reaction furnace, applying a high frequency voltage to adjacent lead frames to cause plasma discharge, and depositing an insulating film on a surface of the chip mounting lead frame. Manufacturing method of semiconductor device.
複数枚、間隔を置いて収容可能なマガジンの、対向する
面を電極として高周波電圧を印加可能とし、 該マガジンに複数枚のチップ搭載リードフレームを差し
込んで、絶縁膜形成ガスを導入される反応炉に入れ、前
記電極に高周波電圧を加えてマガジン内にプラズマ放電
を起させ、該チップ搭載リードフレームの表面に絶縁膜
を被着する工程を有することを特徴とした半導体装置の
製造方法。2. A magazine capable of accommodating a plurality of lead frames each having a semiconductor chip mounted thereon with a space therebetween so that a high-frequency voltage can be applied to the magazines by using the opposite surfaces as electrodes, and a plurality of chip-mounted lead frames are accommodated in the magazine. A step of inserting the insulating film into a reaction furnace into which a gas for forming an insulating film is introduced, applying a high frequency voltage to the electrode to cause plasma discharge in the magazine, and depositing an insulating film on the surface of the chip mounting lead frame. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18997988A JP2535058B2 (en) | 1988-07-29 | 1988-07-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18997988A JP2535058B2 (en) | 1988-07-29 | 1988-07-29 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0239558A JPH0239558A (en) | 1990-02-08 |
| JP2535058B2 true JP2535058B2 (en) | 1996-09-18 |
Family
ID=16250375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18997988A Expired - Fee Related JP2535058B2 (en) | 1988-07-29 | 1988-07-29 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2535058B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0304493B1 (en) * | 1987-03-11 | 1992-09-02 | Kanegafuchi Kagaku Kogyo Kabushiki Kaisha | Hydroxystyrene derivatives |
| GB2238047B (en) * | 1989-11-03 | 1993-02-10 | Orion Yhtymae Oy | Stable polymorphic form of (e)-n,n-diethyl-2-cyano-3-(3,4-dihydroxy-5-nitrophenyl)acrylamide and the process for its preparation |
-
1988
- 1988-07-29 JP JP18997988A patent/JP2535058B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0239558A (en) | 1990-02-08 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |