JP2533162B2 - Multiprocessor system - Google Patents

Description

The present invention relates to a multiprocessor system having an interleaved memory as a shared memory, and aims to realize register access in a processor with a small amount of hardware without reducing memory access efficiency. In addition, each processor is accessible by a bus used to access the memory space of the storage device, and a register space (address space allocated to the register) is provided in each processor in the memory space of different banks in order. , Inter-processor communication is performed through the in-processor register.

[Industrial applications]

The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system having a memory capable of interleave operation as a shared memory.

[Conventional technology]

In a multiprocessor system having a memory capable of interleave operation as a shared memory, access to a register space within a processor for interprocessor communication is generally accessed through the same path as the memory space.

The memory space is divided into a plurality of banks in order to improve access efficiency and interleaved.

The register space in the processor is also as shown in FIG.
By dividing the bank into a plurality of banks like the memory space, the access efficiency can be improved.

[Problems to be Solved by the Invention]

When the register space in the processor is also divided into a plurality of banks as described above, the processor needs a control circuit such as an address latch corresponding to each bank. Moreover,
The number of accesses to the register space in the processor is much smaller than that to the memory space. For this reason, it is not preferable to increase a large amount of hardware for a space that is rarely accessed.

If the register space in the processor is not divided into a plurality of banks, the hardware does not increase as in the case of dividing into a plurality of banks, but, for example, while the processor A is accessing the register in the processor B, It is necessary to bus-lock the registers in the processor B so that they cannot be accessed. Bus locking means that other processors cannot access the memory during that time, which reduces the efficiency of memory access.

Further, in order to avoid a decrease in memory access efficiency due to the bus lock, as shown in FIG. 5, when a bus different from the memory access is provided for accessing the register in the processor, the bus control is performed. There is a problem that the amount of hardware such as circuits increases.

The problem to be solved by the present invention is to provide a multiprocessor system that solves such conventional problems.

[Means for solving the problem]

FIG. 1 shows a block diagram of the principle of the multiprocessor system of the present invention.

In the figure, MM is a storage device shared by a plurality of processors, and is capable of interleave operation.

P1, P2, P3, ... Are processors constituting a multiprocessor system.

B is a bus, which each processor uses to access the memory space of the storage device MM.

R1, R2, R3, ... Are registers in the processor, which can be accessed by the bus B used by each processor to access the memory space of the memory device (MM), and the register space can be stored in memory spaces of different banks for each processor. It is assigned.

[Action]

According to the configuration of the present invention, the in-processor registers of one processor are allocated to only one bank, as in the allocation example shown in FIG. The amount of wear is small.

In addition, since the registers in the processor are assigned to one bank, for example, the processor P1 is the processor P2.
When accessing an internal register, another processor P
Since 3, ... cannot access the same bank, they cannot access the register in the processor and need not lock the bus. It does not reduce the efficiency of storage access because the bus does not need to be locked.

Further, since the bus for accessing the storage device and the bus for communicating between the processors are shared, a bus dedicated to register access in the processor is not required.

〔Example〕

Hereinafter, the present invention will be described more specifically with reference to the embodiments shown in FIGS. 2 and 3.

 FIG. 2 is a diagram showing the configuration of an embodiment of the present invention.

FIG. 2A shows the connection configuration, and FIG. 2B shows the bank allocation of the register space in the processor.

As shown in FIG. 2, the memory space of the storage device is divided into four banks (bank 0, bank 1, bank 2, bank 3).

Processor A, Processor B, Processor C, Processor D
And the storage device are connected by an address bus and a data bus.

Registers in processor A of processor A (registers in A) are in bank 0, and registers in processor B are in bank 1
Further, the register in the processor C is allocated to the bank 2 and the register in the processor D is allocated to the bank 3.

As a result, while the processor A is accessing the register in the processor B, the processor C and the processor D cannot access the register in the processor B corresponding to the space of the bank 1. However, the processor C and the processor D can access the memory spaces corresponding to the banks 0, 2, and 3 during this period.

FIG. 3 is a diagram showing the configuration of another embodiment of the present invention.

In the embodiment of FIG. 3, as shown in FIG. 3A, the memory space of the storage device is four banks (bank 0, bank 1, bank 1).
It is divided into two banks 3), and the processors are A, B, C, D,
There are 8 units, E, F, G, H, and registers in each processor are
As shown in (b), they are assigned to banks.

That is, the processor A register and the processor E register are in bank 0, the processor B register and the processor F register are in bank 1, and the processor C register and the processor G register are in bank 2.
The register in the processor D and the register in the processor H are allocated to the bank 3.

〔The invention's effect〕

As described above, according to the present invention, it is possible to reduce the amount of hardware related to the in-processor register for interprocessor communication, and to improve the efficiency of memory access, and its practical effect is extremely large. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing a configuration of an embodiment of the present invention, FIG. 3 is a diagram showing a configuration of another embodiment of the present invention, and FIG. FIG. 5 is a diagram showing a conventional example in which a register space is divided into a plurality of banks, and FIG. 5 is a diagram showing an example in which an internal register access bus for a processor is provided. In the drawing, MM is a storage device, B is a bus, P1, P2, P3, ... Are processors, and R is a processor.
1, R2, R3, ... Represent registers in the processor, respectively.

Claims (1)

(57) [Claims] 1. A multiprocessor system comprising: a memory having a plurality of banks capable of interleave operation; and a plurality of processors connected to the memory by a bus and accessing the memory via the bus, wherein the processor is A multiprocessor system having registers allocated to one of the memory spaces of the bank.