JP2531360B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2531360B2
JP2531360B2 JP21208493A JP21208493A JP2531360B2 JP 2531360 B2 JP2531360 B2 JP 2531360B2 JP 21208493 A JP21208493 A JP 21208493A JP 21208493 A JP21208493 A JP 21208493A JP 2531360 B2 JP2531360 B2 JP 2531360B2
Authority
JP
Japan
Prior art keywords
chip
wafer
thickness
grinding
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP21208493A
Other languages
Japanese (ja)
Other versions
JPH0750280A (en
Inventor
博通 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP21208493A priority Critical patent/JP2531360B2/en
Publication of JPH0750280A publication Critical patent/JPH0750280A/en
Application granted granted Critical
Publication of JP2531360B2 publication Critical patent/JP2531360B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に、半導体基板の裏面を研削して半導体基板
の厚さを一定に加工する工程を含む半導体装置の製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a step of grinding the back surface of a semiconductor substrate to process the semiconductor substrate to a constant thickness.

【0002】[0002]

【従来の技術】半導体装置は、通常、所定の厚さの半導
体ウェハの一主面に半導体素子と配線とを形成し、その
後に素子の形成されていない裏面を研削して所望の厚さ
に調整した後、チップに切断し、ケース内に組み込んで
部品として完成させるものであり、この状態で装置に実
装される。ここで、所望の厚さとは組立上の制約から3
00〜500μm程度であり、一方、半導体ウェハの加
工工程では機械的強度の必要性や熱処理時の結晶欠陥防
止の必要性から500〜800μmの厚さを必要とす
る。したがって、始めから所望の厚さのウェハを用いる
ようにして研削を省略することはできない。
2. Description of the Related Art In a semiconductor device, a semiconductor element and wiring are usually formed on one main surface of a semiconductor wafer having a predetermined thickness, and then the back surface on which no element is formed is ground to a desired thickness. After adjustment, it is cut into chips and incorporated into a case to complete a part, which is mounted in the apparatus in this state. Here, the desired thickness is 3 due to assembly restrictions.
On the other hand, in the process of processing a semiconductor wafer, a thickness of 500 to 800 μm is required due to the necessity of mechanical strength and the prevention of crystal defects during heat treatment. Therefore, grinding cannot be omitted by using a wafer having a desired thickness from the beginning.

【0003】上記の一般的な使用方法に加えて、システ
ムの高速化・高密度化を図るため、近年では半導体チッ
プをケースを介さずに直接装置基板に実装する方法が用
いられるようになってきている。すなわち、チップ表面
に突起電極(バンプ電極)を設け、TAB(Tape Autom
ated Bonding)方式等によるリードを介して装置基板に
直接接続する方法である。通常、上記のチップは、装置
基板上に多数個実装され、チップの放熱のためのヒート
シンク等は複数のチップ裏面に共通に接触する方式が採
用される。なお、上記実装方式が採られる場合、メモリ
素子等のα線によって誤動作を起こす虞のある素子にあ
っては、チップ上にα線遮蔽用の樹脂フィルムを貼り付
けることが行われている。
In addition to the above-mentioned general use method, in recent years, in order to increase the system speed and density, a method of directly mounting a semiconductor chip on a device substrate without using a case has been used. ing. That is, a bump electrode is provided on the chip surface, and TAB (Tape Autom
This is a method of directly connecting to the device substrate via a lead of an ated bonding method or the like. Usually, a large number of the above chips are mounted on a device substrate, and a heat sink or the like for radiating the chips is commonly contacted with the back surfaces of the plurality of chips. In the case where the above-mentioned mounting method is adopted, in an element such as a memory element that may malfunction due to α-rays, a resin film for α-ray shielding is attached to the chip.

【0004】次に、上記実装方式に適合する半導体装置
の従来の製造方法について図5を参照して説明する。ま
ず、図5(a)に示すように、素子と配線が形成され表
面にバンプ2の形成されたウェハ1を用意し、このウェ
ハ1上に表面保護用樹脂フィルム11(厚さ500μm
程度)を貼付ける〔図5(b)〕。然る後、所定の間隙
xにセットした研削装置で裏面を研削する〔図5
(c)〕。その後、樹脂フィルム11を除去し、厚さy
のウェハを得る〔図5(d)〕。
Next, a conventional method of manufacturing a semiconductor device compatible with the above mounting method will be described with reference to FIG. First, as shown in FIG. 5A, a wafer 1 on which elements and wirings are formed and bumps 2 are formed on the surface is prepared, and a resin film 11 for surface protection (thickness 500 μm is formed on the wafer 1.
A) is attached [Fig. 5 (b)]. After that, the back surface is ground with a grinding device set to a predetermined gap x [Fig.
(C)]. Then, the resin film 11 is removed, and the thickness y
To obtain the wafer [FIG. 5 (d)].

【0005】次に、これをチップ3に切断し〔図5
(e)〕、α線遮蔽用のシリコン樹脂フィルム4を表面
に接着し、厚さzのチップを得る〔図5(f)〕。更
に、TABリード7のインナリードボンディングを行っ
た後、チップの電気的検査を行い、その後、アウタリー
ドボンディングを行ってチップ−配線基板間を接続す
る。最後に、チップの搭載された配線基板8をヒートシ
ンク9のあるシステム内に実装して装置を完成する〔図
5(g)〕。
Next, this is cut into chips 3 [FIG.
(E)], The α-ray shielding silicon resin film 4 is adhered to the surface to obtain a chip having a thickness z (FIG. 5 (f)). Further, after the inner lead bonding of the TAB lead 7 is performed, the chip is electrically inspected, and then the outer lead bonding is performed to connect the chip and the wiring substrate. Finally, the wiring board 8 on which the chip is mounted is mounted in a system having a heat sink 9 to complete the device [FIG. 5 (g)].

【0006】[0006]

【発明が解決しようとする課題】上記実装方法を採る場
合、同一配線基板上に複数のチップを配し、チップ裏面
を同一のヒートシンク等で一括して冷却するものである
ため、個々のチップ厚にばらつきがあると、ヒートシン
クに十分裏面が接触しないチップが発生することにな
る。このような問題を避けるにはチップ厚のばらつきを
±10μm程度以下に抑える必要があるが、従来の製法
では±40〜70μmとなるものも発生するため、一部
のチップの冷却が不十分となり、チップ温度の上昇によ
る電気的性能の低下や、極端な場合はチップの破壊を生
じるという問題があった。
When the above-mentioned mounting method is adopted, since a plurality of chips are arranged on the same wiring board and the back surfaces of the chips are collectively cooled by the same heat sink or the like, the individual chip thicknesses are reduced. If there is variation, the chips will not be fully contacted with the heat sink. In order to avoid such a problem, it is necessary to suppress the variation of the chip thickness to about ± 10 μm or less, but in the conventional manufacturing method, some of them may be ± 40 to 70 μm, so that some chips are insufficiently cooled. However, there is a problem that the electrical performance is deteriorated due to the rise of the chip temperature and the chip is broken in an extreme case.

【0007】従来の製造方法でこのような大きなばらつ
きの生じる理由は、研削装置の間隙(x)の誤差約±1
0μmに加え、以下のばらつきがチップ厚に加わるから
である。すなわち、表面保護用樹脂フィルム厚のばらつ
きが±10μm程度、α線遮蔽用のシリコン樹脂フィル
ム厚のばらつきが±20〜±50μm程度加わる。これ
らはフィルム自体の製造ばらつきと、貼り付け時の押圧
力による厚さ変動の双方の要因による。その結果トータ
ルとしてのチップ厚zは±40〜70μmという大きな
誤差を持ってしまう。
The reason why such a large variation occurs in the conventional manufacturing method is that the error in the clearance (x) of the grinding machine is about ± 1.
This is because the following variations are added to the chip thickness in addition to 0 μm. That is, the variation of the surface protection resin film thickness is about ± 10 μm, and the variation of the α-ray shielding silicon resin film thickness is about ± 20 to ± 50 μm. These are due to both manufacturing variation of the film itself and thickness variation due to the pressing force at the time of attachment. As a result, the total chip thickness z has a large error of ± 40 to 70 μm.

【0008】[0008]

【課題を解決するための手段】上記ばらつき発生原因を
解消するために、本発明によれば、素子形成済みのウェ
ハを個々のチップに分割する工程と、各チップ上に素子
面を半永久的に保護するための保護膜を電極部を避けて
形成する工程と、半導体基板の裏面を研削して基板厚さ
を所望の値に加工する工程と、を備え、裏面研削はチッ
プの素子面を上記保護膜にて被覆した状態で行うことを
特徴とする半導体装置の製造方法が提供される。
According to the present invention, in order to eliminate the above-mentioned cause of variation, a step of dividing a wafer on which elements have been formed into individual chips, and an element surface on each chip is semipermanently formed. The method includes a step of forming a protective film for protection while avoiding the electrode portion, and a step of grinding the back surface of the semiconductor substrate to process the substrate thickness to a desired value. There is provided a method for manufacturing a semiconductor device, which is performed while being covered with a protective film.

【0009】[0009]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1は、本発明の第1の実施例の製造工程
フローを示す工程断面図である。まず、半導体基板の一
主面に素子、配線およびバンプ2を形成したウェハ1を
作る〔図1(a)〕。次に、ウェハ1を半導体チップ3
に切断する〔図1(b)〕。さらにα線遮蔽用兼表面保
護用のシリコン樹脂フィルム4をチップ表面に接着する
〔図1(c)〕。次に、このチップ3の表面を真空チャ
ック5にて吸着・保持し、真空チャック5の下面との間
の間隙をzに調整された研削用ダイヤモンドホイール6
を移動させて研削を行い〔図1(d)〕、トータル厚z
のチップを得る〔図1(e)〕。然る後、TABリード
7を半導体チップ3にインナリードボンディングし、電
気的検査を行った後、、配線基板8上に搭載し、裏面を
ヒートシンク9に接触させて装置内への実装を完了する
〔図1(f)〕。本実施例によれば、トータルチップ厚
zのばらつきは研削装置の間隙にのみ依存するものにな
り、±10μm程度の高い精度の厚さに加工された半導
体チップを得ることができる。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a process cross-sectional view showing the manufacturing process flow of the first embodiment of the present invention. First, a wafer 1 is prepared in which elements, wirings and bumps 2 are formed on one main surface of a semiconductor substrate [FIG. 1 (a)]. Next, the wafer 1 is attached to the semiconductor chip 3
It is cut into pieces [Fig. 1 (b)]. Further, a silicon resin film 4 for α-ray shielding and surface protection is adhered to the chip surface [FIG. 1 (c)]. Next, the surface of the chip 3 is sucked and held by the vacuum chuck 5, and the clearance between the tip of the chip 3 and the lower surface of the vacuum chuck 5 is adjusted to z.
Is moved to perform grinding [Fig. 1 (d)], and the total thickness z
To obtain a chip [FIG. 1 (e)]. After that, the TAB lead 7 is inner lead bonded to the semiconductor chip 3, an electrical test is performed, and then the TAB lead 7 is mounted on the wiring board 8 and the back surface is brought into contact with the heat sink 9 to complete mounting in the device. [FIG. 1 (f)]. According to the present embodiment, the variation of the total chip thickness z depends only on the gap of the grinding device, and it is possible to obtain a semiconductor chip processed into a highly accurate thickness of about ± 10 μm.

【0010】図2は、本発明の第2の実施例の製造工程
フローを示す工程断面図である。本実施例において、図
2(a)〜図2(c)までの工程は先の第1の実施例の
図1(a)〜図1(c)の工程と同様であるが、図2
(d)に示す研削工程においては、第1の実施例の場合
とは異なり、研削といし10をチップ下方から上昇させ
て研削を行い、間隙が所望厚zになったところで上昇を
停止させるようにして、図2(e)に示す、トータル厚
さzのチップ3を得る。その後、第1の実施例の場合と
同様に、TAB方式により配線基板8、ヒートシンク9
のある装置内に実装する〔図2(f)〕。本実施例で
は、チップを漸進的に削っていくので、先の実施例で起
こりがちなチップ端部のカケが発生しにくいという利点
がある。
FIG. 2 is a process sectional view showing a manufacturing process flow of the second embodiment of the present invention. In this embodiment, the steps of FIGS. 2A to 2C are the same as the steps of FIGS. 1A to 1C of the first embodiment, but FIG.
In the grinding step shown in (d), unlike the case of the first embodiment, the grinding wheel 10 is lifted from below the chip to perform grinding, and the lifting is stopped when the gap reaches the desired thickness z. Then, a chip 3 having a total thickness z shown in FIG. After that, as in the case of the first embodiment, the wiring board 8 and the heat sink 9 are formed by the TAB method.
It is mounted in a certain device [FIG. 2 (f)]. In this embodiment, since the tip is gradually cut, there is an advantage that chipping of the tip end portion, which is likely to occur in the previous embodiment, is unlikely to occur.

【0011】図3は、本発明の第3の実施例の製造工程
フローを示す工程断面図である。まず、半導体基板の一
主面に素子、配線およびバンプ2が形成されたウェハ1
を用意し〔図3(a)〕、ウェハ状態のまま各チップ上
に、α線遮蔽用兼表面保護用のシリコン樹脂フィルム4
を接着する〔図3(b)〕。次に、このウェハ1の裏面
を、間隙zをもつ研削装置にて研削して、トータル厚z
のウェハを得る〔図3(c)〕。続いて、ウェハ1をダ
イシングしてトータル厚zの半導体チップ3を得る〔図
3(d)〕。さらに、第1の実施例の場合と同様に、配
線基板8、ヒートシンク9のある装置内に実装する〔図
3(e)〕。本実施例では、ウェハ状態で裏面研削を行
うため、先の実施例に比較して作業性が向上する。
FIG. 3 is a process sectional view showing a manufacturing process flow of the third embodiment of the present invention. First, a wafer 1 in which elements, wirings and bumps 2 are formed on one main surface of a semiconductor substrate
[Fig. 3 (a)], and a silicon resin film 4 for α-ray shielding and surface protection is provided on each chip in the wafer state.
Are adhered [Fig. 3 (b)]. Next, the back surface of the wafer 1 is ground by a grinding machine having a gap z to obtain a total thickness z.
To obtain the wafer [FIG. 3 (c)]. Then, the wafer 1 is diced to obtain semiconductor chips 3 having a total thickness z (FIG. 3D). Further, as in the case of the first embodiment, it is mounted in a device having the wiring board 8 and the heat sink 9 [FIG. 3 (e)]. In this embodiment, since the back surface is ground in the wafer state, workability is improved as compared with the previous embodiment.

【0012】図4は、本発明の第4の実施例の製造工程
フローを示す工程断面図である。まず、半導体基板の一
主面に素子、配線およびバンプ2が形成されたウェハ1
を用意し〔図4(a)〕、ウェハ上に感光性樹脂フィル
ム4aを接着する〔図4(b)〕。次いで、露光、現像
を行って各チップ上に、α線遮蔽用兼表面保護用となる
感光性樹脂フィルム4aを形成する〔図4(c)〕。次
に、このウェハ1の裏面を、間隙zをもつ研削装置にて
研削して、トータル厚zのウェハを得る〔図4
(d)〕。続いて、ウェハ1をダイシングしてトータル
厚zの半導体チップ3を得る〔図4(e)〕。さらに、
第1の実施例の場合と同様に、配線基板8、ヒートシン
ク9のある装置内に実装する〔図4(f)〕。本実施例
では、α線遮蔽用兼表面保護用の樹脂膜をフォトリソグ
ラフィ法により形成しているため、樹脂膜を精度高く形
成できるという利点がある。
FIG. 4 is a process sectional view showing a manufacturing process flow of the fourth embodiment of the present invention. First, a wafer 1 in which elements, wirings and bumps 2 are formed on one main surface of a semiconductor substrate
Is prepared [FIG. 4 (a)], and the photosensitive resin film 4a is adhered on the wafer [FIG. 4 (b)]. Then, exposure and development are performed to form a photosensitive resin film 4a for α-ray shielding and surface protection on each chip [FIG. 4 (c)]. Next, the back surface of the wafer 1 is ground by a grinding machine having a gap z to obtain a wafer having a total thickness z [FIG.
(D)]. Then, the wafer 1 is diced to obtain semiconductor chips 3 having a total thickness z (FIG. 4E). further,
Similar to the case of the first embodiment, it is mounted in a device having the wiring board 8 and the heat sink 9 [FIG. 4 (f)]. In this embodiment, since the resin film for α-ray shielding and surface protection is formed by the photolithography method, there is an advantage that the resin film can be formed with high accuracy.

【0013】以上好ましい実施例について説明したが、
本発明はこれら実施例に限定されるされるものではな
く、特許請求の範囲に記載された本願発明の要旨内にお
いて各種の変更が可能である。また、その実装方法もT
AB方式に限定されるものではない。
While the preferred embodiment has been described,
The present invention is not limited to these examples, and various modifications can be made within the scope of the present invention described in the claims. The mounting method is also T
The method is not limited to the AB method.

【0014】[0014]

【発明の効果】以上説明したように、本発明による半導
体装置の製造方法は、半導体チップに永久的に接着され
てα線遮蔽の用途に用いられる樹脂膜を裏面研削時の表
面保護膜としても用いるものであるので、本発明によれ
ば、裏面研削時に表面保護専用の樹脂膜を用いる場合の
ように、この表面保護膜の厚さのばらつきおよびアルフ
ァ線遮蔽用専用樹脂膜のばらつきの影響を受けることが
なくなり、高精度の厚さのチップを得ることができる。
したがって、本発明によれば、複数のチップを共通のヒ
ートシンクに接触させるときにはすべてのチップを適度
な接触圧をもってこれに接触させることができ、実装時
の冷却を均一にかつ十分に行うことができるようにな
る。また、本発明によれば、α線遮蔽膜を表面保護膜と
兼用することにより表面保護専用の樹脂膜を形成する工
程を省略することができ工程が簡素化される。
As described above, in the method of manufacturing a semiconductor device according to the present invention, the resin film permanently adhered to the semiconductor chip and used for the purpose of α-ray shielding is also used as the surface protective film during the back grinding. Therefore, according to the present invention, as in the case of using the resin film dedicated to the surface protection at the time of grinding the back surface, the influence of the variation in the thickness of the surface protection film and the variation in the alpha-ray shielding resin film is eliminated. It is possible to obtain a chip with a high precision thickness without receiving it.
Therefore, according to the present invention, when a plurality of chips are brought into contact with a common heat sink, all the chips can be brought into contact with it with an appropriate contact pressure, and cooling at the time of mounting can be performed uniformly and sufficiently. Like Further, according to the present invention, the process of forming the resin film dedicated to surface protection can be omitted by using the α-ray shielding film also as the surface protection film, and the process is simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の第1の実施例を説明するための工程
断面図。
FIG. 1 is a process sectional view for explaining a first embodiment of the present invention.

【図2】 本発明の第2の実施例を説明するための工程
断面図。
FIG. 2 is a process sectional view for explaining a second embodiment of the present invention.

【図3】 本発明の第3の実施例を説明するための工程
断面図。
FIG. 3 is a process sectional view for explaining a third embodiment of the present invention.

【図4】 本発明の第4の実施例を説明するための工程
断面図。
FIG. 4 is a process sectional view for explaining a fourth embodiment of the present invention.

【図5】 従来例を説明するための工程断面図。FIG. 5 is a process sectional view for explaining a conventional example.

【符号の説明】[Explanation of symbols]

1 ウェハ 2 バンプ 3 半導体チップ 4 シリコン樹脂フィルム 4a 感光性樹脂フィルム 5 真空チャック 6 研削用ダイヤモンドホィール 7 TABリード 8 配線基板 9 ヒートシンク 10 研削といし 11 表面保護用樹脂フィルム 1 Wafer 2 Bump 3 Semiconductor Chip 4 Silicon Resin Film 4a Photosensitive Resin Film 5 Vacuum Chuck 6 Diamond Wheel for Grinding 7 TAB Lead 8 Wiring Board 9 Heat Sink 10 Grinding Wheel 11 Surface Protective Resin Film

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 素子形成済みのウェハを個々のチップに
分割する工程と、各チップ上に素子面を半永久的に保護
する保護膜を電極部を避けて形成する工程と、半導体基
板の裏面を研削して基板厚さを所望の値に加工する工程
と、を備える半導体装置の製造方法において、裏面研削
はチップの素子面を上記保護膜にて被覆した状態で行う
ことを特徴とする半導体装置の製造方法。
1. A step of dividing a wafer on which elements have been formed into individual chips, a step of forming a protective film for semi-permanently protecting the element surface on each chip while avoiding the electrode portion, and a back surface of the semiconductor substrate. In a method of manufacturing a semiconductor device, which comprises a step of grinding to process a substrate thickness to a desired value, backside grinding is performed in a state in which an element surface of a chip is covered with the protective film. Manufacturing method.
【請求項2】 素子形成済みのウェハを個々のチップに
分割する工程と、分割された各チップ上に素子面を半永
久的に保護する保護膜を電極部を避けて貼り付ける工程
と、チップの素子面を上記保護膜にて被覆した状態でチ
ップ裏面を研削してチップの厚さを所望の値に加工する
工程と、を備える半導体装置の製造方法。
2. A step of dividing a wafer on which elements have been formed into individual chips, a step of attaching a protective film that semipermanently protects the element surface on each of the divided chips while avoiding electrode parts, and A method of manufacturing a semiconductor device, comprising the step of grinding the back surface of the chip with the element surface covered with the protective film to process the thickness of the chip to a desired value.
【請求項3】 素子形成済みのウェハの各チップ上に素
子面を半永久的に保護する保護膜を形成する工程と、チ
ップの素子面を上記保護膜にて被覆した状態で前記ウェ
ハの裏面を研削してウェハの厚さを所望の値に加工する
工程と、前記ウェハを個々のチップに分割する工程と、
を備える半導体装置の製造方法。
3. A step of forming a protective film for semipermanently protecting an element surface on each chip of a wafer on which elements have been formed, and a back surface of the wafer with the element surface of the chip covered with the protective film. Grinding and processing the thickness of the wafer to a desired value, dividing the wafer into individual chips,
A method for manufacturing a semiconductor device, comprising:
JP21208493A 1993-08-05 1993-08-05 Method for manufacturing semiconductor device Expired - Lifetime JP2531360B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21208493A JP2531360B2 (en) 1993-08-05 1993-08-05 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21208493A JP2531360B2 (en) 1993-08-05 1993-08-05 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0750280A JPH0750280A (en) 1995-02-21
JP2531360B2 true JP2531360B2 (en) 1996-09-04

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Country Link
JP (1) JP2531360B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4636096B2 (en) * 1999-03-19 2011-02-23 株式会社デンソー Semiconductor device and manufacturing method thereof

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