JP2530159B2 - Transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In the present invention, in a transistor, an insulator layer provided with a localized center of a defect or a non-conductive substance carrier introduced on the surface or inside is used as a source electrode. A gate electrode is formed near the localized center while forming a current path between the drain electrode and the drain electrode, and a tunneling current flowing between the source electrode and the drain electrode through the localized center as a relay point is applied to the gate. By making it controllable by electrodes, ultra high speed and low power consumption have been achieved.

[Industrial applications]

The present invention relates to a transistor that uses a tunneling method for traveling a carrier to achieve high speed and low power consumption.

[Conventional technology]

FIG. 6 shows a MIS (metal) which is widely used as a basic element which constitutes a memory and a logic circuit of a computer at present.
FIG. 2 is a cutaway side view of an essential part of a field effect transistor.

In the figure, 1 is a p-type semiconductor substrate, 2 is a gate insulating film, 3 is a gate electrode, 4 is a source region, and 5 is a drain region.

In this transistor, the electron flow flowing between the source and drain is controlled by the voltage applied to the gate electrode 3.

[Problems to be solved by the invention]

In order to further increase the speed of the MIS field-effect transistor shown in FIG. 6, it is roughly classified into (1) the speed of carriers traveling between the source and the drain is made as large as possible (2) the distance between the source and the drain That is, there are two methods of shortening the channel length.

Generally, in order to improve the speed of carriers, a material having large mobility is selected, and in order to shorten the channel length, fine processing or other process-related measures have been taken.

However, it is natural that there is a limit to the selection of materials with high mobility, and even when the channel length is shortened, it is considerably reduced under the gate voltage which does not reach the threshold voltage due to the so-called short channel effect. There are problems such as the current flowing through the gate oxide, the punch-through occurring, the control characteristics of the gate being lost, and the tunnel current flowing through the gate oxide film.

For this reason, there is a limit to speeding up the MIS field-effect transistor because it depends on the conventional technology. For example, the channel length is considered to be sub-micron, so that the carrier traveling The switching speed determined by the time and the parasitic capacitance inside the element is 5-6 [pico /
Second] is considered to be the limit.

Moreover, LSI (large scale integrated circuit)
In VLSI and VLSI, the delay time is further increased because the wiring capacitance or the load capacitance due to the increase in fan-out is driven. Normally, the transfer conductance is required to drive a capacitor at high speed.
Although a transistor with a large g _m is required, it is as large as 500 in the MIS field effect transistor.
Although ~ 600 [mS / mm] has been obtained, it is still better than that for high-speed operation.

The present invention provides a transistor which uses an ordinary semiconductor material, does not have the problems associated with the shortening of the channel described above, and has ultra-high speed and low power consumption.

[Means for solving problems]

FIG. 1 shows a cutaway side view of essential parts of a transistor necessary for explaining the principle of the present invention.

In the figure, 11 is an insulator layer, 11A is a localized center, 12 is a source electrode, 13 is a drain electrode, 14 is a gate insulating film, and 15 is a gate electrode.

FIG. 2 is an energy band diagram for the transistor seen in FIG. 1, where the same symbols used in FIG. 1 indicate the same parts or have the same meaning, and The figure shows the source electrode 12-insulator layer
11-Along the path of the drain electrode 13.

In the figure, E _F is the Fermi level, E _C is the bottom of the conduction band, E _V is the top of the valence band, and E is the energy level of the localized center.

In the transistor having the structure described with reference to FIG. 1 and FIG. 2, a current does not normally flow because the portion between the source electrode 12 and the drain electrode 13, that is, the portion to be the channel is made of an insulator. It should be, but since the insulator is thin, a slight tunnel current can flow, and since there is a localized center 11A in the insulator layer 11, there is a two-step tunneling in which it is in the intermediate state. (Two s
Because of the fact that a current due to tep tunneling) flows, a tunnel current sufficient to act as a transistor can be made to flow, and it can be controlled by the voltage applied to the gate electrode 15.

The control of this tunnel current will be described in more detail.

Now, assuming that the gate voltage and the drain voltage are both 0, (a) the energy level E when an electron is localized in the localized center 11A (b) one electron is localized in the localized center 11A When the electric charge induced in the gate electrode 15 is X _g e (e is the absolute value of electronic charge) (c) Similarly, the electric charge induced in the drain electrode 13 is X _g e (d) Assuming that the drain voltage is V _d (e) and the gate voltage is V _g , the energy level E for localizing the electrons
Changes to E−e (X _g V _g + X _d V _d ).

In the transistor having the structure shown, the localized center
When an electron is placed at 11A, most of the induced charge is on the gate electrode 1.
5 appears at the interface between the gate insulating film 14 and the gate electrode 15, that is, X _g >> X _d , X _g ≈1. That is, the energy level E can be made high or low by the action of the gate voltage and hardly depends on the drain voltage. As described above, the localized center 11A functions as an intermediate state when electrons move from the source electrode 12 to the drain electrode 13,
The probability that the electrons will tunnel is the insulator layer that should tunnel.
The thicker 11 reduces sharply. Therefore, the probability of electrons directly tunneling from the source electrode 12 to the drain electrode 13 is negligibly small as compared with the probability of two-step tunneling in which the localized center 11A is in the intermediate state. Therefore, by raising or lowering the energy level E at the localized center 11A, the current flowing from the source electrode 12 to the drain electrode 13 can be greatly changed.

As the localized center 11A used in the present invention, a trap formed by introducing defects or impurities into the insulator layer 11 or a three-dimensional quantum well can be used.

Therefore, in the transistor of the present invention, an insulating layer provided with a localized center (for example, localized center 11A) of a defect or non-conductive substance introduced on the surface or inside and an insulating layer Substantially insulated source electrode (eg source electrode 12) and drain electrode (eg drain electrode 13) formed opposite to each other so that the body layer serves as a current path.
And a gate electrode (for example, a gate electrode 15) formed near the localized center and substantially insulated from the insulator layer and the source and drain electrodes.

[Action]

When the above means is adopted, the current flowing between the source electrode and the drain electrode is a tunneling current, and moreover,
Since the channel length is extremely short, carriers travel at an extremely high speed, and even if the channel length is shortened, the source electrode and the drain electrode are insulated from each other, which is a problem associated with shortening the channel. Low power consumption.

〔Example〕

FIG. 3 shows a cutaway side view of essential parts of an embodiment of the present invention.

In the figure, 21 is a substrate, 22 is a buffer layer, 23 is an insulator layer, 23A is a localized center, 24 is a source electrode layer, 25 is a drain electrode layer, 26 is a source ohmic contact layer, and 27 is a drain. An ohmic contact layer, 28 is a gate insulating film, 29 is a gate electrode layer, 30 is a gate ohmic contact layer, 31 is a metal source electrode, 32 is a metal drain electrode, and 33 is a metal gate electrode.

The following is an example of the main data relating to the illustrated parts.

(A) About substrate 21 Material: Semi-insulating InP (b) About buffer layer 22 Material: In _0.52 Al _0.48 As Thickness: 200 [nm] (c) About insulator layer 23 Material: (In _0.53 Ga _0.47 As) _1-x (In _0.52 Al _0.48 As) _x x value: 0.15 Thickness: 20 [nm] (d) Localized center 23A Trap formed by implanting Ar ions into the insulator layer 23 (e) Source electrode layer About 24 Material: n-type In _0.53 Ga _0.47 As Thickness: 200 [nm] Impurity concentration: 2 × 10 ¹⁷ [cm ^-3 ] (f) About drain electrode layer 25 Material: n-type In _0.53 Ga _0.47 As Thickness: 200 nm, the impurity concentration: 2 × 10 ¹⁷ [cm ^-3] (g) for the source ohmic contact layer 26 material: n ⁺ -type InGaAs thickness: 100 nm, impurity concentration: 2 × 10 ¹⁹ [cm ^{- 3]} (h) for the drain ohmic contact layer 27 material: n ⁺ -type InGaAs thickness: 100 nm, impurity concentration: about 2 × 10 ¹⁹ [cm ^-3] (i) a gate insulating film 28 material : In _0.52 Al _0.48 As having a thickness of 50 [nm] (j) for the gate electrode layer 29 material: n-type In _0.53 Ga _0.47 As having a thickness of 100 nm, the impurity concentration: 2 × 10 ¹⁷ [cm ^-3] ( k) About the gate ohmic contact layer 30 Material: n ⁺ type In _0.53 Ga _0.47 As Thickness: 100 [nm] Impurity concentration: 2 × 10 ¹⁹ [cm ^-3 ] (l) About metal source electrode 31 Material: AuCr Thickness: 200 [nm] (m) About metal drain electrode 32 Material: AuCr Thickness: 200 [nm] (n) About metal gate electrode 33 Material: AuCr Thickness: 200 [nm] In the embodiment of semi-insulation, InP on InP substrate 21 In _0.52 Al _0.48 A
s Buffer layer 22 (In _0.53 Ga _0.47 As) _1-x (In _0.52 Al _0.48
As) _x insulator layer 23 is laminated, the tunnel barrier height can be lowered, and therefore the distance between the source electrode 24 and the drain electrode 25 can be set to about 100 nm. Enough tunnel current flows.

FIG. 4 shows a cutaway side view of the essential parts of another embodiment of the present invention.

In the figure, 41 is a substrate, 42 is a buffer layer, 43 is a source ohmic contact layer, 44 is a source electrode layer, 45 is an insulator layer, 45A is a localized center, 46 is a drain electrode layer, and 47 is a drain. Ohmic contact layer, 48 is a gate insulating film, 49 is a gate electrode layer, 50 is a gate ohmic contact layer, 51 is a metal source electrode, 52 is a metal drain electrode, and 53 is a metal gate electrode.

This embodiment is different from the embodiment shown in FIG. 3 in that (1) each layer is laminated so that an insulator layer 45 which is a barrier is sandwiched between a source electrode layer 44 and a drain electrode layer 46. (2) The thickness of the insulating layer 45 is 50 nm, which is slightly thicker than that of the insulating layer 23. (3) The x value of the insulating layer 45 is 0.50. Other than this point, the material, thickness, impurity concentration, etc. are the same as those in the embodiment shown in FIG.

Compared with the embodiment shown in FIG. 3, this embodiment has the advantage that the source-drain distance can be reduced without depending on the fine processing technique.

FIG. 5 is a fragmentary perspective view of still another embodiment of the present invention.

In the figure, 51 is a substrate, 52 is a buffer layer, 53 is an insulator layer, 53A is a first insulator layer, 53B is a second insulator layer, 54 is a source electrode layer, 55 is a drain electrode layer, Reference numerals 56 respectively indicate localized centers composed of three-dimensional quantum wells.

In this embodiment, compared with the embodiment shown in FIGS. 3 and 4, it is possible to set the energy level of the localized center with good reproducibility.

In order to form the localized center 56 in this embodiment, In _0.52
A first insulator layer 53A made of Al _0.48 As is formed, an In _0.53 Ga _0.47 As layer is formed on the first insulator layer 53A, and the In _0.53 Ga _0.47 As layer is finely processed to leave a portion to be a quantum well, A second insulator layer 53B made of In _0.52 Al _0.48 As to fill the particle well portion is formed. The source electrode layer 54 and the drain electrode layer 55 are composed of In _0.53 Ga _0.47 As.

〔The invention's effect〕

In the transistor according to the present invention, an insulator layer provided with localized centers of defects or non-conductive substances introduced on the surface or inside is provided as a current path between the source electrode and the drain electrode. In addition, a gate electrode is formed near the localized center, and a tunneling current flowing between the source electrode and the drain electrode with the localized center serving as a relay point is controlled by the gate electrode.

When the above configuration is adopted, the current flowing between the source electrode and the drain electrode is a tunneling current, and moreover,
Since the channel length is extremely short, carriers travel at an extremely high speed, and even if the channel length is shortened, the source electrode and the drain electrode are insulated from each other, which is a problem associated with shortening the channel. Low power consumption.

[Brief description of drawings]

FIG. 1 is a sectional side view of a main part of a transistor for explaining the principle of the present invention, FIG. 2 is an energy band diagram of the transistor shown in FIG. 1, and FIG. 3 is an essential part of an embodiment of the present invention. 4 is a side view of a portion cut away, FIG. 4 is a side view of a portion cut out of another embodiment of the present invention, FIG. 5 is a perspective view of a portion cut out of yet another embodiment of the present invention, and FIG. The side view of the main part of the conventional example is shown. In the figure, 11 is an insulator layer, 11A is a localized center, 12 is a source electrode, 13 is a drain electrode, 14 is a gate insulating film, and 15 is a gate electrode.

Claims (1)

(57) [Claims] 1. An insulating layer provided with a localized center of a carrier made of a defect or a non-conductive substance introduced on the surface or inside, and is formed so as to face the insulating layer so as to serve as a current path. A source electrode and a drain electrode that are substantially insulated, and a gate electrode that is formed near the localized center and that is substantially insulated from the insulator layer and the source and drain electrodes. And the transistor.