JP2529845B2 - Mullite substrate - Google Patents

Mullite substrate

Info

Publication number
JP2529845B2
JP2529845B2 JP62069554A JP6955487A JP2529845B2 JP 2529845 B2 JP2529845 B2 JP 2529845B2 JP 62069554 A JP62069554 A JP 62069554A JP 6955487 A JP6955487 A JP 6955487A JP 2529845 B2 JP2529845 B2 JP 2529845B2
Authority
JP
Japan
Prior art keywords
mullite
integrated circuit
semiconductor integrated
sio
cao
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62069554A
Other languages
Japanese (ja)
Other versions
JPS63236758A (en
Inventor
淳 田中
均 及川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP62069554A priority Critical patent/JP2529845B2/en
Priority to US07/198,111 priority patent/US4958216A/en
Publication of JPS63236758A publication Critical patent/JPS63236758A/en
Application granted granted Critical
Publication of JP2529845B2 publication Critical patent/JP2529845B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Landscapes

  • Inorganic Insulating Materials (AREA)
  • Compositions Of Oxide Ceramics (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、LSI等の半導体集積回路素子を収納する半
導体素子収納用パッケージや半導体集積回路素子が搭載
される多層配線基板等の絶縁基体に使用されるムライト
基板に関するものである。
The present invention relates to a semiconductor element housing package for housing a semiconductor integrated circuit element such as an LSI or an insulating substrate such as a multilayer wiring board on which the semiconductor integrated circuit element is mounted. The present invention relates to a mullite substrate used.

〔従来の技術〕[Conventional technology]

従来、LSI等の半導体集積回路素子を収納するパッケ
ージや半導体集積回路素子が搭載される多層配線基板等
は電気絶縁性に優れたアルミナ(Al2O3)を基体として
使用し、その表面にタングステン(W)、モリブデン
(Mo)、マンガン(Mn)等の金属から成る電気配線を施
すことによって製作されている。
Conventionally, a package that houses a semiconductor integrated circuit device such as an LSI or a multilayer wiring board on which the semiconductor integrated circuit device is mounted uses alumina (Al 2 O 3 ) having excellent electrical insulation as a base, and tungsten is used on the surface. It is manufactured by providing electrical wiring made of metal such as (W), molybdenum (Mo), manganese (Mn).

しかし乍ら、このアルミナを基体として使用したパッ
ケージ等は電気配線を伝わる信号の伝播速度が基体を構
成するアルミナの誘電率が9乃至10(室温1MNz)と高い
ことに起因して遅く、そのため近年の信号伝播速度の高
速化が進む半導体集積回路素子においては前記アルミナ
を基体として使用したパッケージや多層配線基板等には
収納、搭載することができないという欠点を有してい
た。
However, in a package or the like using this alumina as a base, the propagation speed of the signal transmitted through the electric wiring is slow due to the high dielectric constant of alumina constituting the base, which is 9 to 10 (room temperature 1 MNz). In the semiconductor integrated circuit device in which the signal propagation speed has been increased, there is a drawback that it cannot be housed or mounted in a package using alumina as a base, a multilayer wiring board, or the like.

また近年の半導体集積回路素子の高密度化、高集積化
に伴って素子自体の形状が大型化しており、該半導体集
積回路素子を前記従来のパッケージや多層配線基板等に
実装する場合、半導体集積回路素子とパッケージ等との
熱膨張係数が大きく相違することから、両者に実装の際
の熱が印加されるとパッケージ等が半導体集積回路素子
に比して大きく膨張し、その結果、半導体集積回路素子
が破損したり、パッケージや多層配線基板等より剥離す
るという問題があった。
In addition, the shape of the element itself has become larger with the recent higher density and higher integration of the semiconductor integrated circuit element. When the semiconductor integrated circuit element is mounted on the conventional package or the multilayer wiring board, the semiconductor integrated circuit element is Since the thermal expansion coefficients of the circuit element and the package etc. are largely different, the package etc. expands greatly as compared with the semiconductor integrated circuit element when heat is applied during mounting to the both, and as a result, the semiconductor integrated circuit There are problems that the element is damaged or peeled off from the package, the multilayer wiring board, or the like.

そこで、上記従来のアルミナを基体として使用したパ
ッケージ等の欠点を解消するために半導体集積回路素子
を構成するシリコンの熱膨張係数3.0〜3.5×10-6/℃
(室温〜400℃)とほぼ同等の熱膨張係数4.0〜4.5×10
-6/℃(室温〜400℃)を有し、誘電率が7.0〜7.4(室
温,1MHz)と低いムライトを半導体素子収納用パッケー
ジや多層配線基板等の基体として使用することが検討さ
ている。
Therefore, the thermal expansion coefficient of silicon constituting a semiconductor integrated circuit element is 3.0 to 3.5 × 10 −6 / ° C. in order to solve the drawbacks such as the package using the conventional alumina as a base.
Thermal expansion coefficient of 4.0-4.5 × 10, which is almost the same as (room temperature to 400 ℃)
The use of mullite, which has -6 / ℃ (room temperature to 400 ℃) and a low dielectric constant of 7.0 to 7.4 (room temperature, 1MHz), is under consideration as a substrate for semiconductor device housing packages and multilayer wiring boards.

しかしながらムライトはアルミナに比して難焼結性で
あることから、得られる焼結体は理論密度に対する相対
密度が85%程度と小さく多数の気孔を有しており、それ
故、ムライトの焼結体をパッケージや多層配線基板等の
基体として使用し、その表面に電気配線を施した場合、
該電気配線が前記気孔の存在によって断線を生じてしま
うという欠点を有していた。またムライトの焼結体は多
数の気孔を有していることから放熱性が悪く、そのため
実装される半導体集積回路素子の発する熱を大気中に良
好に放出することができず、半導体集積回路素子が素子
自身の発する熱の熱履歴等によりパッケージや多層配線
基板より剥離してしまう欠点も有していた。
However, since mullite is more difficult to sinter than alumina, the resulting sintered body has a small relative density of about 85% relative to the theoretical density and has a large number of pores. When the body is used as a substrate for a package or a multilayer wiring board, and its surface is provided with electrical wiring,
The electric wiring has a drawback that it is broken due to the existence of the pores. In addition, since the mullite sintered body has a large number of pores, the heat dissipation is poor, and therefore the heat generated by the mounted semiconductor integrated circuit device cannot be satisfactorily released to the atmosphere, and the semiconductor integrated circuit device However, there is also a defect that the element peels off from the package or the multilayer wiring board due to the thermal history of heat generated by the element itself.

〔発明の目的〕[Object of the Invention]

本発明は前記欠点に鑑み案出されたもので、その目的
は高集積化、大型化および信号伝播速度の高速化が進む
半導体集積回路素子を収納、搭載するパッケージや多層
配線基板の基体として好適に使用されるムライト基板を
提供することにある。
The present invention has been devised in view of the above-mentioned drawbacks, and its object is suitable as a base for a package or a multilayer wiring board for accommodating and mounting a semiconductor integrated circuit device, which is highly integrated, large-sized, and has a high signal propagation speed. The present invention is to provide a mullite substrate used in.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のムライト基板はムライトが70乃至95重量%、
MgOおよびCaOのうち少なくとも1種とSiO2との合計量が
5乃至30重量%から成り、第1図におていSiO2,MgOおよ
びCaOが下記A,B,Cの各点で囲まれ、かつA点を除く範囲
内であることを特徴とするものである。
The mullite substrate of the present invention contains 70 to 95% by weight of mullite,
The total amount of at least one of MgO and CaO and SiO 2 is 5 to 30% by weight, and SiO 2 , MgO and CaO are surrounded by the following points A, B and C in FIG. In addition, it is characterized in that it is within the range excluding point A.

ただし、X,Y,ZはそれぞれSiO2,MgO,CaOの重量%を表
わしX+Y+Z=100を満足する。
However, X, Y, and Z represent the weight% of SiO 2 , MgO, and CaO, respectively, and satisfy X + Y + Z = 100.

X Y Z A 100 0 0 B 60 40 0 C 60 0 40 すなわち本発明は、ムライト(3Al2O3・2SiO2〜2Al2O
3・SiO2)結晶相とSiO2,MgO,CaOからなるガラス質粒界
層によって構成され、ムライトとこれらSiO2,MgO,CaOと
の間に固相反応を生起せず、焼結体中にムライト以外の
結晶相を含有させないことによって半導体集積回路素子
を構成するシリコンとほぼ同等の熱膨張係数を有し、か
つ誘電率が低いというムライト本来の特性を損なうこと
なく、相対密度を大として気孔が少ない緻密なものと
し、半導体集積回路素子を収納、搭載するパッケージや
多層配線基板の基体として好適に使用し得るようになし
たものである。
That is, the present invention relates to mullite (3Al 2 O 3 .2SiO 2 to 2Al 2 O).
3 · SiO 2) crystalline phase and SiO 2, MgO, is constituted by a vitreous grain boundary layer of a CaO, mullite and these SiO 2, MgO, not rise to the solid phase reaction between the CaO, in the sintered body It has a coefficient of thermal expansion that is almost the same as that of silicon that constitutes semiconductor integrated circuit elements by not containing a crystalline phase other than mullite, and it does not impair the original characteristics of mullite, which has a low dielectric constant, and it has a high relative density and pores. In this case, the semiconductor integrated circuit device can be suitably used as a package for accommodating and mounting a semiconductor integrated circuit device or a base body of a multilayer wiring board.

尚、本発明においてはムライトの量が95重量%を超え
ると焼結性が低下して緻密な焼結体が得られず、また70
重量%未満では生成されるガラス量が増加して気孔が残
留し易くなり、いずれの場合も半導体素子収納用パッケ
ージや多層配線基板等の基体として使用するのが不適と
なる。
In the present invention, when the amount of mullite exceeds 95% by weight, the sinterability is lowered and a dense sintered body cannot be obtained.
If it is less than 10% by weight, the amount of glass produced increases and pores tend to remain, and in either case, it becomes unsuitable for use as a substrate for a package for housing a semiconductor element, a multilayer wiring board, or the like.

一方、ガラス質粒界層を構成するSiO2,MgO,CaOは第1
図においてA点で示すSiO2のみをムライトに添加したも
のでは、焼結体は緻密とならず多数の気孔を有したもの
となり、しかも焼結温度が極めて高いものとなってしま
う。また、SiO2の量が第1図に示すBC線、すなわち60重
量%未満となると、3Al2O3・2SiO2+CaO→Al2O3・CaO・
2SiO2+2Al2O3の如く、ムライトの一部がCaOと固相反応
してアノーサイト(Al2O3・CaO・2SiO2)とアルミナを
生じ、この結果、生成したアルミナが焼結体の熱膨張係
数を上昇させ、ムライト焼結体の熱膨張係数が半導体集
積回路素子を構成するシリコンの熱膨張係数に対し大き
く相違してしまい、いずれの場合も半導体素子収納用パ
ッケージや多層配線基板等の基体として使用するのが不
適となる。
On the other hand, SiO 2 , MgO, and CaO that make up the glassy grain boundary layer are the first
If only SiO 2 shown by point A in the figure is added to mullite, the sintered body will not be dense and will have many pores, and the sintering temperature will be extremely high. When the amount of SiO 2 is BC line shown in FIG. 1, that is, less than 60% by weight, 3Al 2 O 3 · 2SiO 2 + CaO → Al 2 O 3 · CaO.
Like 2SiO 2 + 2Al 2 O 3 , a part of mullite solid-phase reacts with CaO to produce anorthite (Al 2 O 3 · CaO · 2SiO 2 ) and alumina. As a result, the generated alumina is a sintered body. The coefficient of thermal expansion is increased, and the coefficient of thermal expansion of the mullite sintered body greatly differs from the coefficient of thermal expansion of silicon that constitutes the semiconductor integrated circuit element. In either case, a package for accommodating semiconductor elements, a multilayer wiring board, etc. Unsuitable for use as a substrate.

〔実施例〕〔Example〕

次に本発明を実施例に基づき説明する。 Next, the present invention will be described based on examples.

Al2O376重量%、SiO224重量%の組成から成るムライ
ト粉末とSiO2,MgOおよびCaOをそれぞれ第1表に示した
組成となるように秤量し、有機溶媒およびアルミナボー
ルとともに振動ミルにて粉砕混合して原料スラリーを調
整した。そして、次にこの原料スラリーを乾燥固化させ
た後、ワックス等のバインダー、分散剤および有機溶媒
を加え混合する。その後、再び乾燥して100メッシュ・
パスさせてプレス成形用原料粉末を整粒する。
Al 2 O 3 76 wt%, were weighed mullite powder and SiO 2 having the composition of SiO 2 24% by weight, MgO and CaO to respective concentrations with the composition shown in Table 1, a vibration mill together with an organic solvent and alumina balls The raw material slurry was adjusted by pulverizing and mixing. Then, after the raw material slurry is dried and solidified, a binder such as wax, a dispersant and an organic solvent are added and mixed. After that, dry again to 100 mesh
The raw material powder for press molding is sized by passing.

かくして得られた粉末を800〜1200Kg/cm2の圧力で成
形し、大気中で1400乃至1900℃の範囲内の焼成温度で2
時間焼成し、ムライト焼結体を得た。
The powder thus obtained is compacted at a pressure of 800 to 1200 Kg / cm 2 , and the powder is calcined in the atmosphere at a calcination temperature in the range of 1400 to 1900 ° C.
It was fired for a time to obtain a mullite sintered body.

次に焼成後の直径20mm、厚さ2mmの円盤状ムライト焼
結体を使用して相対密度およびX線回析法による結晶相
の同定を、同様に直径50mm、厚さ1.5mmの円盤状ムライ
ト焼結体を使用して誘電率(室温、1MHz)を、また研摩
仕上げした長さ15mm、5mm角の角柱状ムライト焼結体を
使用して熱膨張係数(室温〜400℃)をそれぞれ測定し
た。その結果を第1表に示す。
Next, using a disc-shaped mullite sintered body with a diameter of 20 mm and a thickness of 2 mm after firing, the relative density and the identification of the crystal phase by the X-ray diffraction method were performed. Similarly, a disc-shaped mullite with a diameter of 50 mm and a thickness of 1.5 mm was used. Dielectric constant (room temperature, 1MHz) was measured using a sintered body, and thermal expansion coefficient (room temperature to 400 ° C) was measured using a polished 15 mm long, 5 mm square prismatic mullite sintered body. . The results are shown in Table 1.

第1表から明らかな様に、試料番号1及び59はムライ
トの量が70重量%未満または95重量%を超える場合であ
り、いずれも相対密度が87%以下と低い。また、試料番
号20,30,58に示すように、ムライトにSiO2のみを添加し
た場合には結晶相としてムライト以外にクリストバライ
トを生じ、相対密度が83%以下と極めて低くなる。ま
た、試料番号2,3,4,21,22,23,40,41,42はSiO2,MgO及びC
aOが第1図に示すA,B,Cの各点で囲まれた範囲外の場合
で、結晶相としてムライト以外にスピネルもしくはアル
ミナとアノーサイトを生じ、熱膨張係数が4.9×10-6/℃
以上と大きくなり、いずれもムライト本来の特性を保持
していない。
As is clear from Table 1, Sample Nos. 1 and 59 are cases in which the amount of mullite is less than 70% by weight or more than 95% by weight, and the relative density is low at 87% or less. Further, as shown in sample numbers 20, 30, and 58, when only SiO 2 was added to mullite, cristobalite was generated as a crystal phase in addition to mullite, and the relative density was extremely low at 83% or less. Also, sample numbers 2 , 3 , 4 , 21, 22, 23, 40, 41, 42 are SiO 2 , MgO and C.
When aO is out of the range surrounded by the points A, B, and C shown in Fig. 1, spinel or alumina and anorthite other than mullite are generated as the crystal phase, and the thermal expansion coefficient is 4.9 × 10 -6 / ℃
The above results are large, and none of them retains the original characteristics of mullite.

それに対し、本発明のムライト基板は、相対密度が91
%以上と緻密質で、かつ熱膨張係数が4.5×10-6/℃以下
と十分低く誘電率も7.1以下と低い。なかでもSiO2,MgO
およびCaOが第1図に示すA,D,Eの各点で囲まれる範囲内
のもの(試料番号11乃至19,30乃至38,49乃至57)は熱膨
張係数が4.3×10-6/℃以下となり、更に第1図に示すA,
F,Gの各点で囲まれる範囲内のもの(試料番号16乃至19,
35乃至38,54乃至57)は熱膨張係数が4.2×10-6/℃以下
で、かつ誘電率が6.9以下となる。
In contrast, the mullite substrate of the present invention has a relative density of 91
% Or higher, and the thermal expansion coefficient is sufficiently low at 4.5 × 10 −6 / ° C. or lower, and the dielectric constant is also low at 7.1 or lower. Above all, SiO 2 , MgO
And CaO within the range surrounded by points A, D and E shown in Fig. 1 (Sample Nos. 11 to 19, 30 to 38, 49 to 57) have a thermal expansion coefficient of 4.3 × 10 -6 / ° C. Below, A shown in Fig. 1
Within the range enclosed by the F and G points (Sample Nos. 16 to 19,
35 to 38, 54 to 57) have a thermal expansion coefficient of 4.2 × 10 −6 / ° C. or less and a dielectric constant of 6.9 or less.

〔発明の効果〕〔The invention's effect〕

本発明のムライト基板は前述の実施例から明らかな如
く、緻密質でかつ半導体集積回路素子を構成するシリコ
ンとほぼ同等の熱膨張係数を有することから、該ムライ
ト基板を半導体集積回路素子を収納、搭載する半導体素
子収納用パッケージや多層配線基板等の基体として使用
した場合、表面に施される電気配線に断線を生じること
はなく、また半導体集積回路素子の破損や、剥離を生じ
ることもない。更に、誘電率が十分低いことから電気配
線に伝わる信号の伝播速度を高速化することが可能とな
り、信号伝播速度の高速化が進む近年の半導体集積回路
素子も収納、搭載することが可能となる。
Since the mullite substrate of the present invention is dense and has a thermal expansion coefficient almost equal to that of silicon constituting the semiconductor integrated circuit device, as is apparent from the above-mentioned embodiment, the mullite substrate contains the semiconductor integrated circuit device, When used as a base for a package for storing semiconductor elements to be mounted, a multilayer wiring board, etc., the electric wiring provided on the surface will not be broken, and the semiconductor integrated circuit element will not be damaged or peeled off. Furthermore, since the permittivity is sufficiently low, it is possible to increase the propagation speed of the signal transmitted to the electric wiring, and it is possible to store and mount the semiconductor integrated circuit device of recent years in which the signal propagation speed is increasing. .

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明のムライト基板におけるガラス質粒界層
を示す三元系図である。
FIG. 1 is a ternary diagram showing the vitreous grain boundary layer in the mullite substrate of the present invention.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】ムライトが70乃至95重量%、マグネシア
(MgO)およびカルシア(CaO)のうち少なくとも1種と
シリカ(SiO2)との合計量が5乃至30重量%から成り、
第1図においてSiO2,MgOおよびCaOが下記A,B,Cの各点で
囲まれ、かつA点を除く範囲内であることを特徴とする
ムライト基板。 ただし、X,Y,ZはそれぞれSiO2,MgO,CaOの重量%を表わ
しX+Y+Z=100を満足する。 X Y Z A 100 0 0 B 60 40 0 C 60 0 40
1. A mullite is 70 to 95% by weight, and the total amount of at least one of magnesia (MgO) and calcia (CaO) and silica (SiO 2 ) is 5 to 30% by weight.
In FIG. 1, a mullite substrate characterized in that SiO 2 , MgO and CaO are surrounded by points A, B and C below and are in a range excluding point A. However, X, Y, and Z represent the weight% of SiO 2 , MgO, and CaO, respectively, and satisfy X + Y + Z = 100. X Y Z A 100 0 B 60 40 0 C 60 0 40
JP62069554A 1987-03-23 1987-03-23 Mullite substrate Expired - Lifetime JP2529845B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62069554A JP2529845B2 (en) 1987-03-23 1987-03-23 Mullite substrate
US07/198,111 US4958216A (en) 1987-03-23 1988-05-24 Package for housing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62069554A JP2529845B2 (en) 1987-03-23 1987-03-23 Mullite substrate

Publications (2)

Publication Number Publication Date
JPS63236758A JPS63236758A (en) 1988-10-03
JP2529845B2 true JP2529845B2 (en) 1996-09-04

Family

ID=13406072

Family Applications (1)

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JP62069554A Expired - Lifetime JP2529845B2 (en) 1987-03-23 1987-03-23 Mullite substrate

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JPS63236758A (en) 1988-10-03

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