JP2523584B2 - Amplifier - Google Patents
AmplifierInfo
- Publication number
- JP2523584B2 JP2523584B2 JP62040860A JP4086087A JP2523584B2 JP 2523584 B2 JP2523584 B2 JP 2523584B2 JP 62040860 A JP62040860 A JP 62040860A JP 4086087 A JP4086087 A JP 4086087A JP 2523584 B2 JP2523584 B2 JP 2523584B2
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- Japan
- Prior art keywords
- voltage
- transistor
- output
- amplifying
- input
- Prior art date
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Description
【発明の詳細な説明】 産業上の利用分野 本発明は音声信号の混合、増幅などに使用する増幅装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifying device used for mixing and amplifying audio signals.
従来の技術 第３図は従来の音響用ミキサなどに使用されている、
混合回路として用いた増幅装置を示している。Prior Art FIG. 3 is used in a conventional audio mixer,
The amplification device used as a mixing circuit is shown.
第３図において、１は数千倍の増幅度を持つ演算増幅
器であり、正入力端子1aは接地され、負入力端子1bと出
力端子1cのあいだに抵抗６が接続されている。２、４は
混合回路の２つの入力端子で、抵抗３、５により負入力
端子1bに接続されている。７は混合回路の出力端子、
８、９は回路の電源である。In FIG. 3, 1 is an operational amplifier having an amplification factor of several thousand times, the positive input terminal 1a is grounded, and the resistor 6 is connected between the negative input terminal 1b and the output terminal 1c. Reference numerals 2 and 4 denote two input terminals of the mixing circuit, which are connected to the negative input terminal 1b by resistors 3 and 5. 7 is the output terminal of the mixing circuit,
Reference numerals 8 and 9 are power supplies for the circuit.
次に上記従来例の動作について説明する。第３図にお
いて、入力端子２に入力信号電圧が加わると電流が流れ
込み、負入力端子1bに電圧が発生するが、演算増幅器１
の大きな増幅度により出力端子1cには逆極性の大きな電
圧が発生し、抵抗６を通じて負入力端子1bの接続点の電
流を吸い込み、入力端子２から流れ込んだ電流と相殺し
たところで平衡状態になる。このとき負入力端子1bの電
圧は正入力端子1aは電圧とほぼ同じ接地電位となる。入
力端子４からも同時に入力信号電圧が加わった場合も入
力端子２、４から流れ込んだ電流は混合され、抵抗６を
通じて出力端子1cに流れ込む。抵抗６の両端には混合し
た電流値と抵抗値の積になる電圧が発生し、その一端が
ほぼ接地電位の負入力端子1bに接続されているため、出
力端子1cにはこの電圧が発生し出力となる。ただし極性
は逆になる。一方、入力端子２、４に流れ込む電流は抵
抗３、５の一端がほぼ接地電位の負入力端子1bに接続さ
れているため、入力信号電圧e2、e4をそれぞれ抵抗３、
５の抵抗値で除した値になる。結果として、入力信号電
圧e2、e4の和に比例した電圧の逆極性の電圧が出力端７
に得られる。この値を定量的に表現すると（１）式のよ
うになる。Next, the operation of the above conventional example will be described. In FIG. 3, when an input signal voltage is applied to the input terminal 2, a current flows and a voltage is generated at the negative input terminal 1b.
A voltage with a large reverse polarity is generated at the output terminal 1c due to the large amplification degree of, the current at the connection point of the negative input terminal 1b is absorbed through the resistor 6, and the current flowing from the input terminal 2 cancels out. At this time, the voltage of the negative input terminal 1b becomes almost the same ground potential as the voltage of the positive input terminal 1a. Even when the input signal voltage is applied from the input terminal 4 at the same time, the currents flowing from the input terminals 2 and 4 are mixed and flow into the output terminal 1c through the resistor 6. A voltage, which is the product of the mixed current value and resistance value, is generated at both ends of the resistor 6, and since one end of the resistor 6 is connected to the negative input terminal 1b at approximately ground potential, this voltage is generated at the output terminal 1c. It becomes an output. However, the polarities are reversed. On the other hand, since the currents flowing into the input terminals 2 and 4 have one ends of the resistors 3 and 5 connected to the negative input terminal 1b having substantially the ground potential, the input signal voltages e 2 and e 4 are applied to the resistors 3 and 4 , respectively.
It becomes the value divided by the resistance value of 5. As a result, the voltage of the opposite polarity of the voltage proportional to the sum of the input signal voltages e 2 and e 4 is output 7.
Is obtained. When this value is quantitatively expressed, it becomes as shown in Expression (1).
e7……出力端子７の電圧 e2……入力端子２の入力信号電圧 e4…… 〃 ４ 〃 R3…… 抵抗３の抵抗値 R5…… 抵抗５ 〃 R6…… 抵抗６ 〃 このように、上記従来の増幅装置を用いても複数の音
声信号電圧を混合することができる。 e 7 ... voltage of output terminal 7 e 2 ... input signal voltage of input terminal 2 e 4 ... 〃 4 〃 R 3 …… resistance value of resistor 3 R 5 …… resistance 5 〃 R 6 …… resistance 6 〃 As described above, it is possible to mix a plurality of audio signal voltages even by using the above conventional amplifier.
発明が解決しようとする問題点 しかしながら、上記従来の増幅装置だけを用いた混合
回路は、出力端子７の振幅が飽和する大きさになると、
負入力端子1bの接続点の流入電流すべてを抵抗６を通じ
て吸い込むことができなくなる。このとき増幅装置は増
幅度を失ない帰還ループが切断された状態になる。その
ため、ほぼ接地電位だった負入力端子1bに電圧が生じ、
入力端子２、４から流入する電流は飽和しているあいだ
減少し入力信号電圧に比例しなくなる。したがってこの
端子の等価入力抵抗は大きく変動し、入力端子２、４に
接続される信号源に逆に信号を送り出してしまい、入力
端子２、４のあいだにクロストークが発生する問題があ
った。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the mixing circuit using only the conventional amplifying device, when the amplitude of the output terminal 7 becomes saturated,
It becomes impossible to absorb all the inflow current at the connection point of the negative input terminal 1b through the resistor 6. At this time, the amplification device is in a state in which the feedback loop is disconnected without losing the amplification degree. Therefore, a voltage is generated at the negative input terminal 1b, which was almost at ground potential,
The current flowing from the input terminals 2 and 4 decreases while being saturated and is not proportional to the input signal voltage. Therefore, the equivalent input resistance of this terminal fluctuates greatly, and a signal is sent back to the signal source connected to the input terminals 2 and 4, which causes a problem that crosstalk occurs between the input terminals 2 and 4.
本発明はこのような従来の増幅装置だけを用いた負帰
還増幅器で、帰還ループが切断されたことによるこのよ
うなクロストークの問題や増幅装置が飽和から定常動作
領域に戻るときの時間遅れや、リンギングなど音質を悪
化させる問題を解決した優れた増幅装置を提供すること
を目的とするものである。The present invention is a negative feedback amplifier using only such a conventional amplifying device, and the problem of such crosstalk due to disconnection of the feedback loop, the time delay when the amplifying device returns from the saturation to the steady operation region, and the like. It is an object of the present invention to provide an excellent amplifying device which solves the problem of sound quality deterioration such as ringing.
問題点を解決するための手段 正入力を接地し、少なくとも２つ以上有する入力端子
を負入力に、出力端子を出力にそれぞれ接続された増幅
手段と、コレクタを前記増幅手段の負入力に、エミッタ
を前記増幅手段の出力にそれぞれ接続される第１トラン
ジスタ及び第２トランジスタと、前記第１トランジスタ
のベースに接続された第１電圧発生手段と、前記第２ト
ランジスタのベースに接続された第２電圧発生手段とを
備えるものであり、また別の手段として、入力端子を正
入力に、出力端子を出力にそれぞれ接続された増幅手段
と、コレクタを前記増幅手段の負入力に、エミッタを前
記増幅手段の出力にそれぞれ接続される第１トランジス
タ及び第２トランジスタと、前記第１トランジスタのベ
ースに接続された第１電圧発生手段と、前記第２トラン
ジスタのベースに接続された第２電圧発生手段とを備
え、前記接続された第２電圧発生手段とを備えるもので
あり、それぞれの手段に対して、前記第１電圧発生手段
の電圧は前記増幅手段の高電圧側の飽和出力電圧より少
なめの電圧で初めて第１トラジスタが導通するように設
定され、前記第２電圧発生手段の電圧は前記増幅手段の
低電圧側の飽和出力電圧より大きめの電圧で初めて前記
第２トランジスタが導通するように設定されるものであ
る。Means for Solving the Problems Amplification means connected to a negative input with an input terminal having at least two or more positive inputs grounded, and an output terminal connected to an output, a collector to a negative input of the amplification means, and an emitter. A first transistor and a second transistor respectively connected to the output of the amplifying means, a first voltage generating means connected to the base of the first transistor, and a second voltage connected to the base of the second transistor. As another means, an amplifying means having an input terminal connected to a positive input and an output terminal connected to an output, a collector to a negative input of the amplifying means, and an emitter to the amplifying means. A first transistor and a second transistor respectively connected to the output of the first transistor, a first voltage generation means connected to the base of the first transistor, and the first transistor. A second voltage generating means connected to the bases of the two transistors, and a second voltage generating means connected to the base of each of the two transistors. The first transistor is set to conduct only at a voltage lower than the saturation output voltage on the high voltage side of the amplifying means, and the voltage of the second voltage generating means is set to be higher than the saturation output voltage on the low voltage side of the amplifying means. It is set so that the second transistor becomes conductive only when the voltage is applied.
作用 本発明は上記のような構成により、増幅手段の出力信
号が、飽和する直前の大きさになると、トランジスタの
ベース・エミッタ間電圧を順方向にするように、トラン
ジスタのベースに印加されたバイアス電圧を設定すこと
で、トランジスタのコレクタ・エミッタ間を導通させ、
トランジスタのエミッタからコレクタに電流を流し、増
幅手段の出力端の飽和と帰還ループの切断を防ぐことが
できる。Action The present invention has the above-mentioned configuration, and when the output signal of the amplifying means has a magnitude just before saturation, a bias applied to the base of the transistor so as to make the base-emitter voltage of the transistor forward. By setting the voltage, conduct between the collector and emitter of the transistor,
A current can be passed from the emitter to the collector of the transistor to prevent saturation of the output end of the amplification means and disconnection of the feedback loop.
実施例 第１図は本発明の一実施例の構成を示すものである。
第１図において１〜９は第３図と同様であり、11、12は
トランジスタ、13、14はそれぞれ抵抗13a、13b、14a、1
4bから成る第１、２電圧発生手段である。Embodiment FIG. 1 shows the structure of an embodiment of the present invention.
In FIG. 1, 1 to 9 are the same as those in FIG. 3, 11 and 12 are transistors, and 13 and 14 are resistors 13a, 13b, 14a and 1 respectively.
4b is a first and second voltage generating means.
次に上記実施例の動作について説明する。上記実施例
において、出力端子1cの正電圧の飽和電圧より少し低い
電圧で、トランジスタ11のコレクタ電流が負入力端子1b
に流れるように電圧発生手段13の電圧を抵抗13a、13bで
設定する。また出力端子1cの負電圧の飽和電圧より少し
高い電圧で、トランジスタ12のコレクタ電流が負入力端
子1bに流れるよう電圧発生手段14の電圧を抵抗14a、14b
で設定する。入力端子２、４に出力端子1cの出力電圧e7
が飽和点より十分低い値にさせる入力信号電圧e2、e4を
加えたときはトランジスタ11、12のベース・エミッタ間
はそれぞれ逆バイアスされ、コレクタ電流は流れず、従
来例の動作と全く同一である。次に入力信号電圧２、４
は大きくしてゆくと、出力電圧７が正のときトランジス
タ１のベース・エミッタ間は順バイアスされてコレクタ
電流が出力端子1cから負入力端子1bに流れ出力電圧e7を
出力端子1cの飽和電圧以内にとどめたままで、入力端子
２、４から流入した電流と相殺させ平衡状態になる。出
力電圧e7が負のときはトランジスタ12と電圧発生手段13
により同様の状態になる。以上の動作により負入力端子
1bの電位は大きな入力信号電圧であっても変動すること
はなくほぼ接地電位を確保される。Next, the operation of the above embodiment will be described. In the above embodiment, when the collector current of the transistor 11 is slightly lower than the positive saturation voltage of the output terminal 1c, the negative input terminal 1b
The voltage of the voltage generating means 13 is set by the resistors 13a and 13b so that the voltage will flow to. Further, the voltage of the voltage generating means 14 is set slightly higher than the saturation voltage of the negative voltage of the output terminal 1c so that the collector current of the transistor 12 flows to the negative input terminal 1b.
Set with. Output voltage e 7 of output terminal 1c to input terminals 2 and 4
When the input signal voltages e 2 and e 4 are set to a value sufficiently lower than the saturation point, the bases and emitters of the transistors 11 and 12 are reverse-biased, respectively, and the collector current does not flow. Is. Next, input signal voltage 2, 4
When the output voltage 7 is positive, the base-emitter of the transistor 1 is forward biased and the collector current flows from the output terminal 1c to the negative input terminal 1b when the output voltage 7 is positive, and the output voltage e 7 is the saturation voltage of the output terminal 1c. The current flowing from the input terminals 2 and 4 is canceled by keeping the current within the range, and a balanced state is achieved. When the output voltage e 7 is negative, the transistor 12 and the voltage generating means 13
Will result in a similar situation. Negative input terminal
The potential of 1b does not fluctuate even with a large input signal voltage, and the ground potential is almost secured.
このように、上記実施例によれば、大きな入力信号電
圧が加えられたとき、トランジスタ11、12が、演算増幅
器１の飽和直前に導通状態になり、増幅装置の増幅度を
低下させ、演算増幅器１の飽和を避け、その結果、負帰
還ループを切断せずに安定した動作を行なわせる利点を
有する。したがって、このような増幅装置を用いた混合
回路においては、入力端子間のクロストークの問題を改
善することができる。As described above, according to the above-described embodiment, when a large input signal voltage is applied, the transistors 11 and 12 become conductive immediately before the saturation of the operational amplifier 1 to reduce the amplification degree of the amplification device, and The saturation of 1 is avoided, and as a result, stable operation can be performed without disconnecting the negative feedback loop. Therefore, in a mixing circuit using such an amplifying device, the problem of crosstalk between input terminals can be improved.
また上記実施例によれば、増幅度の非常に大きな増幅
手段を飽和させずに利用できるため、入力信号電圧に良
く追従する効果を有する。Further, according to the above-described embodiment, the amplifying means having a very large amplification degree can be used without being saturated, so that it has an effect of following the input signal voltage well.
第２図は他の実施例を示すものであり、増幅装置を用
いて電圧増幅回路を構成している。22は入力端子、23は
抵抗６とともに利得を決定する抵抗である。FIG. 2 shows another embodiment in which a voltage amplifying circuit is constructed by using an amplifying device. Reference numeral 22 is an input terminal, and 23 is a resistor that determines the gain together with the resistor 6.
入力端子22の入力信号電圧22が大きく、出力電圧e7が
飽和に近づくと、トラジスタ11、または12が導通し、増
幅度を決めている帰還量を増加させ、増幅度を下げて演
算増幅器１の飽和を避けることができる。しかしこの実
施例では増幅度は１以下には下がらない回路構成のた
め、入力信号電圧は出力電圧e7の最大値を越えて加える
と、効果はない。音響用ミキサの入力増幅器などの入力
信号電圧が低く、増幅度の大きい用途や、入力信号電圧
の最大値が出力電圧のそれを越えないよう工夫したスピ
ーカ駆動用電力増幅器などの用途で、大入力で出力電圧
を飽和させても速やかに回復する効果を有する。When the input signal voltage 22 at the input terminal 22 is large and the output voltage e 7 approaches saturation, the transistor 11 or 12 becomes conductive, increasing the feedback amount that determines the amplification degree, and decreasing the amplification degree to reduce the operational amplifier 1 Can avoid saturation. However, since the circuit configuration amplification degree which does not decrease below 1 in this embodiment, when the input signal voltage is added beyond the maximum value of the output voltage e 7, no effect. Large input for applications with low input signal voltage and large amplification such as input amplifier of audio mixer, and speaker drive power amplifier designed to prevent the maximum input signal voltage from exceeding that of output voltage. Thus, even if the output voltage is saturated, it has an effect of recovering quickly.
発明の効果 本発明は上記実施例より明らかなように （１）増幅手段の出力信号の大きさを、設定されたしき
い値と比較し、その大きさに応じてトランジスタのコレ
クタ・エミッタ間を導通させ、出力端から負の入力端に
電流を流す。そのため、増幅装置に入力にしきい値を越
えるような過大な信号が印加されても、増幅手段の出力
にはしきい値を越える電圧が現れず、総体としての増幅
装置の出力が飽和を回避するという効果を有する。EFFECTS OF THE INVENTION The present invention is clear from the above-mentioned embodiment. (1) The magnitude of the output signal of the amplifying means is compared with a set threshold value, and the collector-emitter of the transistor is connected according to the magnitude. It conducts, and a current flows from the output end to the negative input end. Therefore, even if an excessive signal that exceeds the threshold is applied to the input of the amplifier, a voltage exceeding the threshold does not appear in the output of the amplifier, and the output of the amplifier as a whole avoids saturation. Has the effect.
（２）正入力を接地し、少なくとも２つ以上有する入力
端子を負入力に、出力端子を出力にそれぞれ接続された
増幅手段による構成によれば、混合した出力端の飽和と
帰還ループの切断がないので、仮想接地状態を維持で
き、クロストークの増加や、飽和から定常状態への回復
遅れ、リンギングなど、音質劣化が起こらないという効
果を有する。(2) According to the configuration of the amplifying means in which the positive input is grounded, the input terminal having at least two or more is connected to the negative input, and the output terminal is connected to the output, saturation of the mixed output end and disconnection of the feedback loop are caused. Since it does not exist, the virtual ground state can be maintained, and there is an effect that sound quality deterioration such as increase in crosstalk, delay in recovery from saturation to steady state, ringing, etc. does not occur.
（３）入力端子を正入力に、出力端子を出力にそれぞれ
接続された増幅手段による構成によれば、入力端子が大
きくなっても、出力端の飽和と帰還ループの切断がない
ので、飽和から定常状態への回復遅れ、リンギングな
ど、音声劣化が起こらないという効果を有する。(3) According to the configuration of the amplifying means in which the input terminal is connected to the positive input and the output terminal is connected to the output, the saturation of the output terminal and the disconnection of the feedback loop are not caused even if the input terminal becomes large. It has an effect that voice deterioration such as delay in recovery to a steady state and ringing does not occur.
第１図は本発明の一実施例における増幅装置を混合回路
として構成した回路図、第２図は他の実施例における増
幅装置を電圧増幅回路として構成した回路図、第３図は
従来の増幅装置を混合回路として構成した回路図であ
る。 １……演算増幅器、２、４、22……入力端子、３、５、
６、23……抵抗、７……出力端子、８、９……電源、1
1、12……トランジスタ、13、14……電圧発生手段。FIG. 1 is a circuit diagram in which an amplifier device according to an embodiment of the present invention is configured as a mixing circuit, FIG. 2 is a circuit diagram in which the amplifier device according to another embodiment is configured as a voltage amplifier circuit, and FIG. 3 is a conventional amplifier. It is a circuit diagram which constituted the device as a mixing circuit. 1 ... Operational amplifier, 2, 4, 22 ... Input terminals 3, 5,
6, 23 ... Resistance, 7 ... Output terminal, 8, 9 ... Power supply, 1
1, 12 …… Transistor, 13, 14 …… Voltage generator.
Claims (2)
る入力端子を負入力に、出力端子を出力にそれぞれ接続
された増幅手段と、コレクタを前記増幅手段の負入力
に、エミッタを前記増幅手段の出力にそれぞれ接続され
る第１トランジスタ及び第２トランジスタと、前記第１
トランジスタのベースに接続された第１電圧発生手段
と、前記第２トランジスタのベースに接続された第２電
圧発生手段とを備え、前記第１電圧発生手段の電圧は前
記増幅手段の高電圧側の飽和出力電圧より少なめの電圧
で初めて第１トランジスタが導通するように設定され、
前記第２電圧発生手段の電圧は前記増幅手段の低電圧側
の飽和出力電圧より大きめの電圧で初めて前記第２トラ
ンジスタが導通するように設定されたことを特徴とする
増幅装置。1. An amplifying means in which a positive input is grounded, an input terminal having at least two or more is connected to a negative input, an output terminal is connected to an output, a collector is a negative input of the amplifying means, and an emitter is the amplifying unit. A first transistor and a second transistor respectively connected to the output of the means;
It comprises a first voltage generating means connected to the base of the transistor and a second voltage generating means connected to the base of the second transistor, the voltage of the first voltage generating means being on the high voltage side of the amplifying means. The first transistor is set to conduct only at a voltage lower than the saturated output voltage,
The amplifying device, wherein the voltage of the second voltage generating means is set so that the second transistor becomes conductive only when the voltage is larger than the saturation output voltage on the low voltage side of the amplifying means.
れぞれ接続された増幅手段と、コレクタを前記増幅手段
の負入力に、エミッタを前記増幅手段の出力にそれぞれ
接続される第１トランジスタ及び第２トランジスタと、
前記第１トランジスタのベースに接続された第１電圧発
生手段と、前記第２トラジスタのベースに接続された第
２電圧発生手段とを備え、前記接続された第２電圧発生
手段とを備え、前記第１電圧発生手段の電圧は前記増幅
手段の高電圧側の飽和出力電圧より少なめの電圧で初め
て第１トランジスタが導通するように設定され、前記第
２電圧発生手段の電圧は前記増幅手段の低電圧側の飽和
出力電圧より大きめの電圧で初めて前記第２トランジス
タが導通するように設定されたことを特徴とする増幅装
置。2. A first transistor having an input terminal connected to a positive input and an output terminal connected to an output, a collector connected to a negative input of the amplification means, and an emitter connected to an output of the amplification means. And a second transistor,
A first voltage generating unit connected to the base of the first transistor; a second voltage generating unit connected to the base of the second transistor; and a second voltage generating unit connected to the first transistor. The voltage of the first voltage generating means is set so that the first transistor conducts only when the voltage is less than the saturation output voltage of the high voltage side of the amplifying means, and the voltage of the second voltage generating means is set to the low voltage of the amplifying means. An amplifying device characterized in that the second transistor is set to be conductive only at a voltage larger than a saturated output voltage on the voltage side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62040860A JP2523584B2 (en) | 1987-02-24 | 1987-02-24 | Amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62040860A JP2523584B2 (en) | 1987-02-24 | 1987-02-24 | Amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63208312A JPS63208312A (en) | 1988-08-29 |
| JP2523584B2 true JP2523584B2 (en) | 1996-08-14 |
Family
ID=12592296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62040860A Expired - Lifetime JP2523584B2 (en) | 1987-02-24 | 1987-02-24 | Amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2523584B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4539395B2 (en) * | 2005-03-25 | 2010-09-08 | ヤマハ株式会社 | Power Amplifier |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5526910U (en) * | 1978-07-28 | 1980-02-21 | ||
| JPS567509A (en) * | 1979-06-29 | 1981-01-26 | Tektronix Inc | Nonnlinear amplifying circuit |
-
1987
- 1987-02-24 JP JP62040860A patent/JP2523584B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63208312A (en) | 1988-08-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |