JP2522458B2 - Method of generating land pattern data for wire bonding - Google Patents
Method of generating land pattern data for wire bondingInfo
- Publication number
- JP2522458B2 JP2522458B2 JP26437790A JP26437790A JP2522458B2 JP 2522458 B2 JP2522458 B2 JP 2522458B2 JP 26437790 A JP26437790 A JP 26437790A JP 26437790 A JP26437790 A JP 26437790A JP 2522458 B2 JP2522458 B2 JP 2522458B2
- Authority
- JP
- Japan
- Prior art keywords
- land pattern
- wire bonding
- pattern data
- chip
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
- H01L2224/49173—Radial fan-out arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はワイヤーボンディング用ランドパターンデー
タの生成方法に関し、特に基板に搭載された多ピンのIC
チップをワイヤーボンディング法により接続するための
混成集積回路装置のCADシステム又は作図用ソフトを用
いたパターンレイアウト方法に関する。The present invention relates to a method for generating land pattern data for wire bonding, and more particularly to a multi-pin IC mounted on a board.
The present invention relates to a pattern layout method using a CAD system of a hybrid integrated circuit device or drawing software for connecting chips by a wire bonding method.
従来、この種のパターンレイアウト方法としては、ピ
ン数の比較的少ないICチップについては、ワイヤーボン
ディング用ランドパターンを、このランドパターンの長
手方向がICチップ外形の各辺にそれぞれ直角をなす向き
に固定して自動生成を行なっていたが、多ピンICチップ
の場合には、組立て上の歩留りを考慮しながらマニュア
ル入力にて作成する方法によっていた。Conventionally, as a pattern layout method of this type, for an IC chip having a relatively small number of pins, a wire bonding land pattern is fixed in a direction in which the longitudinal direction of the land pattern is perpendicular to each side of the IC chip outline. However, in the case of a multi-pin IC chip, it was created by manual input while taking the yield in assembly into consideration.
前者の場合、第５図のレイアウト図に示すように、例
えばICチップのボンディングパッドデータ52をICチップ
外形データ51の４辺のうちどの辺に近いかによって４グ
ループに振り分け、更に、各グループ毎のピン数に相当
する数のワイヤーボンディング用ランドパターンデータ
53をICチップ外形データ51から一定の距離の直線上に一
定のピッチで、且つ中央振分けにより配置する。その
際、この一定距離及びピッチは設計基準により定められ
る条件から割り出される値を使用し、配置角度は各辺に
直角を成す向きに固定している。In the former case, as shown in the layout diagram of FIG. 5, for example, the bonding pad data 52 of the IC chip is divided into four groups according to which side of the four sides of the IC chip outer shape data 51 is closer, and further, each group is further divided. The number of land pattern data for wire bonding corresponding to the number of pins
53 are arranged on a straight line at a constant distance from the IC chip outer shape data 51 at a constant pitch and by central distribution. At this time, the constant distance and the pitch are values determined from the conditions defined by the design standard, and the arrangement angle is fixed in a direction forming a right angle to each side.
後者の場合、特に外形に比較してピン数が多いICチッ
プの場合には、同じく第５図に当てはめてみるとワイヤ
ーボンディング用ランドパターンデータ53の間隔が密と
なり、コーナー部分の有効な利用が必至となる。しかし
ながら、前者の場合のように配置角度を固定していたの
では、ワイヤーデータ54の向きとの食い違いが顕著とな
り、１本のワイヤーが複数のワイヤーボンディング用ラ
ンドパターンデータ53にまたがって交差するケースが増
え、最悪の場合ショート不良の多発につながる。それに
対処するために、ワイヤーボンディング用ランドパター
ンデータ53の配置角度を全体に渡って僅かずつスムーズ
に変化させていく方法をとらざるを得ず、上記作業をマ
ニュアル入力により処理していた。In the latter case, especially in the case of an IC chip having a larger number of pins compared to the outer shape, the same applies to FIG. 5, the spacing of the wire bonding land pattern data 53 becomes close, and the effective use of the corner portion is achieved. It will be inevitable. However, if the arrangement angle is fixed as in the former case, the discrepancy with the direction of the wire data 54 becomes noticeable, and one wire crosses over a plurality of wire bonding land pattern data 53. Increase, and in the worst case, short defects will frequently occur. In order to deal with this, there is no choice but to take a method of gradually changing the arrangement angle of the wire bonding land pattern data 53 little by little over the whole, and the above-mentioned work is processed by manual input.
従って、多ピンのICチップの場合には、結局マニュア
ル入力にて作成することになるが、その場合、データの
作成そのものに多くの時間と工数を要し、特に、ICチッ
プが100ピンを越えるような場合、データ作成に要する
時間は１時間から２時間を要していた。Therefore, in the case of a multi-pin IC chip, it will be created by manual input in the end, but in that case, it takes a lot of time and man-hours to create the data, and especially the IC chip exceeds 100 pins. In such a case, the time required to create the data was 1 to 2 hours.
また、上記ランドパターンの位置及び向きについて
は、それらを幾何学的に一意的に決定できるような明確
な基準がなく、あいまいなガイドラインに基づいてパタ
ーンレイアウトが行われていたため、作業者によるパタ
ーン品質のばらつきが回避できないという欠点があっ
た。In addition, regarding the position and orientation of the land patterns, there is no clear standard that can uniquely determine them geometrically, and the pattern layout was performed based on ambiguous guidelines. However, there is a drawback in that the variation in the above cannot be avoided.
上述した従来のワイヤーボンディング用ランドパター
ンデータの生成方法では、このランドパターンデータの
向きが90度単位に固定もしくは不定であるのに対して、
本発明ではこの向きがICチップの４辺の各々に対応して
幾何学的に決定される四つの基準点の方向を向くように
標準化するという相違点を有する。In the conventional method of generating land pattern data for wire bonding described above, the direction of this land pattern data is fixed or unfixed in 90 degree units,
The present invention has the difference that this direction is standardized so as to face the directions of four reference points geometrically determined corresponding to each of the four sides of the IC chip.
本発明は、ICチップの４辺の各々を底辺とし、且つこ
の底辺に対置する頂点がICチップの中心に向かう四つの
直角二等辺三角形を想定し、各々の底辺に沿って並ぶ各
ボンディング用パッドに対する基板側のランドパターン
データの長手方向の向きを前記直角二等辺三角形の底辺
に対置する頂点に向くように自動生成することでワイヤ
ーボンディング用ランドパターンデータの生成向きを決
定する方法である。The present invention assumes four right-sided isosceles triangles whose bases are four sides of the IC chip and whose vertices opposed to the bottom face toward the center of the IC chip, and the bonding pads arranged along the respective bases. Is a method of determining the generation direction of the land pattern data for wire bonding by automatically generating the direction of the land pattern data on the substrate side in the longitudinal direction so as to face the apex opposite to the base of the isosceles right triangle.
また、ワイヤーボンディング用ランドパターンデータ
の配置位置も、仮想ワイヤー長を一定、又は各直角二等
辺三角形毎にその底辺に対置する角90度をランドパター
ン数で等分する等の条件によりアルゴリズム化し、自動
的に生成可能としている。Also, the placement position of the land pattern data for wire bonding, the virtual wire length is constant, or for each right-angled isosceles triangle, the angle 90 degrees opposite to the base is algorithmized by the condition such that the angle 90 degrees is equally divided by the number of land patterns, It can be generated automatically.
第１図は本発明の第１実施例のレイアウト図である。
本実施例では、ICチップ外形データ11の周辺部のボンデ
ィングパッドデータ12からワイヤーデータ14を介してワ
イヤーボンディング用ランドパターンデータ13が滑らか
な曲線に沿ってレイアウトされている。第２図は、第１
図のパターンの幾何学的な位置関係を解説するための図
である。更に、処理アルゴリズムを示すフローチャート
を第４図に示した。FIG. 1 is a layout diagram of the first embodiment of the present invention.
In the present embodiment, the wire bonding land pattern data 13 is laid out along the smooth curve from the bonding pad data 12 in the peripheral portion of the IC chip outer shape data 11 through the wire data 14. FIG. 2 shows the first
It is a figure for demonstrating the geometrical positional relationship of the pattern of the figure. Further, a flowchart showing the processing algorithm is shown in FIG.
まず第２図において、ICチップの外形データ21がABCD
に対応している。各辺AB,BC,CD,DAを底辺とする直角二
等辺三角形は、各々ASB,BTC,CUD、DVAに相当する。これ
らの４頂点はICチップの中心Ｏとは明らかに異なり、IC
チップの外形データ21の縦横比が１からずれる程Ｏ点か
ら遠ざかる。又、各直角二等辺三角形の頂点S,T,U,Vが
前記の四つの基準点となっている。First, in FIG. 2, the outline data 21 of the IC chip is ABCD.
It corresponds to. The isosceles right triangles whose bases are the sides AB, BC, CD, DA correspond to ASB, BTC, CUD, DVA, respectively. These four vertices are clearly different from the center O of the IC chip,
As the aspect ratio of the chip outline data 21 deviates from 1, the distance from the point O increases. Further, the vertices S, T, U and V of each right-angled isosceles triangle are the above-mentioned four reference points.
従って、例えばＰ点にワイヤーボンディング用ランド
パターンデータ23があったとすると、その向きはPVの方
向に一意的に決定される。その場合、四つの基準点のう
ちどれを選ぶかは、ワイヤーボンディング用ランドパタ
ーンデータ23がワイヤーで結ばれるところのボンディン
グパッドデータ22が、どの直角二等辺三角形に含まれる
かによる。このグループ分けの作業が第４図の処理１に
相当する。Therefore, for example, if there is the wire bonding land pattern data 23 at the point P, the direction is uniquely determined in the PV direction. In that case, which of the four reference points is selected depends on which right-angled isosceles triangle includes the bonding pad data 22 where the wire bonding land pattern data 23 is connected by a wire. This grouping work corresponds to process 1 in FIG.
次に、各グループ毎に、頂点S,T,U,Vの内角90度を、
それに含まれるボンディングパッドデータ数で等分する
角度をＤ（Ｇ）と置く。この作業が処理２に相当する。Next, for each group, the interior angles of the vertices S, T, U, V are 90 degrees,
An angle equally divided by the number of bonding pad data included therein is set as D (G). This work corresponds to process 2.
次に、各グループ内の全パッドに対し、このパッドが
左回りに数えて何番目かをグループ内リファレンス番号
としてＲ（Ｎ）とおく。この作業が処理３に相当する。Next, with respect to all the pads in each group, R (N) is set as the in-group reference number, which is the number of this pad counted counterclockwise. This work corresponds to process 3.
また、ワイヤーボンディング用ランドパターンデータ
23の配置座標Ｐの決め方には任意性が残るが、本実施例
では、PVとADとの交点Ｋで決まる距離PKを仮想ワイヤー
長Ｗとし、この仮想ワイヤー長ＷがPVの向きＱによらず
一定という条件を与えている。その結果、ＰはＱの変化
に応じて点線で示す軌跡25を描く。Also, land pattern data for wire bonding
Although the method of determining the arrangement coordinate P of 23 remains arbitrary, in the present embodiment, the distance PK determined by the intersection point K of PV and AD is set as the virtual wire length W, and this virtual wire length W depends on the direction Q of the PV. The condition that it is constant is given. As a result, P draws a locus 25 indicated by a dotted line according to the change of Q.
最終的には、処理４によりピン番号Ｎに対応するワイ
ヤーボンディング用ランドパターンデータ23の配置角度
Ｑ（Ｎ）と配置座標Ｘ（Ｎ）,Y（Ｎ）をピン総数NMAXに
対応する全てのボンディングパッドについて計算した
後、処理５においてワイヤーボンディング用ランドパタ
ーンの発生を行なう。Finally, in process 4, the arrangement angle Q (N) and the arrangement coordinates X (N), Y (N) of the wire bonding land pattern data 23 corresponding to the pin number N are all bonded corresponding to the total number NMAX of pins. After the calculation for the pad, in step 5, a land pattern for wire bonding is generated.
また、第２図から明らかなように、直角二等辺三角形
はICチップ外形データ21のコーナー部分に各々二等分線
を引いて得られる唯一の二等辺三角形であり、ICチップ
外形データ21の縦横比の値によらず、グループの境界部
に不用な隙間や重なりが生ずることがない。そのため、
グループの境界部を挟んで隣り合うワイヤーボンディン
グ用ランドパターンデータ23同士がほぼ平行になり、コ
ーナー部分にスムーズ且つ偏りのない配置角度の連続的
変化を実現できる。従って、本発明において正三角形や
その他の二等辺三角形ではなく直角二等辺三角形を使用
する理由はここにあるといえる。As is clear from FIG. 2, the isosceles right triangle is the only isosceles triangle obtained by drawing bisectors at the corners of the IC chip outline data 21. Irrespective of the value of the ratio, unnecessary gaps and overlaps do not occur at the boundaries of the groups. for that reason,
The land pattern data 23 for wire bonding that are adjacent to each other across the boundary of the group are substantially parallel to each other, and it is possible to realize a continuous change in the arrangement angle that is smooth and has no deviation in the corner portion. Therefore, this is the reason why the right isosceles triangle is used in the present invention rather than the equilateral triangle and other isosceles triangles.
第３図は本発明の第２実施例のレイアウト図である。
第１実施例に対し、本実施例では第２図で示した仮想ワ
イヤー長PKの値を、ワイヤーボンディング用ランドパタ
ーンデータ33の集密度に応じて変化させている。即ち、
仮想ワイヤー長Ｗを固定せず、グループ内パッド数Ｐ
（Ｇ）と底辺長との比によって上記集密度を判定し、こ
の集密度に比例するような長さを新たにＷ（Ｇ）として
以降の計算を行なう。FIG. 3 is a layout diagram of the second embodiment of the present invention.
In contrast to the first embodiment, in this embodiment, the value of the virtual wire length PK shown in FIG. 2 is changed according to the density of the wire bonding land pattern data 33. That is,
The virtual wire length W is not fixed and the number of pads in the group is P
The above confluency is determined by the ratio of (G) to the base length, and the following calculation is performed by newly setting W (G) as a length proportional to this confluence.
例えば、Ｈ（Ｇ）＝Ｐ（Ｇ）／底辺長の適正値をH0と
した時、Ｗ（Ｇ）＝（Ｈ（Ｇ）/H0）×Ｗとする。但
し、ワイヤー長には上限下限があるため、この範囲を越
える場合は値を上限値または下限値に設定する必要があ
る。この操作により、ワイヤーボンディング用ランドパ
ターンデータ33の間隔のグループ間でのばらつきを抑制
できる効果がある。なお、Ｗについて以上のような制御
を施す以外は、処理アルゴリズムは第４図と全く同様で
ある。For example, when H0 is an appropriate value of H (G) = P (G) / base length, W (G) = (H (G) / H0) × W. However, since the wire length has an upper limit and a lower limit, if it exceeds this range, it is necessary to set the value to the upper limit or the lower limit. This operation has the effect of suppressing variations in the spacing of the wire bonding land pattern data 33 between groups. The processing algorithm is exactly the same as that shown in FIG. 4 except that the above W is controlled.
以上説明した本発明のワイヤーボンディング用ランド
パターンデータの生成方法は、最終的なレイアウトが全
て域何学的に決定されるため、自動生成が可能で処理時
間も数秒から数十秒と従来のマニュアル入力に比べ1/10
0以下に短縮できる効果がある。また、作業者によるパ
ターン品質のばらつきや接続ミス等も当然皆無にでき
る。In the method for generating land pattern data for wire bonding of the present invention described above, since the final layout is all geometrically determined, automatic generation is possible and the processing time is from several seconds to several tens of seconds, which is a conventional manual method. 1/10 compared to input
There is an effect that it can be shortened to 0 or less. In addition, it is possible to eliminate variations in pattern quality and connection errors due to the operator.
特に本発明は、原理的に100ピンを越えるような多ピ
ンのICチップに対しても、生産性の高い高品質なパター
ンを自動的に生産できるため、多品種且つ多ピンのICチ
ップを使用する製品設計においては、欠くことのできな
い処理方法になる。In particular, since the present invention can automatically produce a high-quality pattern with high productivity even for a multi-pin IC chip having more than 100 pins in principle, a multi-product and multi-pin IC chip is used. It is an indispensable processing method in product design.
第１図は本発明の第１実施例のレイアウト図、第２図は
第１図のパターンデータの位置関係を説明する図、第３
図は本発明の第２実施例のレイアウト図、第４図は本発
明の第１実施例の動作アルゴリズムのフローチャート、
第５図は従来例のレイアウト図である。 11,21,31,51……ICチップ外形データ、12,22,32,52……
ボンディングパッドデータ、13,23,33,53……ワイヤー
ボンディング用ランドパターンデータ、ABCD……ICチッ
プ外形、Ｏ……ICチップ中心、S,T,U,V……ICチップの
各辺AB,BC,CD,DAを底辺とする各直角二等辺三角形の頂
点、Ｐ……ワイヤボンディング用ランドパターンデータ
の中心、Ｋ……線分PVと辺ADとの交点、PK,W……仮想ワ
イヤー長、Ｇ……グループ番号、Ｐ（Ｇ）……グループ
内パッド数、Ｄ（Ｇ）……グループ内の直角二等辺三角
形の底辺に対置する頂点の内角をグループ内のパッド数
で等分した分割角度、Ｎ……ピン番号、Ｒ（Ｎ）……ピ
ン番号Ｎのパッドがこのピンの属するグループ内で左回
りに数えて何番目かを示すリファレンス番号、Ｑ（Ｎ）
……ピン番号Ｎに対応するワイヤーボンディング用ラン
ドパターンデータの配置角度、Ｘ（Ｎ）,Y（Ｎ）……ピ
ン番号Ｎに対応するワイヤーボンディング用ランドパタ
ーンデータの配置座標、NMAX……ピン総数。FIG. 1 is a layout diagram of the first embodiment of the present invention, FIG. 2 is a diagram for explaining the positional relationship of the pattern data of FIG. 1, and FIG.
FIG. 4 is a layout diagram of the second embodiment of the present invention, FIG. 4 is a flow chart of an operation algorithm of the first embodiment of the present invention,
FIG. 5 is a layout diagram of a conventional example. 11,21,31,51 …… IC chip outline data, 12,22,32,52 ……
Bonding pad data, 13,23,33,53 ... Wire bonding land pattern data, ABCD ... IC chip outline, O ... IC chip center, S, T, U, V ... IC chip sides AB, The vertex of each right-angled isosceles triangle with BC, CD, DA as the base, P ... Center of the wire bonding land pattern data, K ... Intersection point of line PV and side AD, PK, W ... Virtual wire length , G …… Group number, P (G) …… Number of pads in the group, D (G) …… Division by dividing the interior angle of the vertex opposite to the base of the isosceles right triangle in the group by the number of pads in the group Angle, N ... pin number, R (N) ... reference number indicating the number of the pad with pin number N, counting counterclockwise in the group to which this pin belongs, Q (N)
... Arrangement angle of wire bonding land pattern data corresponding to pin number N, X (N), Y (N) ... Arrangement coordinates of wire bonding land pattern data corresponding to pin number N, NMAX ... total number of pins .
Claims (2)
ディング法にて接続するための表面導体ランドパターン
のレイアウト設計を行なうワイヤーボンディング用ラン
ドパターンデータの生成方法において、前記ICチップの
４辺の各々を底辺とし、且つこの底辺に対置する頂点が
ICチップの中心に向かう四つの直角二等辺三角形を想定
し、各々の底辺に沿って並ぶ各ボンディング用パッドに
対する基板側のランドパターンデータの長手方向の向き
が、前記直角二等辺三角形の底辺に対置する頂点に向く
ように自動生成することを特徴とするワイヤーボンディ
ング用ランドパターンデータの生成方法。1. A wire bonding land pattern data generating method for designing a layout of a surface conductor land pattern for connecting an IC chip mounted on a substrate by a wire bonding method, wherein each of four sides of the IC chip is formed. Is the base, and the vertex opposite to this base is
Assuming four right-angled isosceles triangles toward the center of the IC chip, the longitudinal direction of the land pattern data on the substrate side with respect to each bonding pad arranged along the bottom of each is opposite to the bottom of the right-angled isosceles triangle. A method for generating land pattern data for wire bonding, which is characterized in that it is automatically generated so as to face the apex.
ータの配置位置が、仮想ワイヤー長を一定にするか、又
は各直角二等辺三角形毎にその底辺に対置する角90度を
ランドパターン数で等分することによって決定される請
求項１記載のワイヤーボンディング用ランドパターンデ
ータの生成方法。2. The arrangement position of the land pattern data for wire bonding is such that the virtual wire length is constant or the angle 90 degrees opposite to the base is equally divided by the number of land patterns for each right-angled isosceles triangle. The method for generating land pattern data for wire bonding according to claim 1, which is determined by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26437790A JP2522458B2 (en) | 1990-10-01 | 1990-10-01 | Method of generating land pattern data for wire bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26437790A JP2522458B2 (en) | 1990-10-01 | 1990-10-01 | Method of generating land pattern data for wire bonding |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04139840A JPH04139840A (en) | 1992-05-13 |
| JP2522458B2 true JP2522458B2 (en) | 1996-08-07 |
Family
ID=17402310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26437790A Expired - Fee Related JP2522458B2 (en) | 1990-10-01 | 1990-10-01 | Method of generating land pattern data for wire bonding |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2522458B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112486892A (en) * | 2020-12-15 | 2021-03-12 | 泰和电路科技（惠州）有限公司 | Computing method of binding IC (integrated circuit) control calculator |
-
1990
- 1990-10-01 JP JP26437790A patent/JP2522458B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04139840A (en) | 1992-05-13 |
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