JP2519534B2 - Interfering wave remover - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, description will be made in the following order.

A Industrial field of use B Outline of the invention C Conventional technology D Problems to be solved by the invention E Means for solving the problem F Action G Example G ₁ Configuration of the first example (Fig. 1) G ₂ Operation of the first embodiment (Figs. 1 and 3) G ₃ Configuration of the second embodiment (Fig. 2) G ₄ Operation of the second embodiment (Figs. 2 and 3) H EFFECTS OF THE INVENTION A Industrial field of application The present invention is used in SSR (Secondary Surveillance Radar) and the like, and uses an interfering wave component signal sensed from a sub-lobe region of a main antenna, using an interfering wave signal sensed from an auxiliary antenna. The present invention relates to an interfering wave removing device that suppresses or effectively reduces (hereinafter, referred to as necessary).

B Outline of the invention In an interference wave elimination device for suppressing an interference wave component signal which is sensed from a sublobe area of a radiation characteristic of a main antenna by using an interference wave signal which is sensed from an auxiliary antenna corresponding to the sublobe area, Creates a modulated signal by integrating the amplified signal with the offset voltage compensated by the closed or open loop from the baseband signal that mixes the main channel signal supplied from the main antenna and the auxiliary channel signal supplied from the auxiliary antenna. To do. Then, the derived modulation signal and the I and Q signals generated from the auxiliary channel signal are subjected to quadrature two-phase modulation and combined, and the signal derived here is used to remove the interfering wave component signal from the main channel signal. As a result, the closed-loop follow-up control for obtaining the zero level of the signal to be integrated is optimized so as to prevent the deterioration of the interference wave removal efficiency related to the ambient temperature change, the fluctuation of the power supply voltage or the characteristic error between the operating elements, etc. It is the one.

C Conventional technology This type of interference wave elimination device (ECCM = ELectronic Counter
Counter Measure) is a sidelobe canceller (SLC)
Is called.

 Here, an example of the interference wave removing device is shown in FIG.

In the figure, the main channel signal S ₂ is a signal including an interfering wave signal that is sensed from a sub-lobe region such as an INT beam antenna and converted to an intermediate frequency by a receiver (not shown) such as SSR. Further, the auxiliary channel signal S ₃ is a predetermined frequency at the dedicated receiver, which is the interference wave signal sensed from the auxiliary antenna that can cope with reception of the sub-lobe area of the INT beam antenna or the like.
For example, a signal converted to an intermediate frequency. The interference wave removing apparatus shown in this example is supplied with the subtractor _{2 to} which the main channel signal S ₂ is supplied, and the signal derived from the subtractor 2 and the auxiliary channel signal S ₃ to derive respective divided signals. Power dividers 4, 6 and 8 and limiting amplifier
10 and the auxiliary channel signal S ₃ are separately supplied, and I and Q signals having equal amplitude and 90 ° phase difference are derived.
It has 90 ° hybrid circuits 12 and 22. The I and Q signals derived here and the signals derived from the power divider 6 are input to the mixers 14a and 14b, and the baseband signals are input.
_S10a and _S10b are generated. The baseband signal S _10a ,
S _10b is generated into modulated signals S _12a and S _12b via DC amplifiers 16a and 16b and integrators 18a and 18b, and then to modulators 20a and 20b together with I and Q signals derived from 90 ° hybrid circuit 22. It is input and subjected to quadrature two-phase modulation. Each of the signals derived here is input to the power combiner 24 and power-combined, and then supplied to the other input terminal of the subtractor 2, where the main channel signal S ₂ corresponds to the auxiliary channel signal S ₃ . That is, the interference wave component signal is reduced, and the interference wave removal signal S ₁₆ is derived from the power divider 4.

In this way, closed-loop follow-up control is performed so that the levels of the signals input to the integrators 18a and 18b become zero, and thereby the interference wave component signal is suppressed.

D. Problem to be Solved by the Invention However, in the above-described conventional interference wave removing device, the DC amplifiers 16a and 16b are not provided with offset voltage compensating means. Of the modulation signal S _12a ,
S _12b does not correspond to the levels of the baseband signals S _10a and S _10b . That is, there is a drawback that the closed loop follow-up control performed to make the levels of the signals input to the integrators 18a and 18b zero is not optimized and the interference wave removal efficiency is not improved.

The present invention has been made in view of the above point, and the closed loop follow-up control for obtaining the zero level of a signal to be integrated is optimized, and is related to a change in ambient temperature, a change in power supply voltage, a characteristic error between operating elements, and the like. An object of the present invention is to provide an interference wave removing device that effectively prevents deterioration of the interference wave removing efficiency.

E Means for Solving the Problem In order to solve the above-mentioned problems, the interference wave removing device of the present invention comprises: a subtracter for subtracting an interference wave component signal from a main channel signal obtained from a main antenna to derive the signal. First dividing means for dividing the signal derived from the subtractor into first and second signals, and outputting the first signal to the output terminal as an interference wave elimination signal; and an auxiliary channel signal obtained from the auxiliary antenna. Is divided into a third signal and a fourth signal, and the third signal outputted from the second dividing means is divided by 90 °.
Mixing means for deriving a quadrature two-phase baseband signal by mixing two phases of phase difference and mixing with a second signal output from the first dividing means, and quadrature output from the mixing means Switching means for deriving a two-phase baseband signal and a ground potential by switching at a predetermined time interval, and first and second offset voltages for compensating the offset voltage contained in each of the signals output from the switching means. Compensating means, first and second integrators for integrating the signals sent from the first and second offset voltage compensating means, respectively, and a fourth signal output from the second dividing means by 90 °
Modulating means for shifting to two phases of phase difference and modulating with signals output from the first and second integrators, and then synthesizing them and supplying them as an interfering wave component signal to the subtractor; It is characterized by

F action In the interference wave canceling apparatus of the present invention configured as described above, the divided main channel signal and the I and Q signals generated from the auxiliary channel signal are mixed to generate a baseband signal respectively. It Next, a modulation signal is created by integrating the amplified signal with the offset voltage compensated by the closed or open loop from each baseband signal. Furthermore, the I and Q signals created from the auxiliary channel signal by the modulation signal are subjected to quadrature two-phase modulation and combined, and the signal derived here is used to subtract and remove the interference wave component signal from the main channel signal. Excuse me.

In this way, the closed-loop follow-up control that makes the signal level supplied to be integrated zero is optimized, and thereby the interference wave component signal is effectively suppressed.

G Example Next, an example of an interference wave removing device according to the present invention will be described in detail below with reference to the accompanying drawings. In the text and the accompanying drawings, common components are denoted by common reference numerals, and duplicated description thereof will be omitted.

FIG. 1 shows the configuration of the first embodiment using a closed loop offset voltage compensation amplification section, and FIG. 2 shows the second embodiment using an open loop offset voltage compensation amplification section. Further, FIG. 3 shows the waveform and timing of the drive signal.

G ₁ Structure of the First Embodiment (FIG. 1) In this embodiment, first, the INT which is the main antenna
The receiver signal (not shown) such as SSR is the received signal including the interfering wave component signal that is detected from the side lobe area of the beam antenna for
An input terminal T ₁ is provided to which the main channel signal S ₂₀ converted to an intermediate frequency signal or the like after being supplied to the main channel signal S ₂₀ is supplied.
Further, the interfering wave signal sensed by the auxiliary antenna capable of coping with reception of the sub-lobe area of the INT beam antenna or the like is supplied to the dedicated receiver, where the auxiliary signal converted to a predetermined frequency, for example, an intermediate frequency signal is supplied. It has an input terminal T ₂ to which the channel signal S ₂₁ is inputted.

Next, a subtracter 32 connected to the input terminal T ₁ and one input terminal, a power divider 34 for deriving the signal supplied from the subtractor 32 to one and the other output terminals, and the other output terminal A power divider 36 to which the derived signal is input. Note that one output end of the power divider 34 is connected to an output terminal T _{3 from} which an interfering wave elimination signal S ₃₀ described later is derived.

On the other hand, the power divider 38 connected to the input terminal T ₂
And a limiting amplifier 40 connected to one output terminal and the other output terminal from which the divided signal is derived, respectively, and the supplied signal are generated as I and Q signals having an equal amplitude and a 90 ° phase difference. And a 90 ° hybrid circuit 42 to be derived.

Further, the 90 ° hybrid circuit 44 to which the output end of the limiting amplifier 40 is connected, and the I and Q signals having the equal amplitude and the 90 ° phase difference, which are led out to the one and the other output ends, are supplied. It has mixers 46a and 46b. Further, one and the other output ends of the power divider 36 are connected to the mixers 46a and 46b, respectively. The output terminals of the mixers 46a and 46b are connected to the closed loop offset voltage compensation amplification units CLA ₁ and CLA ₂ , respectively.

Here, the closed-loop offset voltage compensation amplifier CLA ₁ , CL
Explain A ₂ .

The closed loop offset voltage compensation amplification units CLA ₁ and CLA ₂ have switching circuits 48 and 49, and the mixers 46a and 4 are provided at the respective contacts 48a and 49a of the switching circuits 48 and 49.
The output terminals of 6b are connected to each other. Note that the contacts that face each other
48e and 49e are grounded. A two-terminal input DC differential amplifier whose movable contacts 48c and 49c are connected to one input end
50a, 51a (hereinafter also simply referred to as DC amplifiers 50a, 51a)
And amplifiers 50b and 51b connected to the output terminals of the DC amplifiers 50a and 51a. Further, it is provided with sample hold circuits 50c and 51c connected to the output ends of the amplifiers 50b and 51b, and integrators 50d and 51d connected to the output ends of the sample hold circuits 50c and 51c. The output terminals of the integrators 50d and 51d are connected to the other input terminals of the DC amplifiers 50a and 51a to form so-called closed loop offset voltage compensation means.

Next, the integrators 56a and 56b to which the signals derived from the DC amplifiers 50a and 51a are supplied, and the modulation signal generated here
S _24a , S _24b and modulators 58a, 58b derived from the 90 ° hybrid circuit 42 to which the I and Q signals are input, respectively. Further, the power combiner for inputting the respective signals derived from the modulators 58a and 58b and for power combining
64, and the signal derived from the power combiner 64 is supplied to the other input terminal of the subtractor 32, where the main channel signal S ₂₀ corresponds to the auxiliary channel signal S ₂₁ .
That is, the interference wave component signal is reduced, and the interference wave removal signal S ₃₀ is derived from the power divider 34.

G ₂ Operation of First Embodiment (FIGS. 1 and 3) In the first embodiment configured as described above, first, the main channel signal S ₂₀ is subtracted from the subtracter 32 via the input terminal T _1. Is supplied to one of the input terminals. Then, the signal derived from the output terminal of the subtractor 32 is input to the power divider 34. One of the signals divided here is supplied to the power divider 36. At the other output terminal, an interfering wave elimination signal S ₃₀ described later is led out to the output terminal T ₃ . Further equally divided signals are output to one output terminal and the other output terminal, respectively.

On the other hand, the auxiliary channel signal S ₂₁ supplied via the input terminal T ₂ is input to the power divider 38, and the equally divided signals are led to one and the other output ends, respectively. Then, the signal derived at one output terminal is supplied to the limiting amplifier 40, amplified to a constant power, and then supplied to the 90 ° hybrid circuit 44. 90 ° phase difference here,
It is divided into equal amplitude I and Q signals. The I signal and the Q signal are supplied to mixers 46a and 46b, respectively. Further, the mixers 46a and 46b are supplied with the signals derived at one and the other output ends of the power divider 36, and are subjected to multiplication processing. It As a result, two baseband signals S _22a and S _{22b of} I and Q signals are generated and supplied to the closed loop offset voltage compensation amplification units CLA ₁ and CLA ₂ . In the closed-loop offset voltage compensation amplification units CLA ₁ and CLA ₂ , first, the baseband signals S _22a and S _22b are applied to the contacts 48a and 49a of the switching circuits 48 and 49. After that, the movable contacts 48c, 49c
Is supplied to one of the input ends of the DC amplifiers 50a and 51a via. Here the movable contact 48c, the 49c driving signal C _c to perform the switching timing shown in FIG. 3 is supplied.
Then, the output signals of the DC amplifiers 50a and 51a are respectively fed to the amplifier 50.
It is supplied to b and 51b and amplified. Then, the output signals are respectively supplied to the sample hold circuits 50c and 51c, the signals held here are supplied to the integrators 50d and 51d, respectively, and the signals derived by integration here are the other of the DC amplifiers 50a and 51a. Is input to the input terminal of. After the closed loop offset voltage compensation is performed in this way, the signals derived from the DC amplifiers 50a and 51a, respectively, are supplied to the integrators 56a and 56b.

Here, the closed loop offset voltage compensation will be described. First, at the timing of regular intervals Suichinngu circuit 48 and 49 do not require the removal of the interference wave represented by the FIG. 3, i.e., the movable contact 48c with the driving signal C _c, contact the 49c 48
e, 49e is switched, that is, grounded, and the value of the signal at one input end of the DC amplifiers 50a, 51a, that is, the baseband signals _S22a , _S22b is set to zero (V). Here, the offset voltages of the DC amplifiers 50a and 51a are held by the sample hold circuits 50c and 51c. The signal held here is integrated by integrators 50d and 51d, and the voltage formed here is fed back to the DC amplifiers 50a and 51a. In this case, if the response time of the closed loop offset voltage compensation is set to a value sufficiently larger than the offset voltage sampling period, the DC amplifiers 50a and 51a operate so that the offset voltage is always zero (V), and the offset voltage compensation is performed. Done.

On the other hand, the removal of the interfering wave component signal is performed by setting the switching circuits 48 and 49 shown in FIG. 3 to the movable contacts 48c and 49c.
It is performed between the timings of switching to 9a, but in the same manner as described above, offset voltage compensation is performed even in a state where an offset voltage is generated in the DC amplifiers 50a and 51a.
No offset voltage is generated at the outputs of 50a and 51a. In this way, the output signals of the DC amplifiers 50a, 51a, which have been offset voltage compensated and derived, are supplied to the integrators 56a, 56b,
Here, the modulated signals S _24a and S _{24b that} have been integrated are respectively modulators.
It is supplied to 58a and 58b. Furthermore, 90 ° hybrid circuit
The I and Q signals derived from 42 are supplied to modulators 58a and 58b, modulated by the modulation signals S _24a and S _24b , respectively supplied to a power combiner 64, and power is combined,
It is supplied to the other input terminal of the subtractor 32. The combined modulation signal is input to the other input terminal of the subtractor 32 and corresponds to the main channel signal S ₂₀ to the auxiliary channel signal S ₂₁ , that is, the interference wave component signal is reduced, and then the power divider 34 Is input to the output terminal T ₃ as the interfering wave elimination signal S ₃₀ from the other output end.

G ₃ Configuration of Second Embodiment (FIG. 2) The second embodiment is different from the closed loop offset voltage compensating amplifiers CLA ₁ and CLA ₂ employed in the first embodiment described above in comparison with the open loop offset voltage. Compensation amplifiers OLA ₁ and OLA ₂ and 2-terminal input differential integrators 57a and 57b (hereinafter, simply integrators).
57a and 57b) are used, and other configurations are the same. Therefore, here, the configuration of the open loop offset voltage compensation amplifiers OLA ₁ and OLA ₂ and the integrators 57a and 57b will be described.
Others are omitted.

The open-loop offset voltage compensation amplifiers OLA ₁ and OLA ₂ are DC amplifiers 52a and 53a to which the baseband signals S _22a and S _22b are supplied via the switching circuits 48 and 49, and the DC amplifiers.
Output terminals and input terminals of 52a and 53a are connected to each other and have sample and hold circuits 52b and 53b.
The output terminals of 52a, 53a and the sample hold circuits 52b, 53b are connected to the input terminals of integrators 56a, 56b, respectively.

G ₄ Operation of the Second Embodiment (FIGS. 2 and 3) The operation of the second embodiment is performed with respect to the closed loop offset voltage compensation amplifiers CLA ₁ and CLA ₂ adopted in the first embodiment. The operations of the open-loop offset voltage compensation amplifiers OLA ₁ and OLA ₂ and the two-terminal input integrators 57a and 57b are different, and the other operations are the same. Therefore, here, the open loop offset voltage compensation amplifiers OLA ₁ , OLA ₂ and the integrator 57 are used.
The operations of a and 57b will be described, and the others will be omitted.

In this case, the timing of regular intervals that do not require removal of the interfering wave shown a Suichinngu circuit 48 and 49 in the FIG. 3, i.e., the movable contact 48c with the driving signal C _c, the 49c contacts 48
e, 49e is switched, that is, grounding is performed, and the offset voltage of the DC amplifiers 52a, 53a and the DC amplifiers 52a, 53a is supplied, where the DC subtraction is performed and the offset voltage is held by the sample hold circuits 52b, 53b. To be done.
Next, the integrators 57a and 57b are connected to the sample hold circuit.
The offset currents of 52b and 53b and the DC amplifiers 52a and 53a are supplied, and the voltage of the offset is compensated by the direct subtraction.

The closed loop offset voltage compensation amplifiers CLA ₁ and CLA ₂ of the first embodiment are provided with switching circuits 48 and 49 and an amplifier 50.
b, 51b, sample hold circuits 50c, 51c, integrators 50d, 5
1d, switching circuits 48 and 49, sample and hold circuits 52b and 53b are used for the open loop offset voltage compensation amplifiers OLA ₁ and OLA ₂ of the second embodiment, and an integrator 57 is further used.
Although a and 57b are used, the invention is not limited to this. Of course, other closed and open loop offset voltage compensating and amplifying means that operate similarly can be utilized.

Further, in the first and second embodiments, the closed loop offset voltage compensation amplification units CLA ₁ and CLA ₂ and the open loop offset voltage compensation amplification units OLA ₁ and OLA ₂ are arranged in a mixed manner to obtain a similar operating state. This is also included in the present invention.

H Effect of the Invention As described above, according to the interference wave cancel device of the present invention, the main channel signal supplied from the main antenna and the auxiliary channel signal supplied from the auxiliary antenna are mixed to close or close the baseband signal. The amplified signal that has been subjected to offset voltage compensation by the open loop is integrated to create a modulated signal, and the modulated signal and the I and Q signals generated from the auxiliary channel signal are subjected to quadrature two-phase modulation and combined, The signal derived here is used to remove the interfering wave component signal from the main channel signal, thereby optimizing the closed-loop tracking control for obtaining the zero level of the signal to be integrated, thereby changing the ambient temperature and the power supply. This has the effect of reducing deterioration of the interference wave removal efficiency due to voltage fluctuations or characteristic errors between operating elements, and enabling effective removal of interference wave component signals. That.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment in which a closed loop offset voltage compensating / amplifying unit is adopted in an interference wave removing device according to the present invention, and FIG. 2 is an interference wave removing device according to the present invention, FIG. 4 is a block diagram showing a configuration of a second embodiment in which an open loop offset voltage compensating / amplifying unit is adopted. FIG. 3 is a waveform diagram of a drive signal used for explaining operations of the first and second embodiments. FIG. 1 is a block diagram showing a configuration of an interference wave removing device in which a closed loop interference wave removing control circuit according to a conventional technique is formed. 32 …… Subtractor 34, 36, 38 …… Power divider 40 …… Limiting amplifier 42, 44 …… 90 ° Hybrid circuit 46a, 46b …… Mixer 48, 49 …… Switching circuit 50a, 51a …… DC amplifier 50b , 51b ...... Amplifiers 50c, 51c ...... Sample hold circuits 50d, 51d ...... Integrators 52a, 53a ...... DC amplifiers 52b, 53b ...... Sample hold circuits 56a, 56b ...... Integrators 57a, 57b ...... 2-terminal input Integrator 58a, 58b …… Modulator, 64 …… Power combiner S ₂₀ …… Main channel signal S ₂₁ …… Auxiliary channel signal S _24a , S _24b …… Modulation signal S ₃₀ …… Interfering signal CLA ₁ , CLA ₂ …… Closed loop offset voltage compensation amplifier OLA ₁ , OLA ₂ …… Open loop offset voltage compensation amplifier

Front page continuation (72) Seiichi Kanegae Seiichi Kanegae 325 Kamimachiya, Kamakura City, Kanagawa Prefecture Mitsubishi Electric Corporation Kamakura Factory (72) Inventor Yokichi Hirota 325 Kamimachiya, Kamakura City, Kanagawa Mitsubishi Electric Corporation Kamakura Factory (72) Inventor Atsushi Shimada 325 Kamimachiya, Kamakura City, Kanagawa Mitsubishi Electric Corporation Kamakura Manufacturing Co., Ltd. (56) Reference JP-A 64-16981 (JP, A) Sankaihei 1-107979 (JP, U) Actual development Sho 64-42485 (JP, U) Special table Sho 63-502133 (JP, A)

Claims (3)

(57) [Claims] 1. A subtractor for subtracting an interference wave component signal from a main channel signal obtained from a main antenna to derive the signal, and a signal derived from the subtractor for dividing into a first signal and a second signal. First dividing means for outputting the signal No. 1 to the output terminal as an interfering wave removal signal, and second dividing means for dividing the auxiliary channel signal obtained from the auxiliary antenna and outputting the divided signals as third and fourth signals, The third signal output from the second dividing means is phase-shifted into two phases having a 90 ° phase difference and mixed with the second signal output from the first dividing means to form a quadrature two-phase base. Mixing means for deriving a band signal, switching means for deriving by switching a quadrature two-phase baseband signal output from the mixing means and a ground potential at predetermined time intervals, and a signal output from the switching means, respectively. First and second offset voltage compensating means for compensating the included offset voltage respectively, and first and second integrators for integrating the signals sent from the first and second offset voltage compensating means, respectively. The fourth signal output from the second dividing means is phase-shifted into two phases with a 90 ° phase difference, modulated by the signals output from the first and second integrators, and then combined. An interfering wave removing apparatus comprising: a modulating unit that supplies the interfering wave component signal to the subtractor. 2. The interference wave removing device according to claim 1,
The offset voltage compensating means includes a two-terminal input DC differential amplifier that receives the output signal from the switching means as one input, and a sample hold circuit that receives the output of the DC differential amplifier and samples and holds it at a predetermined time interval. An interfering wave removing apparatus comprising: a closed loop circuit including an integrator that integrates an output signal of the sample-hold circuit and uses the integrated signal as the other input of the DC differential amplifier. 3. The interference wave removing device according to claim 1,
The interference wave removing device is provided with a two-terminal input differential integrator instead of the integrator, and the offset voltage compensating means is provided with a sample and hold circuit for sampling and holding the output signal from the switching means at predetermined time intervals. And an output signal from the switching means are input to the differential integrator, the difference between the two input signals is integrated, and the integrated signal is sent to the modulating means.