KR0142742B1 - Carrier leakage elimination circuit of balanced modulator - Google Patents

Abstract

According to the present invention, a sampling pulse generating means for outputting sampling pulses equal to a period of an input carrier of a balanced modulator, and a frequency modulated signal of the amplified signal output from the modified modulator by sampling pulses output from the sampling pulse generating means are provided. Comprising means for calculating the average voltage for each half period and comparing them to each other and outputting an error voltage generation control signal, and an error voltage generator for generating an error voltage in accordance with the error voltage generation control signal output from the comparison means to return to the balanced modulator. The present invention relates to a carrier leakage cancellation circuit of a balanced modulator, which removes carrier leakage caused by an offset voltage of a balanced modulator because the voltage returned from the balanced modulator is controlled according to the amplitude change of the signal output from the balanced modulator.

Description

Carrier Leakage Cancellation Circuit of Balanced Modulator

1 is a carrier leakage cancellation system diagram of a balanced modulator according to the present invention.

2 is an exemplary embodiment of the comparison means shown in FIG.

3 is a main partial input and output waveform diagram of a carrier leakage cancellation circuit of the balanced modulator according to the present invention.

* Explanation of symbols for main parts of the drawings

10: balance modulator 20: amplification means

30: sampling pulse generating means 40: comparison means

42: first level detection circuit 44: second level detection circuit

46: error voltage generation control circuit 50: error voltage generation unit

The present invention relates to a carrier leakage cancellation circuit of a balanced modulator. More particularly, the balanced modulator detects a waveform change of a frequency-modulated signal generated when an input offset occurs and generates an error voltage. A carrier leakage elimination circuit of a balanced modulator that feeds back and removes carrier leakage.

In general, a balanced modulator, which is widely used in analog transmission circuits and frequency conversion circuits, generates a converted frequency by inputting a carrier signal having a constant frequency generated from a local oscillator and a signal for frequency conversion. In this case, the balanced modulator serves to minimize leakage of the carrier signal at the output of the frequency conversion circuit.

However, in the application of most balanced modulators actually used, there is a drawback that the suppression capability of the carrier is significantly reduced by the characteristic matching and offset voltage of each element constituting the balanced modulator. Although the carrier component could be removed by adjusting the input offset by installing the adjustment terminal outside the chip, there is a problem that it is not practical for commercialization because a separate adjustment terminal is installed outside the chip. Although the carrier component can be removed by implementing the band cancellation filter, the problem is that the chip size is increased because the circuit configuration is very complicated because the characteristics of the band cancellation filter are very sophisticated.

Accordingly, the present invention has been made to solve the above-mentioned shortcomings, and an object of the present invention is to return an error voltage generated by detecting an amplitude of a frequency modulated signal based on a sampling pulse to a balance modulator to reduce carrier leakage. It is to provide a carrier leakage cancellation circuit of the balanced modulator to remove.

In order to achieve the above object, the carrier leakage elimination circuit of the balanced modulator includes sampling pulse generating means for outputting sampling pulses equal to a period of a carrier wave input to the balanced modulator, and a signal output and amplified by the balance modulator. Comparing means for calculating the average voltage for each half period of the signal frequency-modulated by the sampling pulses output from the sampling pulse generating means and comparing them to each other and outputting an error voltage generation control signal, and the error voltage generation output from the comparing means Characterized in that it consists of an error voltage generator for generating an error voltage in accordance with the control signal and fed back to the balance modulator.

Hereinafter, the leakage current cancellation circuit of the balance modulator according to the present invention will be described in more detail with reference to the illustrated drawings.

1 is a block diagram of a carrier leakage cancellation circuit of the balanced modulator according to the present invention, FIG. 2 is an exemplary view of the comparison means shown in FIG. 1, and FIG. 3 is a carrier leakage cancellation circuit of the balanced modulator according to the present invention. The main part of the input and output waveform diagram.

1 and 2, the sampling pulse generating means 30 is configured to output a plurality of sampling pulses SP1, SP2, SP3, SP4 which are the same as the period of the carrier wave input to the balanced modulator 10, The amplifying means 20 is configured to amplify and output the signal output from the balance modulator 10 at a constant level.

On the other hand, the comparison means 40 is the average voltage for each half cycle by the sampling pulses SP1, SP2, SP3, SP4 output from the balanced modulator 10 and amplified by the sampling pulse generation means 30. And first and second level detection circuits 42 and 44 and an error voltage generation control circuit 46 to output the error voltage generation control signal by comparing them with each other. ) Detects the level of the signal output from the field effect transistors MP1 and MN1 and the field effect transistors MP1 and MN1 for switching the output of the balanced modulator 10 according to the levels of the sampling pulses SP1 and SP2. And a transistor Q1 for outputting an average voltage every half cycle of the signal modulated by the balance modulator 10 by the charge / discharge voltage of the capacitor C1, and the second level detection. The circuit 44 depends on the levels of the sampling pulses SP3 and SP4. Field effect transistors MP2 and MN2 for switching the output of the balanced modulator 10, capacitor C2 for detecting the level of the signal output from the field effect transistors MP2 and MN2, and capacitor C2. The transistor Q11 or the like outputs an average voltage every half cycle of the signal modulated by the balance modulator 10 by the charge / discharge voltage.

In addition, the error voltage generation control circuit 46 generates an error voltage in conjunction with the transistors Q13 and Q14 operated according to the voltages output from the first and second level detection circuits 42 and 44, thereby generating a balanced modulator ( The error voltage generator 50 is controlled by the field effect transistors MP5 and MP6 that control the output voltage of the error voltage generator 50 to be returned to 10 and the current flowing through the field effect transistors MP5 and MP6. Transistors Q16, Q17, Q21 and the like which form a discharge route so as to discharge the voltage charged in the capacitor.

Referring to the operation of the carrier leakage cancellation circuit of the balanced modulator according to the present invention having the embodiment as described above as follows.

In the system employing the carrier leakage cancellation circuit of the balanced modulator according to the present invention, if any modulated signal is input to the balanced modulator 10 shown in FIG. 1, the output of the balanced modulator 10 is shown in FIG. In accordance with the carrier input signal as shown in FIG.

The frequency-converted signal output from the balance modulator 10 is amplified by the amplifying means 20 and then input to the first and second level detection circuits 42 and 44 of the comparing means 30. The carrier wave as shown in (A) of FIG. 3 inputted to 10) becomes sampling pulses such as SP1, SP2, SP3, and SP4 of FIG. 3 through the sampling pulse generating means 30, and thus the first and second of the comparison means 30. It is input to the level detection circuits 42 and 44, respectively.

In this way, the sampling pulses SP1 and SP2 (SP3 and SP4) and the amplifying means 20 output from the sampling pulse generating means 30 by the first and second level detection circuits 42 and 44 of the comparing means 40. When the output of the balanced modulator 10 is amplified through the input, the field effect transistors MP1 and MN1 of the first level detection circuit 42 are balanced according to the levels of the sampling pulses SP1 and SP2. By switching the output of the signal and supplying it to the base terminal of the transistor Q5 through the capacitor C1, the transistor Q5 outputs an average voltage V1 corresponding to the frequency-converted signal half period, and the second level detection circuit. The field effect transistors MP2 and MN2 of 44 switch the output of the balanced modulator 10 according to the levels of the sampling pulses SP3 and SP4 and supply them to the base terminal of the transistor Q10 via the capacitor C2. In the transistor Q10, an average voltage V2 corresponding to the frequency-converted signal half period ) Is output.

The average voltages V1 and V2 output from the first and second level detection circuits 42 and 44 are respectively supplied to the base terminals of the transistors Q13 and Q14 of the error voltage generating circuit 46. For example, if the average voltage V1 is "high" and the average voltage V2 is "low" (that is, if the average voltage V1 is greater than the average voltage V2), the transistor Q13 and the field effect transistors MP3 and MP4 ) Is "on", so that the capacitor of the error voltage generator 50 is in a charged state, on the contrary, if the average voltage V2 is "high" and the average voltage V1 is "low" (that is, the average voltage V2) When the average voltage V1 is greater than the transistor Q14, the field effect transistors MP5 and MP6, and the transistors Q17 and Q21 are turned on, the capacitor of the error voltage generator 50 is discharged and the balance modulator ( The voltage fed back to 10) is controlled according to the amplitude change of the signal output from the balance modulator 10.

According to the present invention described above, since the voltage fed back to the balanced modulator is controlled according to the change in amplitude of the signal output from the balanced modulator, carrier leakage caused by the offset voltage of the balanced modulator is removed.

Claims (5)

Sampling pulse generating means for outputting sampling pulses equal to the period of the carrier wave input to the balanced modulator, and for each half period of the signal frequency-modulated by the sampling pulses output from the sampling pulse generating means for the amplified signal output from the balanced modulator. Comprising means for calculating the average voltage and comparing them to each other and outputting an error voltage generation control signal, and an error voltage generation unit for generating an error voltage in accordance with the error voltage generation control signal output from the comparison means to return to the balance modulator A carrier leakage elimination circuit for a balanced modulator. The control circuit of claim 1, wherein the comparing unit calculates an average voltage every half cycle by sampling pulses output from the balance modulator by the sampling pulses output from the sampling pulse generator, and compares them with each other to output an error voltage generation control signal. And a first and second level detection circuit and an error voltage generation control circuit. 3. The first level detection circuit according to claim 2, wherein the first level detection circuit switches the output of the balanced modulator according to the level of sampling pulses having different levels, and the field effect transistors MP1 and MN1. A capacitor (C1) for detecting the level of the signal output from the signal, and a transistor (Q1) for outputting an average voltage every half cycle of the signal modulated by the balance modulator (10) by the charge / discharge voltage of the capacitor (C1). A carrier leakage elimination circuit for a balanced modulator, characterized in that. 3. The second level detection circuit according to claim 2, wherein the second level detection circuit comprises field effect transistors MP2 and MN2 for switching the output of the balanced modulator according to the levels of sampling pulses SP3 and SP4, and the field effect transistors MP2 and MN2. A capacitor (C2) for detecting the level of the signal output from the signal, and a transistor (Q11) for outputting an average voltage every half cycle of the signal modulated by the balance modulator (10) by the charge / discharge voltage of the capacitor (C2). A carrier leakage elimination circuit for a balanced modulator, characterized in that. The transistor (13) (14) according to any one of claims 2 to 4, wherein the error voltage generation control circuit (46) operates according to the voltage output from the first and second level detection circuits (42) (44). ) And an electric current flowing through the field effect transistors MP5 and MP6 for controlling an output voltage of the error voltage generator that generates an error voltage and returns it to the balance modulator 10. And a transistor (Q16, Q17, Q21), etc. for forming a discharge route so as to discharge the voltage charged in the capacitor of the error voltage generator by means of the carrier leakage elimination circuit of the balanced modulator.