JP2519259B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2519259B2 JP2519259B2 JP62234655A JP23465587A JP2519259B2 JP 2519259 B2 JP2519259 B2 JP 2519259B2 JP 62234655 A JP62234655 A JP 62234655A JP 23465587 A JP23465587 A JP 23465587A JP 2519259 B2 JP2519259 B2 JP 2519259B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor chip
- semiconductor device
- lead frame
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、タブなしリードフレームの半導体装置に関
し、特に、レジンモールドパッケージにおいて、タブな
しリードフレーム半導体チップ搭載用絶縁フィルムの半
導体チップ搭載部のコーナに熱，温度サイクヴによる各
部の応力が集中するのを低減させるために、その応力を
分散させる技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tabless lead frame semiconductor device, and more particularly, to a semiconductor chip mounting portion of a tabless lead frame semiconductor chip mounting insulating film in a resin mold package. The present invention relates to a technique of dispersing stress in each part due to heat and thermal cycle to reduce the concentration of the stress in each corner.
従来のレジンモールドパッケージ方式の半導体装置に
おいては、半導体チップはタブ上に搭載されているが、
例えば、４メガ［Ｍ］のダミナミック・ランダム・アク
セス・メモリ（DRAM）のような大きなチップを、且つ30
0ミル［mil］パッケージに収納するにはきわめて困難で
あった。そこで、タブなしリードフレームの半導体チッ
プ搭載部に半導体チップ搭載用絶縁フィルムを接着し、
その上に半導体チップを搭載することが提案されてい
る。In the conventional resin mold package type semiconductor device, the semiconductor chip is mounted on the tab.
For example, a large chip such as 4 mega [M] dynamic random access memory (DRAM)
It was extremely difficult to fit in a 0 mil package. Therefore, attach the semiconductor chip mounting insulating film to the semiconductor chip mounting part of the tabless lead frame,
It has been proposed to mount a semiconductor chip on it.
しかしながら、前記タブなしリードフレームの半導体
チップ搭載部に半導体チップ搭載用絶縁フィルムを接着
し、その上に半導体チップを搭載する方式の半導体装置
では、半導体チップ，リードフレーム，半導体チップ搭
載用絶縁フィルム，レジン等の個々の熱膨張系数αの差
により、温度サイクル時に半導体チップ搭載用絶縁フィ
ルムのコーナ部に応力が集中してパッケージにクラック
を発生することを本発明者は見い出した。However, in a semiconductor device in which a semiconductor chip mounting insulating film is adhered to the semiconductor chip mounting portion of the tabless lead frame and the semiconductor chip is mounted thereon, the semiconductor chip, the lead frame, the semiconductor chip mounting insulating film, The present inventor has found that stress is concentrated in the corner portion of the insulating film for mounting a semiconductor chip during the temperature cycle due to the difference in the individual thermal expansion coefficient α of the resin or the like to cause cracks in the package.
本発明は、前記問題点を解決するためになされたもの
であり、 本発明の目的は、タブなしリードフレームの半導体チ
ップ搭載部に半導体チップ搭載用絶縁フィルムを接着
し、その上に半導体チップを搭載し、レジン等の樹脂封
止材で封止した半導体装置において、前記樹脂封止材に
クラックが発生するのを防止することができる技術を提
供することにある。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to bond a semiconductor chip mounting insulating film to a semiconductor chip mounting portion of a tabless lead frame, and to mount the semiconductor chip thereon. It is an object of the present invention to provide a technique capable of preventing a crack from occurring in the resin sealing material in a semiconductor device mounted and sealed with a resin sealing material such as a resin.
本発明の前記ならびにその他の目的と新規な特徴は、
本明細書の記述及び添付図面によって明らかになるであ
ろう。The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.
本願において開示される本発明のうち、代表的なもの
の概要を簡単に説明すれば、下記のとおりである。The following is a brief description of the outline of the typical invention disclosed in the present application.
すなわち、タブなしリードフレームの半導体チップ搭
載部に半導体チップ搭載用絶縁フィルムを接着し、その
上に半導体チップを搭載し、レジン等の樹脂封止材で封
止した半導体装置において、前記半導体チップ搭載用絶
縁フィルムに応力を分散させる応力分散手段を備えたも
のである。That is, in a semiconductor device in which a semiconductor chip mounting insulating film is bonded to a semiconductor chip mounting portion of a lead frame without tabs, the semiconductor chip is mounted thereon, and the resin is sealed with a resin sealing material such as resin, The insulating film for use is provided with a stress dispersing means for dispersing stress.
前述の手段によれば、半導体チップ搭載用絶縁フィル
ムに応力を分散させる応力分散手段、例えば、半導体チ
ップ搭載用絶縁フィルムを４分割することにより、半導
体チップ搭載用絶縁フィルムに働く応力が４分割に分散
されるので、樹脂封止材にクラックが発生するのを防止
することができる。According to the above-mentioned means, the stress distribution means for distributing the stress to the semiconductor chip mounting insulating film, for example, by dividing the semiconductor chip mounting insulating film into four, the stress acting on the semiconductor chip mounting insulating film is divided into four. Since they are dispersed, it is possible to prevent cracks from occurring in the resin sealing material.
以下、本発明の一実施例を図面を用いて具体的に説明
する。An embodiment of the present invention will be specifically described below with reference to the drawings.
なお、実施例を設計するための全図において、同一機
能を有するものは同一符号を付け、その繰り返しの説明
は省略する。In all the drawings for designing the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof is omitted.
本実施例の半導体装置は、第１図に示すように、タブ
なしリードフレーム１のインナー部1aの半導体チップ搭
載部に半導体チップ搭載用絶縁フィルム（以下、絶縁フ
ィルムという）２が接着されている。この絶縁フィルム
２は、分割絶縁フィルム2a,2b,2c,2dからなっており、
分割絶縁フィルム2a,2b,2c,2dは、例えば、厚さ125μｍ
からなるポリイミド系樹脂材（Dupon製のカプトンＨ）
で構成されている。また、この分割絶縁フィルム2a,2b,
2c,2dの形状は、それぞれ長方形の絶縁フィルムを対角
線で切って４分割したものである。In the semiconductor device of this embodiment, as shown in FIG. 1, a semiconductor chip mounting insulating film (hereinafter referred to as an insulating film) 2 is bonded to the semiconductor chip mounting portion of the inner portion 1a of the tabless lead frame 1. . This insulating film 2 is composed of divided insulating films 2a, 2b, 2c, 2d,
The divided insulating films 2a, 2b, 2c, 2d have a thickness of 125 μm, for example.
Polyimide resin material (Kapton H made by Dupon)
It is composed of Also, this divided insulation film 2a, 2b,
The shapes of 2c and 2d are obtained by cutting a rectangular insulating film with a diagonal line and dividing it into four.
この分割絶縁フィルム2a,2b,2c,2dとリードフレーム
１のインナー部1aとの接着は、例えば、厚さ20〜30μｍ
のポリアミドイミド等のリードフレーム接着剤３（第９
図）によって行われる。このポリアミドイミド接着剤
は、270〜300℃温度までの熱に耐え得る。The divided insulating films 2a, 2b, 2c, 2d and the inner portion 1a of the lead frame 1 are bonded to each other with a thickness of, for example, 20 to 30 μm.
Lead frame adhesive 3 such as polyamide imide
Figure). This polyamide-imide adhesive can withstand heat up to temperatures of 270-300 ° C.
そして、第２図乃至第４図に示すように、分割絶縁フ
ィルム2a,2b,2c,2dの上に半導体チップ４がペレット付
接着剤５によりペレット付される。Then, as shown in FIGS. 2 to 4, the semiconductor chips 4 are pelletized by the pelletized adhesive 5 on the divided insulating films 2a, 2b, 2c, 2d.
このペレット付接着剤５としては、非導電性のRZ012C
又はRO041CをベースにSiO2とフィラーしたものを用い
る。半導体チップ４とリードフレーム１とは、ボンディ
ングワイヤ６によって電気的に接続される。ボンディン
グワイヤ６としては、Au,Al,Cu及びこれらの被覆ワイヤ
が用いられる。このボンディングワイヤ６のボンディン
グエリヤ部は、銀（Ag）メッキされている。この状態で
レジン等の封止材７で封止される。As the adhesive with pellets 5, non-conductive RZ012C
Or use those SiO 2 and filler RO041C based. The semiconductor chip 4 and the lead frame 1 are electrically connected by a bonding wire 6. As the bonding wire 6, Au, Al, Cu and their covered wires are used. The bonding area of the bonding wire 6 is plated with silver (Ag). In this state, it is sealed with a sealing material 7 such as a resin.
このように、半導体チップ４を搭載する絶縁フィルム
を分割して分割絶縁フィルム2a,2b,2c,2dに分割するこ
とにより、分割絶縁フィルム2a,2b,2c,2dに働く応力は
４分割に分散されるので、レジン等の樹脂封止材７にク
ラックが発生するのを防止することができる。In this way, by dividing the insulating film on which the semiconductor chip 4 is mounted and dividing it into the divided insulating films 2a, 2b, 2c, 2d, the stress acting on the divided insulating films 2a, 2b, 2c, 2d is divided into four. Therefore, it is possible to prevent cracks from being generated in the resin sealing material 7 such as the resin.
また、前記分割絶縁フィルム2a,2b,2c,2dの替わり
に、第５図に示すように、長方形の絶縁フィルムの中央
部を除去し、対角線に沿って切った形状の分割絶縁フィ
ルム2e,2f,2g,2hにしてもよい。Further, instead of the divided insulating films 2a, 2b, 2c, 2d, as shown in FIG. 5, the central portion of the rectangular insulating film is removed, and the divided insulating films 2e, 2f are cut along a diagonal line. , 2g, 2h may be used.
また、第６図に示すように、長方形の絶縁フィルムの
中央部を除去した形状の絶縁フィルム2iにしてもよい。Further, as shown in FIG. 6, an insulating film 2i may be formed by removing the central portion of the rectangular insulating film.
また、第７図に示すように、長方形の所定位置に複数
の穴を設けた絶縁フィルム2jにしてもよい。このように
絶縁フィルム２の形状を変化させることによって応力の
逃げが量的に異なる。Alternatively, as shown in FIG. 7, an insulating film 2j may be used in which a plurality of holes are provided at predetermined rectangular positions. By changing the shape of the insulating film 2 as described above, the relief of stress varies quantitatively.
なお、本発明の絶縁フィルム２の形状は、前記リード
フレーム１のインナーリード部と絶縁フィルム２とが少
なくとも一点で支持され、応力を分散する形状のもので
あればどのような形状あってもよい。例えば、絶縁フィ
ルム２をうず巻状の形状，千鳥状の形状等に構成したも
のでもよい。The insulating film 2 of the present invention may have any shape as long as the inner lead portion of the lead frame 1 and the insulating film 2 are supported at at least one point to disperse stress. . For example, the insulating film 2 may have a spiral shape, a zigzag shape, or the like.
また、第２図に示すように、本実施例の半導体装置の
パッケージと半導体チップ４の寸法関係の一例を示す
と、パッケージの長辺の長さ（寸法）が22.26mm、パッ
ケージの短辺の長さが7.30mm、半導体チップ４の長辺の
長さが15.22mm、半導体チップ４の短辺の長さが5.91mm
である。このように、本実施例によれば、タブなしリー
ドフレーム１の半導体チップ搭載部に接着された絶縁フ
ィルム２の上に半導体チップ４を搭載する方式にしたの
で、パッケージの短辺の長さが7.30mmであるのに対し
て、半導体チップ４の短辺の長さが5.91mmまでの大きさ
にすることができる。As shown in FIG. 2, an example of the dimensional relationship between the package of the semiconductor device of this embodiment and the semiconductor chip 4 is shown. The length (dimension) of the long side of the package is 22.26 mm and the short side of the package is The length is 7.30 mm, the long side of the semiconductor chip 4 is 15.22 mm, and the short side of the semiconductor chip 4 is 5.91 mm.
Is. As described above, according to this embodiment, since the semiconductor chip 4 is mounted on the insulating film 2 bonded to the semiconductor chip mounting portion of the tabless lead frame 1, the length of the short side of the package is reduced. While the length is 7.30 mm, the length of the short side of the semiconductor chip 4 can be up to 5.91 mm.
次に、本実施例の半導体装置の組立方法について簡単
に説明する。Next, a method of assembling the semiconductor device of this embodiment will be briefly described.
第８図及び第９図（第８図のIX−IX切断線で切断した
断面図）に示すように、テープ状の台紙10の上に、ペレ
ット付接着剤５を塗布した分割絶縁フィルム2a,2b,2c,2
dからなるパターンを所定間隔で配置し、分割絶縁フィ
ルム2a,2b,2c,2dのそれぞれの上にリードフレーム接着
剤３を塗布し、台紙10の両側の辺部にそれぞれのパター
ンの位置決めの穴11を設けた絶縁フィルム部材12を用意
する。前記台紙10の材料は、例えば、セロハン等を用い
る。As shown in FIGS. 8 and 9 (cross-sectional view taken along the line IX-IX in FIG. 8), a tape-like mount 10 is coated with the adhesive 5 with pellets, and the divided insulating film 2a, 2b, 2c, 2
A pattern consisting of d is arranged at a predetermined interval, the lead frame adhesive 3 is applied on each of the divided insulating films 2a, 2b, 2c, 2d, and holes for positioning each pattern are provided on both sides of the mount 10. An insulating film member 12 provided with 11 is prepared. The material of the mount 10 is, for example, cellophane.
そして、第10図に示すような複数のリードフレーム１
が一列に所定間隔で配列されたテープ状のリードフレー
ム部材13の上に、第８図に示す絶縁フィルム部材12を、
リードフレーム接着剤３側を内側にして載置する。この
時、リードフレーム部材13の各リードフレームの位置決
め穴14と絶縁フィルム部材12の各パターンの位置決め穴
11とを合致させて、リードフレーム１の所定位置上に分
割絶縁フィルム2a,2b,2c,2dを配置して接着させ、台紙1
0をはがして、第１図に示すように、リードフレーム部
材13上の半導体搭載部に分割絶縁フィルム2a,2b,2c,2d
のパターンを接着する。Then, a plurality of lead frames 1 as shown in FIG.
On the tape-shaped lead frame member 13 in which the rows are arranged at a predetermined interval, the insulating film member 12 shown in FIG.
The lead frame adhesive 3 side is placed inside. At this time, the positioning holes 14 of each lead frame of the lead frame member 13 and the positioning holes of each pattern of the insulating film member 12
11 and the divided insulating films 2a, 2b, 2c, 2d are arranged on the predetermined positions of the lead frame 1 and adhered to each other, and the mount 1
Peeling off 0, as shown in FIG. 1, the divided insulating films 2a, 2b, 2c, 2d are attached to the semiconductor mounting portion on the lead frame member 13.
Glue the pattern.
次に、第２図乃至第４図に示すように、第１図に示す
絶縁フィルム２（分割絶縁フィルム2a,2b,2c,2dのパタ
ーン）の上に半導体チップ４をダイボンディングした
後、半導体チップ４のパッドとボンディングワイヤ６及
びリードフレーム１のインナー部1aとボンディングワイ
ヤ６とをそれぞれウエッジ・ボールボンディングによっ
て電気的に接続する。次に、レジン等の封止材７で封止
して第３図に示すように、リードフレーム１のアウター
部1bを所定長さに切断した後、所定形状に折り曲げて半
導体装置が完成する。Next, as shown in FIGS. 2 to 4, after the semiconductor chip 4 is die-bonded on the insulating film 2 (patterns of the divided insulating films 2a, 2b, 2c, 2d) shown in FIG. The pads of the chip 4 and the bonding wires 6, and the inner portion 1a of the lead frame 1 and the bonding wires 6 are electrically connected by wedge ball bonding. Next, as shown in FIG. 3, after sealing with a sealing material 7 such as a resin, the outer portion 1b of the lead frame 1 is cut into a predetermined length and then bent into a predetermined shape to complete a semiconductor device.
以上、本発明を実施例にもとづき具体的に説明した
が、本発明は、前記実施例に限定されるものではなく、
その要旨を逸脱しない範囲において種々変更可能である
ことは言うまでもない。As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various modifications can be made without departing from the spirit of the invention.
以上、説明したように、本願において開示された新規
な技術によれば、以下に述べる効果を得ることができ
る。As described above, according to the novel technique disclosed in the present application, the effects described below can be obtained.
半導体チップ搭載用絶縁フィルムに応力を分散させる
応力分散手段を設けたことにより、半導体チップ搭載用
フィルムに働く応力が分散されるので、封止材にクラッ
クが発生するのを防止することができる。By providing the stress dispersing means for dispersing stress on the semiconductor chip mounting insulating film, the stress acting on the semiconductor chip mounting film is dispersed, so that cracks can be prevented from occurring in the sealing material.
第１図は、本発明の一実施例のタブなしリードフレーム
に４分割絶縁フィルムを接着した平面図、 第２図は、第１図に示す４分割絶縁フィルム上に半導体
チップを搭載し、樹脂封止した半導体装置の平面図、 第３図は、第２図のIII−III切断線で切断した断面図、 第４図は、第２図のIV−IV切断線で切断した断面図、 第５図乃至第７図は、それぞれ本発明の絶縁フィルムの
他の実施例の概略構成を示す平面図、 第８図は、第１図に示す４分割絶縁フィルムの接着前の
絶縁フィルム部材の概略構成を示す平面図、 第９図は、第８図のIX−IX切断線で切断した断面図、 第10図は、第１図に示すリードフレーム部材の概略構成
を示す平面図である。 図中、１……リードフレーム、２……絶縁フィルム、2
a,2b,2c,2d……分割絶縁フィルム、３……リードフレー
ム接着剤、４……半導体チップ、５……ペレット付接着
剤、６……ボンディングワイヤ、７……封止材、10……
台紙、11……パターンの位置決めの穴、12……絶縁フィ
ルム部材、13……リードフレーム部材、14……各リード
フレームの位置決め穴である。FIG. 1 is a plan view in which a four-division insulating film is adhered to a tabless lead frame according to one embodiment of the present invention, and FIG. 2 is a diagram in which a semiconductor chip is mounted on the four-division insulating film shown in FIG. A plan view of the sealed semiconductor device, FIG. 3 is a sectional view taken along the line III-III of FIG. 2, FIG. 4 is a sectional view taken along the line IV-IV of FIG. 5 to 7 are plan views each showing a schematic configuration of another embodiment of the insulating film of the present invention, and FIG. 8 is a schematic view of the insulating film member before the four-divided insulating film shown in FIG. 1 is bonded. FIG. 9 is a plan view showing the structure, FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG. 8, and FIG. 10 is a plan view showing the schematic structure of the lead frame member shown in FIG. In the figure, 1 ... Lead frame, 2 ... Insulating film, 2
a, 2b, 2c, 2d ...... Separated insulation film, 3 ...... Lead frame adhesive, 4 …… Semiconductor chip, 5 …… Pellets with adhesive, 6 …… Bonding wire, 7 …… Encapsulation material, 10 ・ ・ ・…
Mount, 11 ... Pattern positioning hole, 12 ... Insulating film member, 13 ... Lead frame member, 14 ... Positioning hole for each lead frame.
Claims (6)
載部に半導体チップ搭載用絶縁フィルムを接着し、その
上に半導体チップを搭載し、樹脂封止材で封止した半導
体装置において、前記半導体チップ搭載用絶縁フィルム
に働く応力を分散させる応力分散手段を備えたことを特
徴とする半導体装置。1. A semiconductor device in which a semiconductor chip mounting insulating film is adhered to a semiconductor chip mounting portion of a lead frame without tabs, the semiconductor chip is mounted on the insulating film, and the semiconductor chip is sealed with a resin sealing material. A semiconductor device comprising a stress dispersing means for dispersing stress acting on an insulating film for a vehicle.
のインナーリード部と半導体チップ搭載用絶縁フィルム
とが少なくとも一点で支持されるように、前記半導体チ
ップ搭載用絶縁フィルムを複数に分割したことを特徴と
する特許請求の範囲第１項に記載の半導体装置。2. The stress distributing means divides the semiconductor chip mounting insulating film into a plurality of pieces so that the inner lead portion of the lead frame and the semiconductor chip mounting insulating film are supported at at least one point. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
割は、４分割であることを特徴とする特許請求の範囲第
２項に記載の半導体装置。3. The semiconductor device according to claim 2, wherein the insulating film for mounting the semiconductor chip is divided into four parts.
載用絶縁フィルムの中央部を除去したことを特徴とする
特許請求の範囲第１項に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the stress distribution means removes a central portion of the semiconductor chip mounting insulating film.
載用絶縁フィルムに複数の穴を設けたことを特徴とする
特許請求の範囲第１項に記載の半導体装置。5. The semiconductor device according to claim 1, wherein the stress dispersion means has a plurality of holes formed in the insulating film for mounting semiconductor chips.
面には半導体チップ付接着剤が設けられ、裏面にはリー
ドフレーム付接着剤が設けられていることを特徴とする
特許請求の範囲第１項乃至第５項の各項に記載の半導体
装置。6. An adhesive with a semiconductor chip is provided on a front surface of the insulating film for mounting a semiconductor chip, and an adhesive with a lead frame is provided on a back surface thereof. A semiconductor device according to each of the items 5 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62234655A JP2519259B2 (en) | 1987-09-17 | 1987-09-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62234655A JP2519259B2 (en) | 1987-09-17 | 1987-09-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6476741A JPS6476741A (en) | 1989-03-22 |
| JP2519259B2 true JP2519259B2 (en) | 1996-07-31 |
Family
ID=16974413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62234655A Expired - Fee Related JP2519259B2 (en) | 1987-09-17 | 1987-09-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2519259B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2644773B2 (en) * | 1987-10-28 | 1997-08-25 | 株式会社日立製作所 | Resin-sealed semiconductor device |
| US5084753A (en) * | 1989-01-23 | 1992-01-28 | Analog Devices, Inc. | Packaging for multiple chips on a single leadframe |
| JP2503638B2 (en) * | 1989-03-24 | 1996-06-05 | 日本電気株式会社 | Semiconductor device |
| US5278101A (en) * | 1989-06-28 | 1994-01-11 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| JP2765265B2 (en) * | 1991-05-13 | 1998-06-11 | 日立電線株式会社 | Lead frame for semiconductor device |
-
1987
- 1987-09-17 JP JP62234655A patent/JP2519259B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6476741A (en) | 1989-03-22 |
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