JP2517172Y2 - Static induction transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an electrostatic induction transistor used in a high frequency induction heating oscillator or the like.

[Conventional technology]

Conventionally, static induction transistor (hereinafter referred to as SIT).
Are roughly classified into two types according to the gate structure. First
As a type of, the embedded gate type SIT has a structure in which the gate is embedded between the drain layer and the source layer.
This type of SIT is most suitable for high withstand voltage and high power consumption. The second type is a surface wiring type SIT in which the gate and the source layer are formed on the drain layer on substantially the same plane.
Is. Among the surface wiring type SITs, there is a cut gate type SIT which is formed by slightly cutting the source layer and forming a gate at the bottom of the groove.

Among the above SITs, the embedded gate type SIT is shown in Fig. 2. In this figure, in order to show the planar shape of the gate, in which the source layer is excluded, 4'is a gate electrode portion, 9 and 9'are metal thin films formed on the gate electrode 4 ',
It is the feeding point. The gate 10 'is formed in a striped pattern between the gate electrodes 4'and 4'provided with the feeding points 9 and 9'.

[Problems to be solved by the invention] However, in the conventional gate-shaped SIT, the feeding points 9, 9 '
Especially in the high frequency region where the voltage applied to 1 exceeds 1 MHz, the gate resistance γ _g cannot be ignored, and it drops at the intermediate portion between the feeding points 9 and 9 ′. As a result, the channel in the central part of the SIT cannot respond to the input signal, and there are some open and closed parts of the channel, which prevents the SIT element from operating normally.

[Means for solving problems]

The electrostatic induction transistor according to the present invention is characterized in that the planar shape of the gate is a lattice shape, and that the lattice spacing becomes narrower as the distance from the feeding portion to the intermediate region between the two feeding portions increases. And

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 (b) illustrates an embodiment of the present invention with reference to the drawings. FIG. 1 (b) is a vertical cross-sectional view of the buried gate type SIT of the present invention, which shows a gate P ⁺ between the drain N ⁻ layer 6 and the source N layer 7 on the drain ohmic N ⁺ layer.
Layer 12 is embedded. A plan view of the buried gate layer is shown in FIG. In the figure, 4 is the gate electrode part, and 8 and 8'are the feeding points of the metal thin film formed on the gate electrode. The plane shape of the buried gate layer 12 is a vertical stripe gate.
A horizontal stripe gate 11 is formed so as to be orthogonal to 10. Here, in the second area 2 which is slightly far from the first area 1 near the feeding points 8 and 8 ', the interval of the horizontal striped gates 11 gradually becomes smaller, and the interval between the feeding points 8 and 8'is near the middle. The space between regions 3 of 3 is the smallest. In this way, since the horizontal striped gates 11 are formed so as to be orthogonal to the vertical striped gates 10 and have a narrower interval as the distance from the feeding point increases, it is easy for the gate current to flow to the gate middle portion. That is, in FIG. 1, the length of the vertical striped gates between the horizontal striped gates becomes shorter as the distance from the feeding points 8, 8'is increased.
A square mesh is formed in the center part between them. In this case, the farther from the feeding points 8 and 8 ', the more the branching of the gate progresses, so that the decrease in the gate resistance γ _g is smaller than that in the conventional shape. Further, especially in the mesh-shaped gate portion in the central portion, since the vertical and horizontal dimensions are the same, the potential barrier height in the channel is substantially doubled as compared with the conventional vertical striped gate alone. There is. Therefore, even if there is a slight voltage drop, the operation is balanced without being left behind in the operation of the striped portion on the outer peripheral portion. Furthermore, the height of the potential barrier of the channel in the mesh gate part in the central part is higher than that in the striped gate part in the peripheral part, which means that the drain current of the SIT element is prevented from being biased toward the central part of the element. Since it also has the structure at the same time, it is a structure that also helps prevent the destruction of the device.

In the embodiment of the present invention, the impurity concentration Nd of the drain N ⁻ layer is:
6 × 10 ¹³ cm ^-3 gate concentration _{NG (S)} : 2 × 10 ¹⁹ cm ^-3 , region 1 gate length: region 2 gate length: region 3 gate length = 4: 2:
In the case of 1 (channel width 7.0μ) SIT element, the cut-off frequency _r is 15 M in the present invention compared with the conventional gate pattern element.
Hz, 10MHz with the conventional element.

[Effect of device]

As described above, according to the present invention, it is possible to provide a SIT element having improved frequency characteristics and breakdown resistance without changing the element area.

[Brief description of drawings]

FIG. 1 (a) is a plan view showing the gate portion of the static induction transistor according to the present invention except for the source layer thereof, and FIG. 1 (b) is the XY line portion of FIG. 1 (a). FIG. 2 is a vertical cross-sectional view including the source layer, and FIG. 2 is a plan view of a gate portion of a conventional static induction transistor. 4 ... Gate electrode, 5 ... Drain ohmic N ⁺ layer, 6 ...
... Drain N ^- layer, 7 ... Source N layer, 8,8 ', 9,9' ... Feeding point, 12 ... Embedded gate layer.

Claims (1)

(57) [Scope of utility model registration request] 1. A buried gate type static induction transistor, comprising a power supply section made of a metal film formed at both ends of the buried gate, wherein the buried gate has a grid-like planar shape, and An electrostatic induction transistor, characterized in that the lattice spacing is made narrower as the distance between the two feeding portions becomes an intermediate region.