JP2510262B2 - Asynchronous data transmission device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an asynchronous data transmission apparatus suitable for asynchronously transmitting data between two system controllers, and particularly to a first system controller for one system controller. And a clock used for the second determination is different from the clock used for the third determination in the other system controller.

[Conventional technology]

When data transmission is performed between two system controllers, a buffer device is usually provided between these controllers in order to synchronize hardware and adjust speed.

In the conventional device, one buffer device is provided, and access from one controller is prioritized over access from the other controller to prepare for an access collision. Alternatively, when one of the controllers is accessing, a busy signal is output to the other controller to wait for the section access. In this case, the controllers will weigh each other, hindering the actual operating time of the controllers. The same is true even if only one of the busy signals is issued.

[Problems to be Solved by the Invention]

However, in such a conventional configuration, for example, when data transfer from the system controller A to the system controller B is considered and it is set that the write request of the controller A has priority over the read request of the controller B, when a write request is made during reading, Since the data will be different before and after the read, there arises a problem that the controller B cannot handle the data of the same time and the same content of the controller A.

This is a serious problem when transferring one set of data from the system controller A to the system controller B, and accurate data transfer cannot be performed.

In this type of data transfer, different system clocks are usually used in the system controllers A and B. Therefore, the write request of the controller A and the read of the controller B which are generated in synchronization with these different system clocks are performed. Requests may occur at exactly the same time, and in such a case, a write and a read will collide with the same memory.

The present invention has been made in view of such circumstances,
It is an object of the present invention to provide an asynchronous data transmission device that can perform accurate and reliable data transmission between two system controllers that use different system clocks and that does not cause the two system controllers to wait.

[Means for solving the problem]

According to the present invention, data transmission between the first system controller and the second system controller using different system clocks is shorter than the non-access time of the first system controller from the first system controller. In an asynchronous data transmission device for transmitting data to a second system controller having access time, a readable / writable first memory for temporarily storing data output from the first system controller, and the first and second A predetermined priority is set in advance for an access from the system controller, the output data of the first system controller or the temporary storage data of the first memory is written, and the write data is changed to the second data. Parallel configuration to read to system controller Determining the access states of the second and third memories and the second system controller by the second system controller with the start of the write request from the first system controller, at least three times, by shifting the time. Then
First determining means for obtaining at least three determination results, majority determining means for obtaining a majority decision logic of the determination results of the first determining means, and the second and the third based on the output of the majority determining means and the priority. A first selecting means for selecting a side memory which is not accessed by the second system controller among the memories; and a first selecting means for responding to a write request from the first system controller. First write means for performing first write control for simultaneously writing the output data of the first system controller to the memory corresponding to the selection result and the first memory; and with the end of the first write control, the first write means. Second judging means for judging the access states of the second and third memories by the second system controller at least twice at different times; Second writing means for performing second writing control for writing the data stored in the first memory to the other memory of the memories selected by the first selecting means according to the determination result of the second determining means; A third method of determining an access state to the second and third memories by writing from the first system controller or the first memory at the time of starting a read request from the second system controller.
And a second memory for selecting the memory on the side not accessed by the first system controller from the second and third memories based on the output of the third determination means and the priority. The second means in response to a read request from the selecting means and the second system controller;
Reading means for reading stored data from the memory corresponding to the selection result of the selecting means and outputting it to the second system controller.

[Action]

In such a configuration, the memory holding the data to be transferred is duplicated (second memory, third memory), and the first system controller on the data transmission side and the second and third memories When the first system controller is arranged between them and the data is written to the second and third memories from the first system controller, the data is written in two times at different times (first Write control, second write control). At the time of the first write, the access states of the second and third memories by the second system controller are determined at least three times with a time lag, and the majority of these determination results is taken. Of the third memories, the memory on the side not accessed by the second system controller is selected, and the data is written to the selected memory and the first memory. At the time of the second writing, the second
The access states of the second and third memories by the system controller are determined at least twice by shifting the time, and when the determination results match, the second or third memory accessed in the first write is accessed. The data in the first memory is written to the other side. In this way, the second
And write the same data to the third memory. Further, when reading data from the second and third memories, the second and third memories written by the first system controller or the first memory are responded to in response to a read request from the second system controller. Of the second memory and the third memory, the memory on the side not accessed by the first system controller is selected in accordance with the result, and data is selected from the selected memory. Read out.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the accompanying drawings.

FIG. 1 shows a conceptual configuration of an embodiment of the present invention, and FIG. 2 shows a detailed configuration example thereof.

1 and 2, the system controller
A and B are provided in, for example, an industrial machine. In this case, a system controller (hereinafter abbreviated as controller) A is a master controller that controls and manages the industrial machine itself, and has a normal computer configuration including a CPU, a memory and the like. Further, the system controller B exchanges data with sensors and actuators installed in various places of the industrial machine.

The configuration shown in FIG. 1 shows a configuration for transmitting data from the controller A to the controller B. Regarding the memory access period of the controllers A and B, the non-access time TNA (in this case It is premised that the non-writing time) is longer than the memory access period TB of the controller B (reading time in this case).

That is, to be precise, it is premised that the non-access time TNA of the system A> the time Td required for the post-write + the access time TB of the system B (FIGS. 4 (a) and (j)).
reference). The rear light will be described later.

In this case, the system controller A operates by the system clock CKA, and the controller B operates by the clock CKB. These clocks CKA, CKB
Are completely different in terms of their period, phase, etc.

The memory 10 is a write / read dual port RAM that can be accessed by both controllers A and B. In this case, the most significant bit "ALH" or "ARH" of the address.
By setting H to L, the memory area is divided into two on the H side and the L side, whereby the second and third memories in the claims are realized. When accessing from the controller A side, set the "ALH" to H / L to select the H / L side area, and when accessing from the controller B side, set "ARH" to H / L to H / L Select the L side area. That is, in this case, the memory 10 has a so-called duplicated structure, and the H-side region and the L-side region of the memory 10 are controlled by the control logic unit 30 to be described later at each writing cycle of the controller A, as a result. The exact same data is written.

In this case, since data transfer in only one direction from the controller A to the controller B is a problem as described above, the controller A writes only
Controller B only reads.

A buffer circuit is provided between the controller A and the memory 10.
20 are provided. The buffer circuit 20 temporarily stores the output data DT and the address AD of the controller A at the time of writing data from the controller A to the memory 10, and thereafter stores the temporarily stored data in the control logic unit.
According to the signal from 30, the H side area of memory 10 and L
It outputs to either one of the side areas. In this case, two FIFOs 20 and 25 (first in first out circuit: First in First
out) is used. That is, the FIFO 20 stores the address from the controller A, and the FIFO 25 stores the data from the controller.

Next, before explaining the internal configuration of the control logic unit 30,
The signal input / output terminals of the memory 10 and the FIFOs 20 and 25 will be described.

▲ ▼: Chip select from the left side of the memory 10 (controller A side), ▲ ▼: Chip select from the right side of the memory 10 (controller B side), ▲ ▼: Write enable signal of the memory 10: Read enable signal of the memory 10 ALH: Highest address bit of memory 10, signal from left (controller A side) to divide memory 10 into H / L area ARH: Highest address bit of memory 10, right side (Controller B side) ) Signal for dividing memory 10 into H / L areas AD: Address signal DT: Data ▲ ▼: FIFO write enable signal ▲ ▼: Data empty flag output from FIFO:
(H when there is stored data in FIFIO, L when all stored data is read from the FIFO,) ▲ ▼: FIFO read enable signal IN: FIFO data input pin OUT: FIFO data output pin control The logic unit 30 is connected to the control buses CB of the controllers A and B as shown in FIG. 1 (specifically, the write request signal ▲ ▼ from the controller A and the read request signal ▲ ▼ from the controller B are input. ), Which controls writing / reading of the memory 10 and the FIFOs 20 and 25, and is constituted by a plurality of circuits 31 to 54 as shown in FIG. The logics of the plurality of circuits of the control logic unit 30 are all configured by hardware such as flip-flops and logic gates.

Hereinafter, before describing each circuit configuration of the control logic unit 30, the memory 10 and the FIFOs 20, 2 by the control logic unit 30 are described.
The logical configuration of the write / read control for 5 will be briefly described.

First, the memory 10 has an L level for writing / reading.
The side area is set to have a higher priority than the H side area.

When the write request signal ▲ ▼ is output from the controller A, the same data of the controller A is written in the H side area and the L side area of the memory 10 by performing the writing twice in the memory 10 at different times. Put in.

At the time of the first write (hereinafter referred to as the previous write), either the H side area or the L side area of the memory 10 and the FIFO 25
The data is written simultaneously to and the address is written to FIFO20. As to which of the H / L side areas of the memory 10 to select, the state of the controller B side is judged at the start of the transmission of the signal A from the controller A. If the controller B has already read and accessed any of the H / L areas of the memory 10 at this point of time, the controller A writes to the area on the opposite side, and the controller B also writes to the memory 10 If not accessed, writing is performed to the L side area on the priority side.

At the time of the second writing (hereinafter referred to as “post-writing”), the data written in the FIFO25 and the FIFO20 during the above-mentioned writing
After writing the address written above to the FIFO25,2
The data read from 0 and the data read from the FIFO 25 are written in the H / L area on the opposite side of the area selected at the time of the previous write of the memory 10 according to the address output from the FIFO 20. However, at the start of writing after this, if the controller B is accessing the area on the opposite side where the data from the FIFO 25 is to be written, the controller B waits until the access of this controller B ends, and after the access ends To do.

When the controller B outputs the read request signal ▲ ▼ (L during the read section), this ▲
▼ The state of the controller A is judged at the start of signal transmission.
When writing access to any of the H / L areas,
Reading is performed from the area on the opposite side, and when the controller A is not accessing, reading is performed from the L side area on the priority side.

When determining the status of the partner controller, the following method is used to prevent simultaneous access of both controllers to the same area of memory 10 that occurs when the status of the partner controller is judged at the same time. I am trying to do it.

That is, when the controller A performs the previous write, the judgment process for selecting the memory area (H / L area) to be accessed by the self controller A based on the status judgment of the partner controller B is performed a plurality of times, for example, 3 times. Times,
Stagger the time. Then, the majority decision of the decision results at these three different times is taken, and the memory area which the controller A actually accesses is decided by the result of the majority decision. For example, when the judgment results at the three time points are H, L, and L (H; H side region is selected; L; L side region is selected), the result of the majority decision is L and the controller A
Accesses the L side area. In addition, the above three judgment results
When L, H, H, the result of the majority decision is H and the controller A accesses the H side area. It should be noted that taking three majority votes means that the result of the majority vote cannot be obtained only by the first decision result, and at least two decision results are required to obtain the three majority results. That is, the memory access area of the controller A at the time of the previous write is determined after the determination result is obtained at least twice.

The result of the majority decision is used as a flag signal indicating the memory access state of the controller A to judge the status of the partner controller A when the controller B reads. The flag signal is in a state corresponding to the first determination result when the first determination result is output.

When the memory B is read by the controller B, the state of the controller A side is judged based on the flag signal only once at the start of sending the read request signal ▲ ▼, and the memory area accessed by the own controller B is determined according to this judgment. decide. When the read request signal ▲ ▼ is started at the first determination time point of the three different time point determinations, the controller B is set to access the L side area on the priority side as the determination at exactly the same time point. ing.

The above is the outline of the logic of the control logic unit 30, and the operation of the configuration of FIG. 1 will be described below in various cases with reference to the time charts of FIGS. 3 to 5.

In FIGS. 3 to 5, (a) is generated from the write request signal ▲ ▼ output from the controller A.
▼ A signal (described later), (b) a previous write in which the previous write section is delayed by the delay circuit 40, (c) a clock signal ck, and (d) a read request signal output from the controller B ▲ ▼ And the read period, (e) is ▲
▼ A flag that is set by judging the state of the partner controller B when the signal falls, (f) is the same flag that is set after a half clock ck when the signal falls, and (g) is a ▲ ▼ signal 1 clock ck at the falling edge of
The same flags that will be set later, (h) is flag 1 to
3 is a flag for which a majority decision has been taken, (i) is a flag for deciding a memory area to be selected at the time of pre-writing and post-writing,
(J) shows the post-write period, respectively. In addition, (e) ~
The flags 1 to 3 shown in (g) indicate the determination process for selecting the memory area to be accessed by the self controller A based on the status determination of the partner controller B at the time of the previous write as described above. The results are shown at two different times. Moreover, these FIGS.
In the figure, L is active for signals other than the flag signal, and the symbol above each signal indicates the H / L region on the selected side of the memory 10.

FIG. 3 shows a state in which the controller 13 is already accessing the memory 10 at the start of the previous write.

In FIG. 3, since the controller B is accessing the L side area of the memory 10 at time t ₀ , the H side area is selected as the access target of the controller A side. As a result, the time t ₁ to the time t _In the period of ₃ , pre-write processing is performed in which the data of the controller A is written in the H side area of the memory 10 and the data and address of the controller A are written in the FIFOs 25 and 20. Note that time t ₂
In reading processing of the controller B in ~t _4, since the H-side region of the memory 10 is occupied by the controller A at time t _2, L-side region is selected as the access target controller B.

Next, the time t ₃ when the front light of the controller A ends
In, the controller B occupies the L-side area (the area opposite to the front light) where the rear light is to be performed. Therefore, the control logic unit 30 waits until the access of the controller B ends, and starts the post-write from the end point (time t ₄ ). The rear light ends at time t ₅ .

FIG. 4 shows a case where the signal A generated from the signal A of the controller A (the trailing edge which will be described later and the trailing edge of the signal B of the controller B simultaneously fall (time t ₀ ). In this case, The other party's status will be judged at the same time. At this time, the controller B, which judges only once, judges that the ▲ ▼ indicating the access of the controller A is H (not accessed). Will select the L side.

Therefore, from time t ₀ , the controller B starts the memory 1
A read access to the 0 side L area is started. On the other hand, the flag 1 indicating the result of selecting the memory area own controller A side based on the state of the mating controller B at time t ₀ is trying to access is detected the memory access to L region of the mating controller B at time t ₀ It remains L because it cannot be done. However, at time t half a clock later
_When it becomes ₁ , the state of the partner controller B can be detected, so the flag 2 rises to H, which is the opposite of the memory access area L of the controller B, at time t ₁ . Flag 3 is also the same, and rises to H at time t ₂ . Therefore, the majority flag from which the majority logic of these flags 1 to 3 is output rises to H at time t ₂ . The write area selection flag has the same logical value as the majority flag when the previous write,
In the case of post-write, it is the inverted value of the majority vote flag. Accordingly, then, the data output from the controller A is written to the H-side area of the memory 10 (time t ₃ ~t _4). Of course, before the write period in the time t ₃ ~t _4, data and address of the controller A is written into FIFO25,20. Time t ₄ when the front light of the controller A ends
In, the controller B does not access the L-side area that is going to perform the post-write. Therefore,
In this case, post-write is performed immediately from time t ₄ without waiting time.

Fig. 5 shows the ▲ ▼ signal of controller A (to be exact, ▲
A half clock after the falling of the ▼ signal) and the falling time of the ▼ signal of the controller B are shown at the same time.

At time t _0, the controller B so not performed the memory access, the flag 1 has a preferential side L at time t _0. At a time t _{1 which} is a half clock after the time t ₀ , the read request signal ▲ ▼ of the controller B falls to L, and at this time, the majority flag,
The state of the partner controller A is judged based on the ▲ ▼ indicating the access of the controller A and the rear light. In this case, at time t ₁ , the majority flag is L and ▲ ▼ is L (the controller A is accessing the L side). Therefore, the H area opposite to the majority flag is selected as the read target area of the controller B. As a result, during the period from time t _{1 to} t ₃ , the controller B reads from the H side area of the memory 10.

On the other hand, at time t _1, the controller B because it has to select the H-side region, flag 2, flag 3 performing the decision operation at time t _1, t ₂ remains L. Therefore, the majority flag also maintains L, and as a result, the previous write is started for the L side area of the memory 10 from time t ₂ . At the time t ₄ when the previous write of the controller A is completed, the controller B does not access the H side area to perform the post write. Therefore, also in this case, as in FIG. 4, the post-write is immediately performed from time t ₄ .

Next, each circuit configuration in the control logic unit 30 will be described with reference to FIG. Note that, in FIG. 2, the system clock CK is input to various places, but the input state is shown only for important points, and the other parts are omitted.

The write request signal {circle around ()} (FIGS. 6 and 7 (a)) of the controller A is input to the previous write section generation circuit 31 and the gate 41. The pulse cycle of the system clock CK is sufficiently shorter than the pulse width of the write request signal WR.

The previous write section generation circuit 31 is composed of a one-shot multivibrator circuit, a flip-flop, etc., takes in the write request signal ▲ ▼ at the falling edge of the system clock CK, and thereafter holds the L state for a predetermined time TA.
▼ Form a signal and output it (Fig. 7 (b)). That is, the ▲ ▼ signal is T during one writing period of the controller A.
A large number of signals are sequentially output from the controller A to A (see FIG. 6), and the signal ▼ is L corresponding to the period in which these signals ▼ are being output.

This ▲ ▼ signal is the state cross-section circuit on the system B side.
It has been entered in 32 mag.

The system B side state determination circuit 32 includes a gate 33 and five Ds.
The flip-flops 34 to 38 and the majority circuit 39. ▲ ▼ signal is D of flip-flop 34
By being input to the terminal, the signal is delayed by a half cycle (half clock) of the clock signal CK.
The signal (FIG. 7 (c)) is output from the flip-flop 34. This ▲ ▼ signal is further input to the flip-flop 36, so that the ▲ ▼ signal is delayed by one cycle (1 clock) of the clock CK.
The signal (FIG. 7 (d)) is output from the flip-flop 36. That is, ▲ ▼, ▲
The ▼ signal is obtained by delaying the ▲ ▼ signal by half a clock, and the ▲ ▼ signal, ▲ ▼ signal, and ▲ ▼ signal are each flip-flop 3
Input to the clock terminals of 5,37,38. The output SBLA of the gate 33 is connected to the D terminals of these flip-flops 35, 37 and 38.
Has been entered.

The gate 33 outputs the read request signal ▲ ▼ of the system controller B and the output AR of the system A side state determination circuit 47.
By taking the AND of each inverted output of H, the state on the system B side is judged, and in response to this judgment, the controller A side judges which area (H / L area) of the memory 10 should be selected, Output signal SBLA. The SBLA signal has a property as a judgment material for the controller A side to decide which H / L area of the memory 10 to select.

The ARH signal indicates which of the H / L areas the controller B selects when reading by the controller B, and the logical configuration for outputting the ARH signal will be described in detail later. When the ARH signal is H, the H side area of the memory 10 is selected, and when the ARH signal is L, the L side area is selected.

That is, the configuration including the gate 33 and the flip-flop 35 determines the access state on the controller B side based on the states of the ▲ ▼ signal and the ARH signal when the ▲ ▼ signal falls to L, and the controller A responds to this determination. The side determines which region (H / L region) of the memory 10 to select, and outputs a signal ABC1 indicating the determination result (FIG. 7 (e)). That is, the signal ABC1 is
▼ ▼ signal when the signal falls to L and
The truth table is determined by the state of the ARH signal, and is shown in Table 1 below.

That is, as described above, in the memory 10, the L side area is prioritized.
When the signal is H, that is, when the controller B is not accessing, the ABC1 signal becomes L corresponding to the priority area (L area) of the memory 10, and the ▲ ▼ signal is L at the start of the previous write.
That is, when controller B is accessing, ABC1
The signal becomes the opposite of the ARH signal, and the controller B tries to select the area opposite to the area being accessed.

Further, the flip-flop 37 sets the output SBLA of the gate 33 to ▲
▼ When the signal falls, that is ▲
▼ It is latched half a clock after the falling edge of the signal and output as the ABC2 signal (Fig. 7 (f)). flip flop
38 latches the output SBLA of the gate 33 at the time of the falling of the signal, that is, one clock after the falling of the signal, and outputs it as the ABC3 signal (FIG. 7 (g)).

That is, the flip-flops 35, 37, 38 latch the output of the gate 33 at three different time points shifted by half a clock to judge the state of the controller B three times with different times, and respond to each of these judgments. Then, the flag signal ABC indicating the memory area (H / L area) to be selected by the controller A side
Outputs 1, ABC2, ABC3.

These flag signals ABC1 to ABC3 are input to the majority decision circuit 39, and the majority decision circuit 39 takes the majority decision logic of these input signals. That is, the majority decision circuit 39 receives these input signals AB
A majority decision is taken at each time point of C1 to ABC3, and the result of the majority decision is output as A10H (FIG. 6 (l), FIG. 7 (p)). For example, ABC1 to ABC3 at a certain time point, L, L,
When H, L is output, and at some point ABC1 to ABC3
When L, H, L, L is output, and similarly, when H, H, L, H is output.

On the other hand, the ▲ ▼ signal is input to the delay circuit 40,
Here, after a time delay of several clocks CK, the signal is input to the gate 41. The gate 41 is ▲ ▼ from the controller A.
The NAND of the signals and the inverted outputs of the delayed outputs of the above signals is taken and the outputs are input to the terminals of the FIFOs 20 and 25 (FIG. 6 (e), FIG. 7 (j)). As mentioned above, the pulse period of the system clock CK is sufficiently shorter than the pulse width of the WR signal.
▼ The output of the delay circuit 40 which delayed the signal by several clocks and ▲
▼ By inputting a signal to the gate 41,
▼ The first pulse of the signal is not erased (7th pulse)
See figure). The delay circuit 40 is the ALH of the memory 10 at the time of previous write.
This is for gaining time until the output of the selector 50 is input to the terminal. When the input to the ▲ ▼ terminal of the FIFO 20, 25 is L, the address signal and the data signal output from the controller A are written in the storage areas of the FIFO 20, 25, respectively.

A ▲ ▼ signal and a ▲ ▼ signal are input to the pre-write end detection circuit 42, and the pre-write end time is defined based on these input signals. In this case, ▲
An intermediate time between the ▼ signal rising edge and the ▲ ▼ signal rising edge, that is, the ▲ ▼ signal rising edge is set as the end of the previous write, and at this time point, the previous write end signal WRED is output.

The ▼ signal, the WRED signal, and the feedback signal from the FIFO 20 are input to the ▲ ▼ generation circuit 43, and the inside thereof is composed of a plurality of logic gates, flip-flops, and the like. As described above, the signal (FIG. 6 (h), FIG. 7 (m)) is the empty flag of the FIFO 20, and is in the H state while the above-mentioned front write and rear write are performed. The ▲ ▼ generation circuit 43 rises when the WRED signal rises, that is, when the ▲ ▼ signal rises, and rises when the ▲ ▼ signal falls.
▼ Form a signal. That is, the signal ▲ ▼ becomes L from the end of the front write to the end of the rear write.

Selector 50 controls ▲ ▼ signal and ▲ ▼
The A10H signal and its inverted signal are switched according to the state of the signal and output as the ALH signal. The output ALH is a non-inverted output of the signal A10H when the ▲ ▼ signal is L (during approximately before writing). Is selected and the ▲ ▼ signal is L
In this case (from the end of the previous write to the end of the subsequent write), the inverted output of the signal A10H is selected, and when the ▲ ▼ and ▲ ▼ signals are H, L is selected corresponding to the priority area of the memory 10. . That is, the selector 50 selects the area on the opposite side to the area on the side of the front writing at the time of the rear writing. Output from this selector 50
The ALH signal is input to the ALH terminal that selects the H side area and the L side area of the memory 10.

Next, the read request signal ▲ ▼ output from the controller B is directly input to the ▲ ▼ terminal and the terminal of the memory 10. Therefore, the stored data is always read from any of the H / L areas of the memory 10 while the signal (L) is L. That is, there is no waiting time for reading. Which of the H / L areas is selected for reading is determined by the ARH signal output from the system A side state determination circuit 47 (FIG. 6 (n), FIG. 7 (o)).
Determined by This system A side state judgment circuit 47
The logical configuration of will be described in detail later, but its outline will be briefly described. That is, the output ARH of this judgment circuit 47 is
▼ ▼ signal and AL when the signal falls to L
The truth table determined by the state of the H signal is shown in Table 2 below.

When the ARH signal is H, the H side area of the memory 10 is selected, and when the ARH signal is L, the L side area of the memory 10 is selected.

The post-write wait condition generation circuit 44 stores the memory 1 from the FIFO 20, 25.
The post-write to 0 generates a part of the conditions waited for by the access to the memory 10 of the controller B. The ▲ ▼ signal, the ARH signal and the A10 signal.
The H signal is used as an input signal and the signal is output (Fig. 6 (j)). The signal ▲ ▼ becomes L when the weighting conditions shown in Table 3 below are satisfied.

That is, in the above table, the inversion signal of A10H represents the memory area for post-write, so when the inversion of A10H and ARH (access area on the controller B side) match, and the ▲ ▼ signal is L At this time (while the controller B is accessing), it is necessary to make the post-write wait, and the signal ▼ is set to L.

The signal ▲ ▼ is input to the D terminals of the flip-flops 45 and 46. The inverted signal of the system clock CK is input to the clock terminal of the flip-flop 45, and the non-inverted signal of the system clock CK is input to the clock terminal of the flip-flop 46. ▼ The signals are latched twice at a timing shifted by half a clock CK, and their outputs are input to the gate 48.

The gate 48 takes the AND signal of the inverted signal of the signal and the outputs of the flip-flops 45 and 46, and outputs the inverted signal as the signal (FIG. 6 (k), FIG. 7 (l)). That is, the gate 48 forms and outputs a signal which becomes L only during the post-write period.

This ▲ ▼ signal is input to the gates 49, 52 and 53. The gate 49 takes the NOR of the inverted signal of the ▲ ▼ signal and the inverted signal of the ▲ ▼ signal, and inputs the NOR output ▲ ▼ to the ▲ ▼ terminal of the memory 10. That is, by the gate 49, at the time of the front light (▲
▼) and after light (▲ ▼) ▲ ▼
The signal becomes L, and at this time, the memory 10 is chip-selected from the left side.

The signal ▲ ▼ is also input to the system A side state determination circuit 47. The A-side state determination circuit 47 determines the access state on the controller A side based on the ▲ ▼ signal and the ALH signal input as described above at the time when the ▲ ▼ signal falls to L, and the controller responds to this determination. B
The side determines which area (H / L area) of the memory 10 to select, and outputs a signal ARH signal indicating the selection result (FIG. 6 (n)). The truth table is as shown in Table 2. As with the ALH signal, when the ARH signal is H, the H side area of the memory 10 is selected, and when the ARH signal is L, the L side area of the memory 10 is selected.

By the way, the system A side state determination circuit 47 is
As shown in the table, the L side area is prioritized. Therefore, when it is determined that the controller A side is not accessing due to the fall of the ▲ ▼ signal (▲ ▼ signal is H), immediately L
It is designed to access the side area. Therefore, when the rear write of the controller A is in the L side area, the read request signal from the controller B is
When the falling edge of ▼ and the start of the post-write occur at the same time, there is a possibility that the read and the post-write are performed on the same L-side area. In order to prevent this, two flip-flops 45, 46 are provided, and the flip-flops 45, 46
▼ Two signals are latched by shifting the time, and these latched signals are input to the gate 48.

The gates 52 and 53 are respectively supplied with pulse signals with a slight phase shift from the pulse generator 51.
A pulse signal input to the other terminal of 3 switches between passage and interruption of the pulse signal. That is,
(2) When the signal is L, the pulse output from the pulse generator 51 is output from each gate 52, 53.

The pulse signal that has passed through the gate 52 is
Input to the terminal (Fig. 6 (d)). Therefore, FI
Addresses and data stored during the previous write are output from the FOs 20 and 25 in accordance with the output pulse of the pulse generator 51 when the signal ▼ becomes L. The address output from the FIFO20 is input to the AD terminal of the memory 10,
The data output from the FIFO 25 is input to the DT terminal of the memory 10.

On the other hand, the pulse signal that has passed through the gate 53 is input to the gate 54. The gate 54 takes the NOR of the output of the gate 41 and the output of the gate 53 and inputs it to the ▲ ▼ terminal of the memory 10. That is, the gate 54 stores the pulse train necessary for the front write and the rear write by taking the NOR of the output of the gate 41 indicating the front write and the output of the gate 53 indicating the during the rear write.
Input to ▲ ▼ terminal of 10.

In this case, the post-write is the hardware configured FIFO.
Since it is output control from 20,25, front light (▲
From ▼ to ▲ ▼) its length (▲
▼) is extremely short, and the same number of pulse signals as the ▲ ▼ signals are output during the period when the ▲ ▼ signal is L. This is because ▲ ▼ is output when the number of data written by the system A is read from the FIFO 20, and ▲ ▼ causes H to stop, that is, the pulse from the pulse generator.

 The above is the configuration of the control logic unit 30.

Next, the overall operation of the control logic unit 30 will be described with reference to the time chart shown in FIG. In addition,
The explanation of the operation relating to FIG. 6 is not always exact with respect to time.

At the time t ₁ , the first A signal is output from the controller A (Fig. 6 (a)). The previous write section generation circuit 31 triggers the L state of this first-shot signal at the falling edge of the clock CK, and then the controller A
Outputs a signal that holds this L state for a predetermined time TA during the access. This ▲
The signal is delayed by one clock by the flip-flops 34 and 36, further delayed by several clocks by the delay circuit 40, and then input to the gate 41. At gate 41 ▲ ▼
Signals are also being input. The output of the gate 41 is input to the ▲ ▼ terminals of the FIFOs 20 and 25, and is also input to the ▲ ▼ terminal of the memory 10 via the gate 54 (FIG. 6 (c),
(E)). ▲ ▼ and ▲ ▼ are write enable terminals, respectively. Almost at the same time (approximately time t ₁ ) ▲
▼ Signal is sent to the memory 10 via the gate 49 ▲
Input to the terminal (Fig. 6 (d)), and the chip select from the left side becomes possible.

Further, at the same time, the system B side state determination circuit 36
Is Signal at the time of each fall and
The state of the controller B side is judged by the majority logic based on the state of the ARH signal, and the memory is judged based on this judgment result.
It outputs a signal indicating which of the 10 H / L areas is selected. In this case, the ▲ ▼ signal is near the time t _1.
Since the H and ARH signals are L, the A10H signal becomes L so that the L side area on the priority side is selected. This A10H signal is a selector
It is input to the ALH terminal of the memory 10 via 50. As a result, during the period from time t ₁ to time t ₇ , the data of the controller A is written in the L side area of the memory 10 in synchronization with the signal ▼ of the system controller A, and the address of the controller A is stored in the FIFO 20. A pre-write process is executed in which the data of the controller A is written and the data of the controller A is written in the FIFO 25.

Note that the controller B is still accessing (reading) during this pre-write processing, and the system A
In side state determination circuit 47, ▲ ▼ at each fall time of the signal (time _{t 2, t 3, t 4} , t 5, t 8) determines the access status of the controller A side controller B based on the determination result
Determines which area of memory 10 to access. In this case, during the period of the previous write, the controller A uses the memory 10
Since the L side area is selected, the access target of the controller B during the previous write is the H side area, as can be seen from the ARH signal.

After that, when the pre-write process ends, this
▼ The preceding write end detection circuit 42 detects the rising of the signal, and the WRED signal is output from the circuit 42 (time t
₇ ).

With this WRED signal, the signal {circle around (1)} output from the circuit {circle around (43)} falls to L at time t ₇ .
As described above, the selector 50 outputs the inverted signal of the A10H signal during the period when the signal ▲ ▼ is L, and therefore, the time t ₇
The ALH signal becomes H during the period from t ₉ to t ₉ .

In this case, the memory that is going to write after
There is a waiting time (TC) because the controller B is performing read access to the H side area (A10H) of 10. Therefore, after the waiting time TC exists, the post-write is started by the configuration of the post-write waiting condition generation circuit 44, the flip-flops 45 and 46, and the gate 48. That is,
At time t ₉ , the ▲ ▼ signal falls to L due to the rising of the ▲ ▼ signal, and then at time t ₉ ▲
The ▼ signal rises to H by the rise of the PFD signal caused by the fall of the ▲ ▼ signal. This period of time t ₈ ~t ₉ is the rear light period, during this period FIFO20,25 ▲
The output pulse of the pulse generator 51 is input to the ▼ terminal (read enable) by the ▲ ▼ signal (FIG. 6 (d)), and the pulse generator is connected to the ▲ ▼ terminal (write enable) of the memory 10. Output pulse of 51 is input. Furthermore, the ▲ ▼ terminal of the memory 10 is also ▲
▼ Chip select state by signal.

Therefore, during this period of time t ₈ ~t _9, FIFO20
Output, that is, the address signal output from the controller A at the time of the previous write is input to the AD terminal of the memory 10, and the output of the FIFO 25, that is, the data output from the controller A at the time of the previous write is stored in the memory 10. Since it is input to the DT terminal and the ALH terminal is H at this time, as a result, the data output from the controller A at the time of the previous write is written in the H side area of the memory 10. Then, as a result of the subsequent writing, the stored contents of the L side area and the H side area of the memory 10 become exactly the same.

FIG. 7 shows a time chart when the falling edge of the ▲ ▼ signal and the falling edge of the ▲ ▼ signal of the controller B are at the same time. This is a detailed time chart at the start of the previous write, which is shown in FIG. 4 above. Equivalent to. That is, FIG. 7 is a drawing obtained by greatly extending the time axis of FIG. As described above, the signal ▲ ▼ indicates the read section of the controller B, and is set to L while the controller B reads all the data.

In FIG. 7, at time t ₁ , the ▲ ▼ signal and the ▲ ▼ signal fall almost at the same time. In this case, the fall of the ▲ ▼ signal is assumed to be slightly earlier than the fall of the ▲ ▼ signal.

In this case, the system A side state determination circuit 47 determines the ARH signal based on the logic of the above Table 2 at this time t ₁ .
Output. In this case, since the signal ▼ is H at time t ₁ , the ARH signal holds the L state. On the other hand, ▲
▼ The output of the flip-flop 35 at the time when the signal falls, that is, the ABC1 signal, becomes LOW according to the logic in Table 1 above because the ▲ ▼ signal falls slightly earlier than the ▲ ▼ signal falls (∵ ▲ ▼ is H).

Further, since the ▲ ▼ signal is directly input to the ▲ ▼ terminal and the terminal of the memory 10, the read access to the L side area of the memory 10 is started at the same time when the ▲ ▼ signal falls.

The flip-flop 37 latches the output SBLA of the gate 33 again at a time point (time t ₂ ) after a half clock delay from the fall of the signal ▼. At this time t ₂ , the signal and the AR input to the gate 33 and AR
Since the H signal is L and L, respectively, the ABC2 signal rises to H at time t ₂ . Similarly, the ABC3 signal has a time t ₂
It rises to H at time t ₃ after half a clock CK. Therefore, they, A10H signals taking a majority logic of the ABC1~ABC3 signal rises at time t ₃ in H.

On the other hand, the gate 41 delays the ▲ ▼ signal to the delay circuit 40.
The NAND logic of the inverted signal of the signal delayed by several clocks and the inverted signal of the ▲ ▼ signal is taken, and the output is FIFO20,25.
Input to the ▲ ▼ terminal of and the ▲ ▼ terminal of the memory 10. Therefore, in this case, the data of the controller A is written in the FIFO 25 and the memory 10 and the address of the controller A is written in the FIFO 20 from the time t ₄ when the inputs to the terminals ▲ ▼ and ▲ ▼ fall to L. The front light is started. The area in which the data of the controller A is written is the H area, which is the opposite of the access area (L area) of the controller B.

As described above, according to the configuration of the system B side state determination circuit 32, both controllers A and B are never accessed to the same area even when the status determination of the partner controller is made at the same time. In this example, the case where the falling edge of the ▲ ▼ signal is slightly earlier than the falling edge of the ▲ ▼ signal is shown. However, the access does not collide even in the opposite case, and the access is performed even at the same time. There is no collision.

FIG. 8 shows a time chart when the falling edge of the ▲ ▼ signal and the falling edge of the ▲ ▼ signal of the controller B are the same. This is a detailed time chart at the start of the previous write, which is shown in FIG. 5 above. Equivalent to.

In FIG. 8, the ABC1 signal is L at the time t ₁ when the signal ▼ falls to L because the signal ▼ is H (see Table 1). Therefore, at time t ₁ , the A10H signal output from the majority decision circuit is also L,
The ALH signal is also L.

At the time t _2, the system A side state judgment circuit 47 judges that the partner side controller A is accessing the L side area based on the inputted ALH signal, and reverses the ARH signal. Start up to H. As a result, the read access by the controller B is started to the H side area of the memory 10 at the same time as the falling of the signal at the time t ₂ .

On the other hand, in the system B side state judgment circuit 32,
▼ A signal ABC2 indicating the memory area to be selected by the self controller A at the time t _{2 which} is delayed by a half clock from the falling edge of the signal and at the time t _{3 which} is delayed by a half clock from the falling edge of the signal. , ABC3 is output, but in this case, ▲ ▼ is H (the controller B is not accessing) or the controller B starts the actual read access to the H side area of the memory at time t ₂ . There is. Therefore, the ABC2 signal and the ABC3 signal also remain in the L state, and as a result, the A10H signal and the ALH signal also remain in the L state.

On the other hand, ▲ ▼ terminal of memory 10 and ▲ ▼ of FIFO20,25
▼ terminal is at the falling edge of ▲ ▼ signal (time t
_It falls to L after a predetermined time (time t ₄ ) from ₃ ).

As a result, from time t _4, the data of the controller A is written in the L side area of the memory 10 and the FIFO 25, and the address of the controller A is written in the FIFO 20.

In this way, the falling of the ▲ ▼ signal is ▲
(C) The collision of the memory access area can be reliably avoided even when the signal falls at the same time.

The operation when the falling edge of the RD signal coincides with the falling edge of the ▼ signal is almost the same as in FIG. 8, and in this case also, the collision of the memory access area can be avoided.

As described above, according to the configuration of this embodiment, when the controller A and the controller B are operating at different clocks, the clock used for the first and second determinations by the controller A side is the clock by the controller B side. Even when the determination time of 3 is irrelevant to the phase, access collision to the same memory area can be preferably avoided. Particularly, the collision at the start of the front write can be avoided by the configuration of the majority circuit 39 and the collision at the start of the rear write can be avoided by the flip-flops 45, 46.

Although the memory 10 is divided into two by the most significant bit address in the above embodiment, the memory 10 may be divided into two by the least significant bit other than the most significant bit as a duplicated structure of the memory. Further, a memory composed of two different chips may be used. Also,
The logical configuration of the control logic unit 30 may be any other logical configuration as long as it achieves a function equivalent to these. Furthermore, instead of the FIFO as the buffer circuit, a normal aggregate of flip-flops may be used.

〔The invention's effect〕

As described above, according to the present invention, in data transmission between system controllers having different memory access periods and using different system clocks, access to the same memory area can be performed without waiting two system controllers. It is possible to preferably avoid the collision of data, so that the data will not be interrupted in the middle of the access period of each system controller, whereby the system controller on the receiving side can receive the same time and contents of the controller on the transmitting side. The data can be received, and thus the error-free and accurate data transmission can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed block diagram of an internal circuit configuration of the above-mentioned embodiment device, and FIGS. 3 to 5 are conceptual diagrams showing the operation of the above-mentioned embodiment device. The time charts shown in FIGS. 6 to 8 are time charts for explaining more detailed actions of the embodiment apparatus. A, B: System controller, 10: Memory (dual port memory), 20,25: Buffer circuit (FIFO), 3
0 …… Control logic section.

Claims (2)

(57) [Claims] 1. Data transmission between a first system controller and a second system controller, which use different system clocks, respectively, and the data is transmitted from the first system controller according to a non-access time of the first system controller. In an asynchronous data transmission device for transmitting data to a second system controller having a short access time, a readable / writable first memory for temporarily storing data output from the first system controller; A predetermined priority order is preset for access from the second system controller, and
Output data of the system controller or temporary storage data of the first memory is written, and the write data is read to the second system controller, and second and third memories in parallel configuration, A first system controller determines a state of access to the second and third memories by the second system controller with the start of a write request, and determines at least three times at different times to obtain at least three determination results. No. 1 determination means, majority decision means for taking majority decision logic of the decision result of the first decision means, and the second of the second and third memories based on the output of the majority decision means and the priority. First selection means for selecting a memory on the side not accessed by the system controller; and the first system controller. A first write control for simultaneously writing the output data of the first system controller to the memory corresponding to the selection result of the first selecting means and the first memory in response to the write request from the controller. Write means for determining the access state to the second and third memories by the second system controller upon completion of the first write control, and determining the access state at least twice by shifting the time.
And the second write control for writing the stored data of the first memory to the other memory of the memories selected by the first selecting means in accordance with the determination result of the second determining means. Second
Writing means and third judgment for judging the access states to the second and third memories by the writing from the first system controller or the first memory at the start point of the read request from the second system controller. Means and second selecting means for selecting one of the second and third memories on the side not accessed by the first system controller based on the output of the third determining means and the priority. And a read means for reading the stored data from the memory corresponding to the selection result of the second selecting means and outputting it to the second system controller in response to the read request from the second system controller. Transmission equipment. 2. The second writing means writes the data stored in the first memory of the second and third memories to the memory to which the second system writes the second system. The asynchronous device according to claim 1, further comprising a standby unit for waiting the second write control until the access of the second system controller is completed when the determination result that the controller is accessing is output. Data transmission equipment.