JP2508979C - - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus controller for a computer system connected via a bus, and more particularly to a bus for controlling a bus interface of a microprocessor. It relates to a control device. 2. Description of the Related Art An example of this type of conventional bus control device is an IBM-PC / AT.
FIG. 3 shows a configuration of a bus control device of an ISA (Industry Standard Architecture) bus included in the system and its compatible machine. As shown in FIG. 3, in a conventional bus control device 12, an address strobe signal which is a control signal output from a microprocessor in a write cycle of the microprocessor 1 in synchronization with a clock output signal CLKOUT8. ASTB4,
It takes in the write / read signal W / R5 and the memory / IO signal M / IO6 and generates a memory write signal MWTC20 and an I / O write signal IOWC21, which are ISA bus control signals. The output of each ISA bus control signal must be maintained at an active level for a certain period in accordance with the ISA bus regulations. During this time, the microprocessor 1 is in a wait state. When the microprocessor 1 starts a write cycle to the ISA bus 19, it first outputs an address strobe signal ASTB4 for transmitting the start of the bus, and then writes a write signal W / R5 and a memory / IO Outputs signal M / IO6 and immediately enters the wait state. The write / read signal W / R5 is a signal for instructing a write request at a high level and a read request at a low level. In the following, the write / read signal is limited to the description of a write cycle. It is simply called "write signal." Next, the bus control unit 12 converts each control signal from the microprocessor 1 into MWTC20 and IOWC21, which are ISA bus control signals. At that time,
A latch enable signal LE13 for latching the address bus 2 and the data bus 3 is output to the latch 10 and the data latch 11. When the control signals MWTC20 and IOWC21 output to the ISA bus hold the active level for a certain period of time, and when the signal CHRDY22 requesting extension of the active level of the control signals MWTC20 and IOWC21 is input from the ISA bus side During this period, the active level is maintained for a period obtained by adding the output width of the signal CHRDY22 to the certain period. A period in which each ISA bus control signal is obtained by adding an extension by the signal CHRDY22 to a fixed period defined by the ISA bus (6 clocks in an 8-bit I / O standard cycle and 3 clocks in a 16-bit I / O) After the output, the bus controller 12 outputs a ready signal RDY7 to the microprocessor 1 to notify that the bus control has been completed. The microprocessor 1 samples the input ready signal RDY7 at a predetermined timing, and if active, releases the wait state and writes the signal.
End the cycle and start the next instruction cycle. [0011] As described above, in the conventional bus control device,
While outputting the control signal to the bus, the microprocessor is in a wait state, and an empty cycle of several clocks to ten or more clocks is generated until the next instruction cycle is executed. Due to such a bus bottleneck caused by a difference in operating speed between the microprocessor and the bus, the processing capability of the microprocessor itself, whose operating frequency keeps increasing, has not been maximized. Further, it is a cause of hindering improvement in the processing performance of the entire system. Accordingly, the present invention solves such a problem, and provides a bus control device which shortens the wait state of the microprocessor caused by a difference in the operation speed between the microprocessor and the bus and improves the processing performance of the system. The purpose is to do. According to the present invention, there is provided a bus control device for controlling an interface between a microprocessor and a bus, the bus control device including a write control signal output from the microprocessor. A latch circuit to which the control signal is input, and a bus for transmitting the write control signal latched by the latch circuit.
A synchronizing circuit which converts a control signal output to the bus use, outputs a latch enable signal to the latch circuit receives a control signal such as the write control signal and the address driving signals output from the microprocessor A latch control circuit, and a ready control circuit for outputting a ready signal for notifying the microprocessor of the end of the bus control, wherein the latch control is performed when the microprocessor starts a write cycle for the bus. The circuit activates the latch enable signal, the latch circuit latches the predetermined control signal, and the ready control circuit latches the predetermined control signal in the latch circuit and outputs a signal through the synchronization circuit.
A bus control device for activating the ready signal immediately after being output as a bus control signal. According to the present invention, in addition to the conventional synchronizing circuit in the bus control device,
A latch circuit for latching a control signal from a microprocessor, a latch control circuit for generating a latch timing for the latch circuit and an output timing for an ISA bus, and for releasing a wait state for the microprocessor And a ready control circuit for generating a ready signal. The operation of the present invention will be described below. In the present invention, by providing the above-described latch circuit and control circuit, when the microprocessor executes a write cycle for the ISA bus, the microprocessor performs a write cycle before the cycle on the ISA bus ends. By outputting the ready signal immediately, the microprocessor can shift to the next instruction cycle. Therefore, especially in a system using a microprocessor having an operation frequency higher than the bus frequency of the ISA bus, the wait time of the microprocessor can be reduced.
The number of cycles can be reduced, and the processing performance of the entire system can be improved. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. As shown in FIG. 1, the bus control circuit 12 includes a latch circuit 16 for latching a control signal output from the microprocessor 1, a latch control circuit 14 for outputting a latch enable signal LE15 of the latch circuit 16, A ready control circuit 17 for outputting a ready signal RDY7 for permitting the microprocessor 1 to end the bus cycle;
It is composed of a synchronization circuit 18. The latch circuit 16 receives a write / read signal W / R5 and a memory / IO signal M / IO6, which are control signals output from the microprocessor 1, as inputs. Is latched and output to the synchronization circuit 18. The synchronization circuit 18 receives the output of the latch circuit 16, decodes the write / read signal W / R 5 and the memory / IO signal M / IO 6, and outputs a memory write / control signal for the ISA bus 19. A signal MWTC20 and an I / O write signal IOWC21 are generated. The synchronization circuit 18 is provided with a wait control signal CHRD from the ISA bus 19.
Input Y22 to control the extension of the cycle to the bus. An example of the configuration of the ready control circuit 17 will be described with reference to FIG. The ready control circuit 17 receives the memory write signal MWTC20 or the I / O write signal IOWC21 output from the synchronization circuit 18 and connects the edge trigger D type latch circuits 25 and 26 in two stages. The clock output signal CL is supplied to the latch circuit 26 at the subsequent stage.
KOUT8 is inverted and supplied through an inverter 28, and the latch circuit 26 takes in data at the trailing edge of the clock output signal CLKOUT8. The gate circuit 27 has an input signal latched at the leading edge of the clock output signal 8 by the latch circuit 25 at a low level, and an input latched by the latch circuit 26 at the trailing edge of the previous clock output signal 8. Only when the signal (delayed by a half cycle) is at a high level, the ready signal RDY7 is made active (low level). As shown in FIG. 1, the output signal of the decoder 9 for decoding the address bus 2 of the microprocessor 1 is input to the bus control device 12, and the input signal of the ready control circuit 17 shown in FIG. Includes control signals MWTC20, IOWC21 and IS
The logical product with the output signal of the decoder 9 indicating that the A bus 19 has been selected is input. Next, with reference to FIG. 4, the operation of the write cycle of the bus control device 12 according to the present embodiment will be described with reference to a timing chart. In this embodiment, the operating frequency of the microprocessor 1 is 33 MHz,
The bus clock signal BCLK23 of the ISA bus 19 is set to 8.25 MHz. As shown in FIG. 4, when a write cycle is started, the microprocessor 1 first activates the address strobe signal ASTB4 (low level), and then activates the write signal W / R5 (high level). The latch control circuit 14 makes the latch enable signal LE15 active (low level) at the trailing edge of the address strobe signal ASTB4 based on the write signal W / R5. The synchronization circuit 18 converts this write signal W / R5 into a memory write signal MWTC20 or an I / O write signal IOWC21 which is an ISA bus signal. The ready control circuit 17 inputs the memory write signal MWTC20 or the I / O write signal IOWC21 generated by the synchronization circuit 18, and outputs the clock after the MWTC20 or IOWC21 becomes active (low level). At the leading edge of the signal CLKOUT8, both inputs of the gate circuit 27 become active, the ready signal RDY7 is made active (low level), and the ready signal RDY7 is output to the input terminal of the microprocessor 1. The ready signal RDY7 becomes inactive (high level) at the trailing edge of the clock output signal CLKOUT8. The microprocessor 1 makes the write signal W / R5 inactive (low level) at the trailing edge of the input ready signal RDY7, and ends the write cycle on the microprocessor side. Microprocessor 1 that has completed the write cycle
Starts the execution of the next instruction cycle immediately without waiting for the end of data writing to the ISA bus 19. Even after the microprocessor 1 completes the write cycle, the write signal W / R5, the memory / IO signal M / IO6, and the address latch 10 of the microprocessor 1 latched by the latch circuit 16 are latched. Address 2, data
The data 3 latched by the latch 11 is transmitted by the latch control circuit 14 to the next latch enable signal LE.
It is held until 13,15 is output. Thereafter, the synchronizing circuit 18 generates a signal based on the signal CHRDY22 on the ISA bus.
Memory write signal MWTC20, I / O write signal IOWC, which is an ISA bus control signal
21 is kept active for a certain period of time, and the wait control signal CHRD from the ISA bus is
Y22 is sampled, and a wait cycle is inserted if the signal CHRDY22 is inactive. If the sampled wait control signal CHRDY22 is active, the synchronization circuit 18 makes the memory write signal MWTC20 and the I / O write signal IOWC21 inactive, and ends the write cycle of the ISA bus 19. As described above, in the present embodiment, when the microprocessor of the operating frequency of 33 MHz starts the write cycle to the ISA bus, the 8-bit I / O is executed.
In the standard cycle, a wait cycle for about 20 clocks is normally required, but the cycle is completed in about 4 clocks as shown in FIG. 4, so that the wait cycle for about 16 clocks is reduced. Embodiment 2 FIG. 2 is a block diagram showing a configuration of a second embodiment of the present invention. In the present embodiment, a write / read signal W / R5 and a memory / IO signal M which are control signals output from the microprocessor 1 by adding a latch circuit 24 to the first embodiment. / IO6 has two latch circuits and ISA bus 1
9 enables a continuous write cycle to be executed. Similarly, by increasing the number of stages of the latch circuit, more write cycles to the ISA bus 19 can be continuously executed. Although the present invention has been described based on the embodiment of the bus interface of the ISA bus, it is needless to say that the present invention is not limited to this bus.
The present invention includes the difference between the configuration of the microprocessor and the control signal of the bus used in the bus control device as long as the control signal has the same function as the present invention. In this embodiment, the bus control device is described as an integrated circuit separate from the microprocessor. However, the bus control device of the present invention may be integrated as a single-chip microcomputer on the same chip as the processor. As described above, according to the present invention, for example, when the operating frequency is 33
When a high-speed microprocessor of the MHz starts a write cycle to the ISA bus, an 8-bit I / O is transmitted by latching a write request signal to the bus and immediately transmitting a ready signal for canceling the wait to the microprocessor. In the standard cycle, where a wait cycle of about 20 clocks is normally required, the cycle is completed in about 4 clocks, and the wait cycle of about 16 clocks can be reduced. It is possible to eliminate the occurrence of idle cycles of the microprocessor, to make full use of the processing capability of the high-speed microprocessor, and to improve the processing performance of the entire system. Further, according to the present invention, a plurality of latch circuits for holding and outputting a control signal of a microprocessor are provided in multiple stages, thereby enabling a plurality of write requests to the bus to be continuously executed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a second exemplary embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of a conventional example. FIG. 4 is an operation timing chart of the first embodiment of the present invention. FIG. 5 is a circuit diagram showing an example of a ready control circuit according to the first embodiment of the present invention. [Description of Signs] 1 Microprocessor 2 Address bus 3 Data bus 4 Address strobe signal (ASTB) 5 Write / read signal (W / R) 6 Memory / IO signal (M / 10) 7 Ready signal (RDY) 8 Clock output signal (CLKOUT) 9 Address decoder 10 Address latch 11 Data latch 12 Bus controller 13, 15 Latch enable signal (LE) 14 Latch control circuit 16 Latch circuit 17 Ready control circuit 18 Synchronization circuit 19 ISA bus 20 Memory write signal (MWTC) 21 I / O write signal (IOWC) 22 Wait control signal (CHRDY) 23 Bus clock signal (BCLK) 24 Latch circuits 25 and 26 D-type latch circuit 27 Gate circuit 28 Inverter

Claims (1)

Claims: 1. A bus control device for controlling an interface between a microprocessor and a bus, comprising: a latch circuit to which a predetermined control signal including a write control signal output from the microprocessor is input; Before being latched by the latch circuit
A synchronization circuit that converts a write control signal into a bus control signal and outputs the control signal to the bus.
Path, a latch control circuit for inputting control signals such as the write control signal and address drive signal output from the microprocessor and outputting a latch enable signal to the latch circuit, and terminating bus control for the microprocessor. And a ready control circuit for outputting a ready signal for notifying the bus.When the microprocessor activates a write cycle for the bus, the latch control circuit activates the latch enable signal and sets the latch circuit to the predetermined state. And the ready control circuit latches the predetermined control signal to the latch circuit.
A bus control device, wherein the ready signal is activated immediately after being output as a bus control signal via the synchronization circuit . 2. The bus control device according to claim 1, wherein a plurality of said latch circuits are connected in cascade. 3. The bus control device according to claim 1, wherein the latch enable signal of the latch control circuit is input as a latch enable signal to a latch circuit for address output and a latch circuit for data output of the microprocessor.