JP2508911B2 - Automatic performance data editing device - Google Patents

Description

The present invention relates to an automatic performance data editing apparatus for editing automatic performance data and performing automatic performance based on the automatic performance data.

[Background Art] Electronic musical instruments having an automatic performance function are known. Further, an automatic performance data editing device for editing automatic performance data for controlling the performance of this kind of electronic musical instrument, or an electronic musical instrument having an automatic performance data editing function is known.

"Problems to be Solved by the Invention" There are cases where the sounding timing of each sound in an automatic performance is changed. In such a case, conventionally, the operation mode of the automatic performance data editing apparatus has been set to the edit mode, and the operation of inputting the changed value of the duration data related to the desired event data by the ten-key input or the like has been performed. Then, after changing the duration data, the operation mode is set to the automatic performance mode and the result of changing the sounding timing is confirmed. As described above, conventionally, since the tone generation timing is changed by inputting a numerical value, it is difficult to move the tone generation timing to a desired position. Also,
It is necessary to repeatedly change the sounding timing and check the result, which requires frequent mode switching, and there is a problem that the operation is troublesome.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide an automatic performance data editing apparatus capable of changing timing data representing the generation timing of event data while performing automatic performance.

"Means for Solving the Problem" The present invention relates to a storage means for storing automatic performance data including event data for performance control and timing data for designating timing of performance control by the event data, and the storage means for storing the automatic performance data. An operator for changing the timing of performance control, a timing operation means for generating timing change information for changing the timing of performance control according to the operation of the operator, and a readout for sequentially reading the event data according to the timing data. Means for changing the timing data according to the generation of the timing change information while the reading means is reading event data from the storage means, and writing the changed timing data in the storage means. Control means for controlling the performance control Thus it is characterized by comprising a tone generating means for generating a musical tone.

[Operation] According to the above configuration, the timing data representing the generation timing of the event data is changed by operating the operator, the changed timing data is written in the storage means, and the performance according to the changed timing is performed. Control is performed.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an automatic performance data editing apparatus according to an embodiment of the present invention. Further, FIG. 2 is a plan view showing an operation panel of the apparatus. This automatic performance data editing device has a rhythm pattern editing function and a function of automatically performing a performance based on the edited rhythm pattern.

In FIG. 1, reference numeral 1 is a CPU (central processing unit) for controlling the entire automatic performance data editing apparatus, and a bus B
The control data and the like are exchanged with each unit of the device via the. Reference numeral 2 is a timer, and the timer interrupt signal INT is sent to the CPU 1 at regular intervals.
Supply. Reference numeral 3 is a ROM (read-on memory) that stores various control programs executed by the CPU 1.

Reference numeral 4 is a RAM (random access memory), and each storage area thereof is used as a register or a flag for storing various control data. Further, a predetermined storage area in the RAM 4 is used as a rhythm pattern storage area for storing automatic performance data forming a rhythm pattern. A storage format in the rhythm pattern storage area is shown in FIG. As shown in this figure, the head address of the rhythm pattern storage area is a header area HD in which tempo data and the like in the rhythm pattern is stored. At each address after the header area, duration data DU1 designating the time length until the first rhythm sound is pronounced, event data IV1 instructing the pronunciation of the first rhythm sound, ... Event data and duration data for one pattern are sequentially and alternately stored, and then end data ED which means the end of the rhythm pattern is stored.

Reference numeral 5 is a wheel rotatably provided on the operation panel surface (see FIG. 2), and 6 is a wheel detection circuit, which detects the operation of the wheel 5 and outputs digital data (hereinafter, wheel value) corresponding to the rotation amount. Is output). The automatic performance data editing device according to the present embodiment generates a rhythm sound based on the automatic performance data stored in the RAM 4, and has a function of editing the automatic performance data in which the sounding timing of the desired rhythm sound is moved (hereinafter, It is called the move clock function.)
Have. When the wheel 5 is operated while the mode is set to the move clock function, the sounding timing of the rhythm sound to be generated immediately after that is moved back and forth according to the amount of rotation of the wheel 5.

More specifically, the movement of the sounding timing of the rhythm sound in this embodiment is performed as follows. FIG. 4 illustrates a case where the sounding timing of the desired rhythm sound R ₃ is delayed, and VF represents a period during which the wheel 5 is rotated. As shown in this figure, the user confirms the sound of a rhythm sound R ₀ before the rhythm sound R _3, rotate the wheel 5 in the forward direction before scheduled time rhythm sounds R ₃ is pronounced. This rotation is performed at least until the scheduled sounding time after the change of the rhythm sound R ₃ has passed. As a result, depending on the amount of rotation of the wheel 5, is changed duration data relating to pronounce rhythm sounds R ₃ is, the rhythm sound R ₃ is pronounced at the timing indicated by the example code R _5. Further, FIG. 5 explains a case where the sounding timing of the desired rhythm sound R ₃ is advanced, and VR indicates a period in which the wheel 5 is rotated. Also in this case, the user confirms the pronunciation of the rhythm sound R ₀ and rotates the wheel 5 in the negative direction before the scheduled sounding time after the change of the rhythm sound R ₃ . This rotation is performed at least until the scheduled sounding time before the change of the rhythm sound R ₃ has passed. As a result, depending on the amount of rotation of the wheel 5, is changed duration data relating to pronounce rhythm sounds R ₃ is, the rhythm sound R ₃ is pronounced at the timing shown by the example code R _2.

In FIG. 1, reference numeral 7 denotes each instrument key arranged on the operation panel surface (see FIG. 2). These instrument keys 7, 7, ... Are provided to specify the tone color of the rhythm sound, and the instrument name is displayed on each key. Further, when any one of the instrument keys 7, 7, ... Is pressed, the key detection circuit 8 detects the pressing operation, the tone color designation data corresponding to the pressed key is output, and the CPU 1 via the bus B Is taken into.

Reference numeral 9 denotes a switch detection circuit, which is a key switch other than the instrument keys 7, 7, ... In FIG. 2, for example, a play key 21, a record key 22, a start key 23, a stop key.
24, the operation state of the move clock key 25, etc. is detected and the operation data is sent to the CPU 1. Reference numeral 10 is a display, and 11 is a driver circuit for driving the display 10 based on display data supplied from the CPU 1. Reference numeral 12 is a tone generator circuit for forming rhythm sounds of various tones, and 13 is a sound system for producing the rhythm sounds formed by the tone generator circuit 12.

The operation of this embodiment will be described below. When the power (not shown) of this automatic performance data editing apparatus is turned on, the CPU 1 starts the processing of the main routine whose flow is shown in FIG. First, in step S1, initialization processing is performed. As a result, the initial values are written in the control registers and flags set in the RAM4. For example, a time register for managing the passage of time by initialization processing.
The initial value "0" is written in the TIME and previous time register OT. In addition, the move clock flag MOVE for instructing the move clock function is set to "0". Next, in step S2, instrument key processing is performed, that is, scanning of the output of the key detection circuit 8 and acquisition of operation data when the operation data of the instrument key is output from the key detection circuit 8.

Next, in step S3, pattern creation processing is performed.
In this pattern creation process, if the operation mode is the record mode and the operation data of the instrument key 7 is fetched in step S2, the operation data is RA and the operation interval is the event data.
Write to the rhythm pattern storage area of M4. In the record mode, the user selects the record switch shown in FIG.
After pressing 22, the setting is made when the start switch 23 is pressed, and the setting is released when the stop switch 24 is pressed.

Next, in step S5, the move clock processing routine whose flow is shown in FIG. 8 is started, and the process proceeds to step S11. Then, the switch detection circuit 9 is scanned to capture the operation state of the move clock switch 25, and it is determined whether or not the switch is switched from the off state to the on state. If the move clock switch 25 is not operated and its state does not change, the determination result in step S11 is "NO", the flow proceeds to step S15, and the move clock flag MOVE is set.
Determines whether is "1". Here, the move clock flag MOVE has been initialized to "0" by the initialization processing in step S1 of the main routine, and the determination result in this case becomes "NO", and the process returns to the main routine.
Proceed to step S5.

In step S5, pattern play processing is performed. That is, when the operation mode at that time is the pattern play mode, the sound source circuit 12 is instructed to sound based on the automatic performance data in the rhythm pattern storage area of the RAM 4. In addition,
The pattern play mode is set when the user presses the start switch 23 after pressing the play switch 21 in FIG. 2, and is released when the stop switch 24 is pressed. Then step S6
Then, other processing such as various controls according to operation data of an operator such as a volume is performed. And after that,
Repeat steps S2 to S6.

FIG. 9 shows the operating state of the CPU 1. In this figure, each arrow indicated by the symbol M indicates the timing at which step S2 of the main routine is executed. The main routine and the move clock processing routine and the like that are activated in association with the main routine include steps for performing conditional branching, and the cycle in which the main routine is executed is not necessarily constant. Therefore, for example, even if a method is adopted in which a count process for timing is provided in a specific step in the main routine, the count value is not generated in a constant cycle, and thus the count value is generated as duration data. Or it cannot be used to control the sounding timing according to the duration data. Therefore, in the present embodiment, when the timer interrupt signal INT is generated at regular intervals T, the CPU 1 executes the timer interrupt routine shown in FIG. 7 to increment the timer count register TC, and the timer count register TC The contents are referred to in the move clock processing routine and used as information indicating the passage of time.

Now, it is assumed that the move clock switch 25 has been turned on by the user. In this case, when the move clock processing routine is started through step S4 of the main routine, the determination result of step S11 is "YES".
Then, the process proceeds to step S12, and the move flag MOVE is set to "1".
Set. Next, in step S13, the start address of the rhythm pattern, that is, the storage address of the duration data DU1 in FIG. 3 is set in the address register ADR that specifies the read / write address of RAM4. Next, in step S14, the timer count register TC is cleared and its contents are set to "0".
Since the content of the move flag MOVE is "1", the determination result of step S15 is "YES" and the process proceeds to step S16.

Then, it is determined whether the content of the timer count register TC is "1" or more. After execution of step S14,
If the timer interrupt routine was desired to be started even once, TC = "0"
The determination result in S16 is "NO", and the process returns to the main routine via step S17.

On the other hand, when the timer interrupt routine is activated after the execution of step S14, the content of the timer count register TC is incremented by the number corresponding to the number of activations. Then, when the move clock processing routine is activated and the process proceeds to step S16, the determination result of step S16 becomes "YES", and the process proceeds to step S19. Then, the content of the timer count register TC is decremented by "1". In this way, each time the content of the timer count register TC becomes "1" or more by the activation of the timer interrupt routine, step S19 and subsequent steps are executed and the timer count register TC is decremented.

Next, when proceeding to step S20, the duration data is read from the RAM 4 based on the designation of the address register ADR. In this case, the first duration data DU1 is read. Then, the duration data DU1 is stored in the duration register DUR. Next, in step S21, the output of the wheel detection circuit 6 is scanned, and the wheel value obtained by scanning is loaded into the wheel value register WH. Here, when the user rotates the wheel 5 in the negative direction in order to accelerate the sounding timing of the rhythm sound, a negative value corresponding to the rotation amount is fetched in the wheel value register WH,
When the wheel 5 is rotated in the positive direction in order to delay the sounding timing, a positive value corresponding to the amount of rotation is loaded into the wheel value register WH. If the user does not rotate the wheel 5, "0" is displayed in the wheel value register WH.
Is taken into.

Next, in step S22, it is determined whether the content of the wheel value register WH is other than "0". If the user does not operate the wheel 5, the result of the determination in step S22 is "NO", and the process proceeds to step S23. Then, it is determined whether or not the content of the time register TIME is equal to or more than the sum of the content of the duration register DUR and the content of the previous time register OT, that is, whether or not it is time to produce a rhythm sound. If the result of this determination is "NO", then step S24.
In step S17, the content of the time register TIME is incremented by 1, and the process returns to the main routine via step S17. When the move clock processing routine is started again through step S4 of the main routine and the process proceeds to step S16, if the content of the timer count register TC is "1" or more, the process proceeds to step S19 and the timer count register TC.
Is incremented and the process proceeds to step S20. Then, the data is read from the RAM 4 according to the address register ADR, and the read data is stored in the duration register DUR. In this case, the contents of address register ADR are
It has the same value as the previous step S20 was executed,
Duration data DU1 is the duration register DUR
Stored in. Then, through step S21, step S
If the wheel 5 is not operated in step 22, the determination result in step S22 becomes "NO", and the process proceeds to step S23.
After that, the same processing as described above is repeated until the content of the time register TIME reaches the sum of the content of the duration register DUR and the content of the previous time register OT.

When the move clock processing routine is started again and the process proceeds to step S23, the determination result is "YE
S ”, the process proceeds to step S25 and the address register AD
Increment the contents of R. As a result, the content of the address register ADR becomes the storage address of the event data IV1 shown in FIG. Next, proceeding to step S26, the storage data at the address specified by the address register ADR in RAM3, that is, the event data IV1 is read. Next, in step S27, it is determined whether or not the data read in step S26 is end data. If the result of this determination is "NO", the flow proceeds to step S28 and the relevant event data, that is, event data IV
1 is output to the tone generator circuit 12. As a result, event data I
A rhythm sound according to V1 is generated from the sound system 13. Then, in step S29, the contents of the time register TIME are set in the previous time register OT. Then, in step S30, the content of the address register ADR is incremented. As a result, the contents of the address register ADR are
It becomes the storage address of the duration data DU2 in FIG. Next, in step S31, the time register TIM
Increment E and return to the main routine via step S17.

Thus, if the timer count register TC is "1" or more, the process proceeds to step S19 and subsequent steps, and the timer count register TC is decremented (step S1.
9) and the time register TIME is incremented (steps S31, S24 and steps S44, S3 described later).
3). As a result of such processing, the time register TIM
E increases in accordance with the increment of the register TC due to the timer interrupt, and the value of the time register TIME increases almost in proportion to the elapsed time.

Now, it is assumed that the user has operated the wheel 5. As a result, when the process proceeds to step S22 of the move clock processing routine, the result of the determination is "YES" and the process proceeds to step S32. Then, it is determined whether or not the content of the time register TIME is greater than or equal to the sum of the content of the duration register DUR, the content of the previous time register OT, and the content of the wheel value register WH. Here, if the user rotates the wheel 5 in the negative direction, it is compared with the time register TIME DUR + WH
+ OT is a value when the wheel 5 is not rotated, that is, a value smaller than DUR + OT by an amount corresponding to the rotation amount. When the user rotates the wheel 5 in the forward direction, DUR + WH + OT is larger than DUR + OT by an amount corresponding to the rotation amount.

If the time indicated by the time register TIME has not reached the time at which the rhythm sound should be produced and the judgment result in step S32 is "NO", the process proceeds to step S33.
E is incremented and the process returns to the main routine via step S17. On the other hand, the time indicated by the time register TIME has reached the time at which the rhythm sound should be generated, and the step S32
When the result of the determination is “YES”, the process proceeds to step S34 and the address register ADR is incremented. As a result, the content of the address register ADR becomes the storage address of the event data IV2 in FIG. Next, in step S35, according to the specification of the address register ADR,
Read event data IV2 from RAM4. Then, in step S36, it is determined whether the read data is end data. When the read data is not the end data, the determination result of step S36 becomes "NO", and the process proceeds to step S37 to output the event data, that is, the event data IV2, to the tone generator circuit 12. As a result, the rhythm sound according to the event data IV2 is generated by the sound system 13
Pronounced from. Then, in step S38, the contents of the time register TIME are set in the previous time register OT. Then, in step S39, the contents of the address register ADR are decremented. As a result, the address register ADR
Is the storage address of the duration data DU2 that specifies the duration value of the event data IV2. Next, in step S40, the contents of the duration register DUR and the contents of the wheel value register WH are added, and the value is decreased from the original value according to the addition result, that is, the turning amount of the wheel 5 (when turning in the negative direction). ) Or an increased (when rotated in the normal direction) duration value is written to RAM4 as duration data DU2. In this way, the sounding timing of the rhythm sound corresponding to the event data IV2 is moved. Next, in step S41, the content of the address register ADR is incremented by 2 to obtain the storage address of the duration data DU3. Then, the duration data DU3 is read according to the designation of the address register ADR, and is taken into the duration register DUR. Then the duration register DUR
The content of the wheel value register WH is subtracted from the content of and the result of the subtraction is written in the RAM4 as the duration data DU3 corresponding to the event data IV3. Since the duration data DU3 is changed so as to cancel the change in the duration data DU2, only the sounding timing corresponding to the event data IV2 is changed, and the sounding timing of each event data after the event data IV3 is not changed. Then, in step S44, the time register T
The IME is incremented and the process returns to the main routine via step S17.

Similarly, when the rhythm performance is performed according to the automatic performance data in the RAM 4 and the wheel 5 is operated, the duration data related to the event data immediately after that is changed. Then, the move clock processing routine is started while the user is not operating the wheel 5, and when the end data ED (see FIG. 2) is read in step S26, the determination result in step S27 becomes “YES”, and the step Proceed to S47 to set "0" in the time register TIME. Next, the procedure proceeds to step S48, where the content of the address register ADR is used as the start address, that is, the storage address of the duration data DU1, and the procedure returns to the main routine via step S17. Also, the end data was read while the user was operating the wheel 5 (step S35).
The case is exactly the same, the time register TIME is cleared (step S45), the start address is set in the address register ADR (step S46), and the process returns to the main routine via step S17). In this manner, the processing for one rhythm pattern is performed, thereafter, the automatic performance of the same rhythm pattern as described above is repeated, and when the wheel 5 is operated, the processing for changing the duration data is performed accordingly.

When finishing changing the duration data, the user presses the stop key 24. If the move clock processing routine is started after this pressing, the determination result is “YES” when the process proceeds to step S17, the process proceeds to step S18, the move flag MOVE is set to “0”, and the process returns to the main routine. . After that, when the move clock processing routine is started, the determination result of step S15 is "NO", and the process returns to the main routine without proceeding to step S19 and thereafter.

In the embodiment described above, the case where the sounding timing of the rhythm pattern is moved has been described as an example.
Needless to say, it can be applied to the movement of the tone generation timing in the normal automatic performance data. Further, in the above embodiment, all the duration data of the rhythm pattern stored in the RAM 4 is targeted for modification, but a means for designating the tone color is provided and only the duration data of the event data corresponding to the designated tone color is modified. Doing so will make it even more convenient. Further, a means for designating a tone color in this case may be realized by, for example, an instrument key so that the tone color for which the duration data can be changed can be changed in real time. Further, the duration data changing process is not limited to the flow of the above embodiment. For example, in the above embodiment, the time register TIME is incremented by monitoring the value of the timer count register TC in the move clock processing routine, but the time register TIME is incremented only within the timer interrupt routine. The time may be managed using only the time register TIME. Further, the manipulator for instructing the movement of the sound generation timing is not limited to the wheel, and various manipulators such as a switch and a joystick can be used.

[Advantages of the Invention] As described above, according to the present invention, the generation timing data of the event data can be changed while performing the automatic performance, and the automatic performance data can be edited very easily.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an automatic performance data editing apparatus according to an embodiment of the present invention, FIG. 2 is a plan view showing an operation panel in the same embodiment, and FIG. 3 is a view showing automatic performance data in the same embodiment. FIG. 4 shows a storage format, FIG. 4 and FIG. 5 are views for explaining movement of sounding timing of a rhythm sound by rotation of the wheel 5 in the same embodiment, and FIGS. 6 to 8 show operations of the same embodiment. Flowchart to explain,
FIG. 9 is a diagram showing the relationship between the start timing of the main routine and the timing of timer interrupt in the same embodiment. 5 …… Wheel, 6 …… Wheel detection circuit, 4 …… RA
M, 1 ... CPU, 2 ... Timer, 12 ... Sound source circuit.

Claims (1)

(57) [Claims] 1. Storage means for storing automatic performance data comprising event data for performance control and timing data for designating timing of performance control by the event data, and for changing performance control timing by the event data. Operator, timing operation means for generating timing change information for changing the timing of performance control according to the operation of the operator, read means for sequentially reading the event data according to the timing data, and the read means. Control means for controlling the timing data to be changed and writing the changed timing data to the storage means in response to the occurrence of the timing change information while the event data is being read from the storage means; Musical tone generation that generates musical tone by control Automatic performance data editing apparatus characterized by and means.