JP2508075B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a technique for capturing an image of a moving object or the like and recognizing the image, and in particular, the present invention sets a predetermined window on the image. In addition, the present invention relates to an image processing device for sequentially processing the data of each pixel included in this window.

<Prior Art> FIG. 9 shows this kind of conventional image processing, and includes an image memory 31, a window memory 32, an address generator 33,
It is composed of a data processor 34, a CPU circuit 35, and the like. The image memory 31 is a part for storing an image of an object imaged by the television camera 36, and the video signal thereof is given from the A / D converter 37. The window memory 32 is a portion for storing a window to be set on the image, and each pixel of the window memory 32 corresponds to each pixel of the image memory 31 in a 1: 1 relationship. Each pixel of the window memory 32 has a 1-bit configuration. If the pixel is "1", the data of the corresponding pixel of the image memory 31 is the data processor 34.
However, if the pixel is “0”, it is not processed.

Therefore, if the window is preset in the window memory 32 by the CPU circuit 35 and then the image memory 31 and the window memory 32 are accessed by the address generator 33 over all addresses, the data processor 34 processes the data only for the pixels included in the window. Will be executed.

According to the apparatus example having the above configuration, for example, when a still object is imaged and the image is always located within a certain range on the image memory, it is effective.

However, when a moving object is imaged and the image cannot be positioned within a certain range on the image memory, the setting position of the window cannot be fixed and the window needs to be moved at high speed.

FIG. 10 shows an attention range 39 for the image portion 38 on the image plane 31.

Now, the rectangular window 40 is located at a position away from the current position of the image portion 38. This window 40
Therefore, in order to perform the image processing of the attention range 39, the window 40 is moved while moving in the direction indicated by the arrow in the figure.
The data processing inside will be repeated.

<Problems to be Solved by the Invention> However, in the case of the conventional apparatus example shown in FIG. 9, the window setting for the window memory 32 is 1 for all pixels.
Since it is necessary to perform pixel by pixel, there is a drawback that it takes time to set the window. Moreover, since it is necessary to access all the pixels outside the window in order to perform the data processing for each pixel included in the window, it is said that the data processing time is long particularly when performing the data processing while moving the window 40. There's a problem.

The present invention has been made in view of the above problems, and reduces the amount of data required for window setting and makes it possible to access only the pixels within the window to reduce the time required for window setting and data processing. It is an object of the present invention to provide a novel image processing device in which the above is shortened.

<Means for Solving Problems> In order to achieve the above object, in the present invention, an image storage unit for storing an image, a window setting unit for setting a predetermined window on the stored image while moving the window, and a window An image processing device is configured with a data processing unit that processes data of each pixel included in the image processing device.

The window setting unit sequentially outputs the address of each pixel in the window from the window shape memory circuit that stores the shape data for defining the shape of the window and the shape data and the position data for specifying the window position. A window address generation circuit that generates address data for designating, and a timing circuit that operates the window address generation circuit and the data processing unit at predetermined timing to sequentially perform predetermined data processing for each pixel in the window. And is equipped with.

<Operation> When the input image is stored in the image storage unit, the window setting unit sets a predetermined window on the image while moving the window, and the data processing unit sets the data of each pixel included in the window. Process it.

In this case, the shape data for defining the shape of the window is stored in the window shape memory circuit of the window setting unit in advance, and this shape data and the position data for specifying the window position are set in the window when setting the window. It is given to the address generation circuit. Then, the window address generation circuit generates address data for sequentially designating the address of each pixel in the window from each of these data. The timing circuit operates the window address generation circuit and the data processing section at a predetermined timing, so that the data processing section sequentially processes only the pixels in the addressed window.

According to the present invention, since the window is set on the image while moving the window based on the position data and the shape data, the amount of data required for the window setting is small and the window setting time is shortened. Further, since the window address generation circuit accesses only the pixels within the window, the data processing time is short and the data processing speed is high.

<Embodiment> FIG. 1 shows an image processing apparatus 1 according to an embodiment of the present invention.
1 shows a schematic configuration of the embodiment. The device shown in FIG.
Window address generation circuit 3, window shape memory circuit
4, a timing generator 5, a data processor 6, a CPU circuit 7, etc., and an image pickup system including a television camera 8 and an A / D converter 9 is connected to the image memory 2.

The television camera 8 images a moving object and outputs the video signal to the A / D converter 9. The A / D converter 9 converts this video signal into a digital signal and supplies it to the image memory 2.

The image memory 2 is for storing this input image. A window of a predetermined shape is set for this stored image, and each pixel data in the window is processed by the data processor 6. The window address generation circuit 3, the window shape memory circuit 4, the timing generator 5, and the CPU circuit 7 are involved in the window setting, and the CPU circuit 7 defines the window shape for the window shape memory circuit 4. And the position data for designating the window position to the window address generation circuit 3.

The window shape storage circuit 4 stores the shape data, and the window address generation circuit 3 generates address data for sequentially designating addresses of pixels included in the window from the shape data and the position data. It is given to the image memory 2.

When the timing generator 5 receives the start signal from the CPU circuit 7, it operates the window shape memory circuit 4, the window address generation circuit 3, and the data processor 6 at a predetermined timing. As a result, the data processor 6
Takes in the data of each pixel associated with the specified address from the image memory 2 and processes them sequentially.

 FIG. 2 shows an operation procedure of the apparatus example of FIG.

When the television camera 8 captures an image of a moving object or the like at the start point in the figure, the video signal is given to the A / D converter 9 and converted from analog to digital. This digital signal is given to the image memory 2 in step 1 (indicated by "ST1" in the figure), and this input image is stored in the image memory 2.

In the next step 2, the CPU circuit 7 gives shape data to the window shape storage circuit 4 to store the shape of the window, and also gives position data to the window address generation circuit 3 to specify the window position. Then in step 3
When the CPU circuit 7 outputs a start signal to the timing generator 5, the timing generator 5 operates the window address generation circuit 3 and the data processor 6 at a predetermined timing. That is, the window address generation circuit 3 generates address data for designating the address of the pixel included in the window, and the data processor 6 fetches the pixel data in the window of the image memory 2 corresponding to the address to obtain predetermined data. The process is executed (step 4).

When all the pixels in the window are similarly accessed and the data processing is completed, the determination in step 5 becomes “YES”,
The data processor 6 displays the data processing result in the window
Output to the CPU circuit 7 (step 6). Based on the data processing result, the CPU circuit 7 determines whether or not the window corresponds to the focused area of the image. If the window does not correspond to the range of interest, the determination at step 7 is "NO" and the process proceeds to step 8, and the CPU circuit 7 obtains the next position data for moving this window along a predetermined route. Output to the window address generation circuit 3.

Thereafter, the same procedure from step 3 onward is repeatedly executed, and when the result of the determination in step 7 is “YES”, the process proceeds to step 9, where the CPU circuit 7 performs a predetermined recognition process based on the data processing result by the data processor 6. Execute and output the recognition result to the outside.

FIG. 3 shows a situation where the rectangular window 11 moves on the image plane 10 along a predetermined route. In the figure,
dX and dY are shape data for defining the shape of the window 11 (in this case, the width of the window 11 in the X and Y directions)
And (x ₀ , y ₀ ) (x ₁ , y ₁ ) ・ ・ ・ ・ (x _i , y _i ) ・ ・ ・
(X _n-1 , y _n-1 ) is position data (in this case, the coordinates of the upper left corner of the window 11) for specifying the position of the window 11. Also, W ₀ , W ₁ , ..., W _i , ..., W _n-1 indicate the respective positions of the window 11 when the position data is given, and the window 11 is set in this route. By moving, the attention range 12 of the image is searched.

FIG. 4 shows this search procedure. First, step 11
After initializing i to zero with, the next step 12 is the cumulative value of the brightness in the window 11 at the first window position W ₀ . Is required. Cumulative value of this brightness Is for determining whether the attention area 12 of the image is located within the window 11. The next step 13 is i
Has reached the final value n. In this case, since the determination is "NO", the routine proceeds to step 14, where the cumulative value It is determined whether the value is larger than the threshold value C. If the determination in step 14 is "YES", it is determined that the attention area 12 of the image is located in the window 11, but if the step
When the judgment in 14 is "NO", i is incremented by 1 and the window 11
To the next position W ₁ (step 15), and the cumulative value of the brightness in the window 11 at that position Will be required.

The same procedure is repeated until the determination in step 13 or 14 becomes “YES”, but if the determination in step 14 is “YE
When the determination in step 13 is “YES” without becoming “S”, it is determined that the attention range 12 does not exist on the image plane 10.

Fig. 5 shows the cumulative value in step 12 above. 2 shows an example of a circuit configuration used to calculate the image data, and includes an image memory 2, a window address generation circuit 3, a window shape memory circuit 4, a timing generator 5, and a data processor 6. The window address generation circuit 3
It is composed of an X position register 15, a Y position register 16, an X address counter 17, and a Y address counter 18. The X position register 15 and the Y position register 16 have position data (x _i , y _i) for designating a window position. ) Is set. Further, the window shape memory circuit 4 has an X width register 19, Y
Width register 20, X comparator 21, Y comparator 22, X width counter 23, Y width counter 24
The shape data dX and dY for defining the window shape are set in the 19 and Y width register 20. The operation of these circuits is controlled by a CPU circuit (not shown).

FIG. 6 shows a timing chart of the above circuit, and the circuit operation of FIG. 5 will be described in detail below with reference to FIG.

First, the CPU circuit outputs latch pulses d _i , d to the X width register 19 and the Y width register 20 of the window shape memory circuit 4.
_By appropriately supplying _j , the window shape data dX and dY are stored in the registers 19 and 20 through the data bus 25.
Similarly, latch pulses i _w , j _w are applied to the X position register 15 and the Y position register 16 of the window address generation circuit 3.
Sets the window position data x _i , y _i . In order to simplify the description, the following circuit operation will be described assuming that the position data dX and dY are dX = 2 and dY = 2.

Next, the CPU circuit applies the start signal SGM to the timing generator 5 to activate this circuit. First in State 1 X
Position data x _i , y _i are loaded as initial values into the address counter 17 and Y address counter 18, and “1” is loaded into the X width counter 23 and Y width counter 24, respectively. Therefore, the setup output SP _i SP _j of the timing generator 5 becomes “0”, and the increment pulse CP _i CP _j rises. In the window address generation circuit 3, the position data x _i , y _i loaded in the X address counter 17 and the Y address counter 18 are given to the image memory 2 as address data. In the window shape memory circuit 4, the X comparator 21 compares the content A of the X width register 19 (A = 2 in this case) with the content B of the X width counter 23 (B = 1 in this case), and the Y comparator. 22 is the content A'of the Y width register 20 (in this case A '
= 2) and the size of the Y width counter are compared. As a result, A> B,
Since A '>B', the comparison signals of the comparators 21 and 22
AG _i AG _j is “0”.

In the states 2 to 4, the respective output signals of the timing generator 5 do not change, and the image memory 2 is accessed during that time and the pixel data Y (x _i , y _i ) is entered into the data processor 6.
Is confirmed. If the comparison signals AG _i AG _j are both "1" in state 3, the state shifts to state 12, but in this case both are "0", the state shifts to state 4.

In state 5, the X address counter 17 is incremented and the contents of the Y address counter 18 are retained. That is, the X address counter 17 gives x _i +1 as the address data and the Y address counter 18 gives y _i as the address data to the image memory 2.
Further, the X width counter 23 is incremented to "2", and the contents of the Y width counter 24 are retained. Therefore, the timing generator 5 outputs the setup output.
SP _i SP _j becomes “1” and increment pulse CP _i
Rises and the increment pulse CP _j remains “0”. Furthermore, at the beginning of state 5, the data input signal IN
When D rises, the pixel data Y (x _i , y _i ) is loaded into the data processor 6.

In the states 6 to 8, the output signals of the timing generator 5 do not change, and the image memory 2 is accessed during that time to enter the pixel data Y (x _i +1,
y _i ) is fixed. Since the content B of the X width counter 23 is "2" and the content A of the X width register 19 is "2",
The comparison signal AG _i applied to A> B of the X comparator 21 is “1”, but the content B ′ of the Y width counter 24 is “1”,
Since the content A'of the Y width register 20 is "2", A '>
The comparison signal AG _{j related} to B ′ remains “0”, and the state 7 shifts to the state 8.

In state 9, the initial value x _i is loaded into the X address counter 17, and the content of the Y address counter 18 is incremented to y _i +1. That is, the X address counter 17 uses x _i as the address data, and the Y address counter 18
Gives y _i +1 as the address data to the image memory 2, respectively. Further, "1" is loaded into the X width counter 23, and the content of the Y width counter 24 is incremented to "2". Therefore, the setup output SP _i of the timing generator 5 becomes “0”, the setup output SP _j becomes “1”, and the increment pulses CP _i and CP _j both rise. Furthermore, at the beginning of state 9, the data input signal IND
Rises, the pixel data Y (x _i +1, y _i )
Is added to the contents of the data processor 6.

In the next states 10 and 11, since the content B'of the Y width counter 24 becomes "2", A '> of the Y comparator 22>
The comparison signal AG _j applied to B ′ becomes “1”, and the setup output SP _j of the timing generator 5 becomes “0”. On the other hand, the comparison signal for A> B of the X comparator 21
AG _i becomes “1”. If in state 11 the comparison signal AG _i
If both AG _j are "1", the state shifts to the state 12, but since the comparison signal AG _i is "0" in this case, the state returns to the state 8.

Next, in state 9, the X address counter 17 displays x _i +1
The contents of the Y address counter 18 are incremented to
held at y _i +1. That is, the X address counter 17 gives x _i +1 as the address data and the Y address counter 18 gives y _i +1 as the address data to the image memory 2. Further, the X width counter 23 is incremented to "2", and the content of the Y width counter 24 is held at "2". Therefore, the setup output SP _i of the timing generator 5 becomes “1”, the increment pulse CP _i rises, and the increment pulse CP _j remains “0”. By data input signal IND rises further the beginning of a state 9, established pixel data _{Y (x i + 1, y} i +1) is added to the contents of the data processor 6.

In the states 10 and 11, the X width counter 23 and the Y width counter 24 both become "2", and the X comparator 21 and the Y comparator
The comparison signal AG _i AG _j of the comparator 22 becomes “1”. The comparison signal AG _i in state 11, since AG _j are both "1", the process proceeds to state 12, in the state 12 pixel data _{Y (x i + 1, y} i +1) is determined. By state 13, the data input signal IND rises, the final pixel data _{Y (x i + 1, y} i +1) is added to the contents of the data processor 6.

In state 14, the output signal of timing generator 5 does not change, and in state 15, the end signal END is output to the CPU circuit and the accumulated value Notify the end of the calculation process of. After receiving the end signal END, the CPU circuit accesses the data processor 6 to calculate the accumulated value. Can be requested.

In the above embodiment, the window shape is a rectangular shape of dX = dY = 2, but the present invention is not limited to this, and the window 11 having an arbitrary shape as shown in FIG. 7 can be applied and implemented. In the figure, of the shape data dX and dY, the width dX of the window 11 in the X direction is represented as a function dX (Y _i ) determined by the Y width position Y _i of the window. In this case, as shown in FIG. 8, the shape data dX and dY are set in advance in the X width register 19 and the Y width register 20, and the X width register 19 is set.
Is given the contents of the Y width counter 24 and the corresponding shape data
It is configured to take out dX.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a flowchart showing an operation procedure of the apparatus example of FIG. 1, and FIG. 3 is a window on an image plane. FIG. 4 is a flow chart showing a procedure for searching a range of interest by a window, FIG. 5 is a block diagram showing a concrete circuit configuration example of the present invention, and FIG. 6 is a circuit shown in FIG. Is a timing chart showing the operation of FIG. 7, FIG. 7 is an explanatory view showing another example of the shape of the window,
FIG. 8 is a block diagram showing an example of the circuit configuration for the window shape of FIG. 7, FIG. 9 is a block diagram showing an example of a conventional device, and FIG. 10 is an explanation showing a method of searching a range of interest by the example of a conventional device. It is a figure. 1 ... Image processing device, 2 ... Image memory 3 ... Window address generation circuit 4 ... Window shape memory circuit 5 ... Timing generator 7 ... CPU circuit

Claims (1)

(57) [Claims] 1. An image storage unit for storing an image, a window setting unit for setting a predetermined window while moving the stored image on the stored image, and a data processing unit for processing data of each pixel included in the window. In the image processing device, the window setting unit includes a window shape storage circuit that stores shape data for defining a shape of the window, and the shape data and position data for designating a window position within the window. Of the window address generating circuit for generating address data for sequentially designating the address of each pixel, and the window address generating circuit and the data processing section are operated at a predetermined timing to obtain predetermined data for each pixel in the window. An image processing apparatus comprising a timing circuit for sequentially executing processing.