JP2506907B2 - Figure connection verification system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic connection verification system for ensuring the validity of output data of an automatic layout system such as a VLSI or a printed circuit board.

2. Description of the Related Art Conventionally, there have been many reports on graphic connection verification such as VLSI layout, and there are also many efficient methods (Terao et al .: IEICE Tech., CAS-86-204, pp.9-15, N. , Miyahara.e
t al .; Proceeding of ISCS Conf., pp.114-117,1
981).

However, since these are all methods for polygonal figure data, in order to handle the data of the output result of the automatic layout, OR processing (Tsukuzoe et al., The Institute of Electronics, Communication and Information Engineers, Vol.J68- D, No6, pp, 1334-1351).

Problems to be Solved by the Invention Output data of an automatic layout system such as a VLSI or a printed circuit board has the following features.

(1) All wiring and contacts are rectangular.

(2) Potential numbers and layers are given as attributes to wirings and contacts.

Here, the potential number is represented by a number for each terminal, wiring, and contact that always changes at the same potential (potential). If the numbers are the same, they are connected at the same potential, and if they are different numbers, they are different. Insulated by electric potential.

For example, a terminal has a potential number of 1, a wire has a potential of 1,
If the contact is given as 1, it means that they are at the same potential, and if the contact is given, it is different from the above potential number 1 and therefore is insulated.

(3) A terminal specific name and a layer are given to the terminal as attributes.

Here, a terminal represents a point for accessing the outside in a functional block or a logic cell.

It is an object of the present invention to efficiently verify output data of an automatic layout system such as a VLSI or a printed circuit board having the above three characteristics.

Means for Solving the Problems The present invention provides a connection description in which a unique name (hereinafter, net name) is given to a set of a plurality of terminals connected to each other, and a set of rectangles having layers and potential numbers as attributes. , Inputting layout pattern information consisting of a layer and a set of terminals having a terminal specific name as an attribute, and comparing the connection information obtained from the connection description with the connection information obtained from the layout pattern information, A graphic connection verification system for verifying the legitimacy of layout pattern information, which extracts a rectangle connected to each terminal included in the layout pattern information, and gives a potential number of the rectangle to each terminal. A means for classifying a plurality of terminals and a set of rectangles included in the layout pattern information for each potential number; In each set of terminals and rectangles that are classified according to their numerical numbers, a unit that determines that the terminals and rectangles are connected to each other, and that each terminal obtained from the layout information has the same terminal unique name as this. A means for giving a net name of a terminal obtained from the connection description, and in each set of terminals and rectangles classified by the potential number, the same net name is given to all the terminals included in the same set. And the arbitrary two terminals to which the same proper name net name is assigned,
The present invention provides a graphic connection verification system, characterized in that it is provided with a means for determining that they are included in the same set of potential numbers.

Effect According to the present invention, it is possible to efficiently verify the graphic connection to the output graphic data of the automatic layout system such as the VLSI or the printed circuit board.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1 is a connection information input means, 2 is an automatic layout system, 3 is a rectangle and terminal input means, 4 is a terminal rectangle connection search means, 5 is a potential number classification means, 6 is a connection classification determination means, and 7 is Terminal unique name matching means, 8 is a terminal unique name classification means, 9 is a unique name matching determination means, 10 is a potential number matching determination means, and 11 is error data output means.

The operation of the graphic connection verification system of the present embodiment configured as described above will be described below.

The connection information inputting means 1 transfers to the automatic layout system 2 a connection description in which a unique name (net name) is given to a set of a plurality of terminals which are connected to each other and have the same potential.

In the automatic layout system 2, a layout pattern represented by all rectangular figures is created based on the passed connection description, and each rectangle has a layer including it and a potential number as attributes, and each terminal has Has as attributes the layer in which it is included and the pin-specific name. The unique pin name is a unique name for each pin, and the pin name is the name given to each block.Therefore, the pin names may be the same, but even if the pin names are the same, the pin name is unique. Is always different.

These data are passed to the figure connection verification system by the rectangle and terminal input means 3.

Next, the terminal rectangle connection search means 4 finds a rectangle connected to the terminal, and gives each terminal a potential number of the rectangle connected to it.

Next, the rectangle and the terminal are divided by the potential number classification means 5 into a set for each potential number.

Next, for the set of rectangles and terminals of each potential number, the connection classification determination means 6 determines whether or not the rectangles and terminals are connected to the same potential. If the same condition is not satisfied, it is not satisfied. The rectangles and terminals included in the set of potential numbers are output to an error file using the error data output means 11, and the data in the file is returned to the automatic layout system 2.

Next, each terminal Pi * obtained from the layout information and each terminal obtained from the connection description are obtained by the terminal proper name matching means 7.
Pj is compared, Pi * and terminal Pj having the same terminal unique name are selected, and the unique name (net name) of terminal Pj is given to terminal Pi *.

Next, in each set of terminals and rectangles classified by the potential number, it is determined by the proper name matching determination means 9 whether the same proper name is given to all the terminals included in the same set. .

If the same unique name is not given, each terminal and rectangle included in the set are output to an error file using the error data output means 11, and the data of the file is returned to the automatic layout system 2.

In addition, the terminal proper name classification means 8 classifies each terminal by proper name, and in each set of terminals classified by proper name, any two terminals included in the same set are included in the set having the same potential number. It is determined by the potential number coincidence determination means 10 whether or not it is satisfied.

If they are not included in the same potential number, then 2
The error data output means 11 outputs an error file for each terminal and rectangle included in each set of terminals and rectangles classified by the potential number including the terminal, and passes the data of the file to the automatic layout system 2. .

2 shows that when two rectangles 13 and 14 are given,
It is explanatory drawing which shows the connection determination of the two rectangles. Rectangle 13
The two rectangles are connected only when one of the lengths of the sides 15 and 16 of the rectangle 14 and the rectangle 14 is equal to or more than the design rule in the layout, and the rectangles 13 and 14 are located in the same layer.

FIG. 3 shows the connection between the terminals 17 and 18 when given two terminals 17 and 18, a rectangle 19, and a block B20.
FIG. 7 is an explanatory diagram showing a determination of connection between a terminal 18 and a rectangle 19.

The terminal 18 is included in the rectangle 19 (including the border of the side),
And it is connected only when it is located in the same layer. Also, the terminal
17 and the terminal 18 are included in the block B20 (including the boundary of the side), and the terminal 17 and the terminal 18 are connected only when they have the same terminal name.

The determinations shown in FIGS. 2 and 3 are executed by the terminal rectangle connection search means 4 and the connection classification determination means 6 shown in FIG.

FIG. 4 is a diagram when a block 21, a rectangle 22 to a rectangle 24 (particularly, the rectangle 24 is divided into a rectangle 24-1 and a rectangle 24-2 for convenience of description below) and a terminal 25 to a terminal 33 are given. It is explanatory drawing for showing the method of connection verification. Although it is shown limited to a part in the figure, the same applies to other parts.

Here, the rectangle 22 has potential number 1, the rectangle 23 has 2,
3 is assigned to the rectangle 24. Further, in this embodiment,
It is assumed that the terminal names from the terminals 25 to 33 do not overlap in the same block 21 (which affects the processing in step 6 below).

 The net information Pi for this example is as follows.

P1 = {terminal 25, terminal 26, terminal 27, terminal 33} P2 = {terminal 28, terminal 29, terminal 30} P3 = {terminal 31, terminal 32} The connection verification of the present invention is the following three determinations. .

(1) Obtain each set of terminals and rectangles classified by potential number and determine whether the terminals and rectangles included in each set are connected to the same potential. (Corresponding to the connection classification determination means 6) (2) In each set of terminals and rectangles classified by potential number, the same unique name is given to all the terminals included in the same set. judge. (Corresponding to proper name coincidence determination means 9) (3) It is determined that any two terminals given the same proper name are included in the set of the same potential number.
(Corresponding to the potential number determination means 10) When any one of the above (1) to (3) is not satisfied, the error data output means 11 is used to output the error data to the error file, and the data of the file is automatically Return to layout system 2.

A processing flow of the graphic connection verification method shown below will be described with reference to FIG. Here, the above (1) is from step 1 to step
Run on 11. The above (2) and (3) are performed in step 12.

<Summary of Processing Flow> Step 1 Initialize all net numbers of terminals included in graphic data to 0.

Step 2 By the adjacent figure search method, the rectangle r connected to each terminal p is examined, and the potential number nr of r is given to the potential number np of p.

In FIG. 4, since the potential number 1 is assigned to the rectangle 22, the potential number 1 is assigned to the terminals 25, 26, 27 and 33. Similarly, the terminals 28, 29, 30 connected to the rectangle 23 to which the potential number 2 is assigned are rectangles to which the potential number 2 and the potential number 3 are assigned.
Potential number 3 is assigned to terminals 31 and 32 connected to 24.

Stage 3 Terminals and rectangles are sorted by potential number N.

In FIG. 4, a set of potential number 1 = {terminal 25, terminal 26, terminal 27,
Terminal 33, rectangle 22}, set of potential number 2 = {terminal 28, terminal 29, terminal 30,
Rectangle 23}, set of potential number 3 = {terminal 31, terminal 32, rectangle 24-
1, rectangle 24-2}.

Step 4 The following steps 5 to 12 are performed for the terminal and rectangle set of each potential number N.

Step 5: Let V be the vertex set corresponding to each terminal and rectangle, and create a graph G = (V, E) without branches. An undirected branch is drawn between the terminals p and the rectangle r connected to p.

Step 6 An undirected branch is drawn between arbitrary terminals p1 and p2 that have the same terminal name and are included in the same block.

In the case of FIG. 4, since it is assumed that the same block has the same terminal name in the above, a new undirected branch cannot be drawn in the graph G.

If the terminal names of terminal 32 and terminal 33 are the same,
Since these terminals are on the same block, graph G
An undirected branch can be drawn between the terminals 33 of the terminal 32 at.

Step 7 Set the rectangles to Y at the bottom left point of each rectangle.
List sorted by coordinates RN = {rN1, rN2, ..., rN
m}.

Step 8 Take out the rectangle rNi from the beginning of the list RN,
Perform steps 9-10.

Step 9: On the list RN, the rectangle rN following rNi is taken out in order, and if the Y coordinate of the lower left point of rNj is smaller than the Y coordinate of the upper right point of rNi, step 10 is performed.

Step 10 If the overlapping part of rNi and rNj is equal to or more than the design rule, they are considered to be connected and an undirected branch is drawn between rNi and rNj.

In the case of FIG. 4, terminal 31, terminal 32, rectangle 24-1 and rectangle 24-2
For example, since the rectangle 24-1 and the rectangle 24-2 are in contact with each other, it can be assumed that there is an overlap, and an undirected branch can be drawn.

The same applies to the set of rectangles that form the rectangle 22 and the rectangle 23.

Step 11 The number of connected components in the graph G is checked, and if it is 2 or more, an open error message is output.

In the case of the example in FIG. 4, since there is one graph for each same potential number, there is no open error. If there is no overlap between the rectangle 24-1 and the rectangle 24-2, since an undirected branch is not drawn in the graph G, there are two connected components in the graph for potential number 3, and there is an open error. become.

Step 12 When the set of terminals included in the graph G is P *, Pi ⊆ P * -in the net information [potential number and proper name] P1, ..., Pn obtained by the connection information.
(1) Moreover, it is investigated that Pi⊇P *-(2) holds.

If (1) does not hold, an open error is output, and if (2) does not hold, a short error message is output.

Taking the net information P1 in the case of FIG. 4 as an example,
First, from graph G, P * = {terminal 25, terminal 26, terminal 27, terminal 3
Since 3}, P * = P1 and (1) and (2) are established, so there is no open or short error.

Similarly, with respect to P2 and P3, since (1) and (2) are established, there are no open and short errors.
Therefore, in this example, there is no error in the connection verification.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to efficiently verify the graphic connection of the output result of the automatic layout system such as the VLSI or the printed circuit board by utilizing the characteristics thereof.

[Brief description of drawings]

1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of connection determination of two rectangles, FIG. 3 is an explanatory diagram of connection of two terminals and determination of connection between a terminal and a rectangle, FIG. 4 is an explanatory diagram of the graphic connection verification. 1 …… Connection information input means 2 …… Automatic layout system 3 …… Rectangle and terminal input means 4 …… Terminal rectangle connection verification means 5 …… Potential number classification means 6 …… Connection classification judgment means 7 …… Terminal unique name match Means 8 …… Terminal unique name classification means 9 …… Terminal unique name match judging means 10 …… Potential number match judging means 11 …… Error data output means

Claims (1)

(57) [Claims] 1. A connection description in which a unique name (hereinafter referred to as a net name) is given to a set of a plurality of terminals connected to each other, a rectangular set having a layer and a potential number as attributes, and a layer and terminal unique name. Inputting layout pattern information consisting of a set of terminals having and as an attribute, the connection information obtained from the connection description and the connection information obtained from the layout pattern information are collated, and the validity of the layout pattern information is verified. A pattern connection verification system for verifying, wherein a rectangle connected to each terminal included in the layout pattern information is extracted and a potential number of the rectangle is given to each terminal, and the layout pattern information Means for classifying a plurality of terminals and a set of rectangles included in each of the potential numbers, and a group for each potential number. Means for determining that the terminals and the rectangles are connected to each other in each set of the formed terminals and the rectangles, and the connection description in which each terminal obtained from the layout information has the same terminal unique name Means for giving the net name of the terminal obtained by the above, and in each set consisting of the terminal and the rectangle classified by the potential number, that the same net name is given to all the terminals included in the same set A graphic connection verification system comprising: a determining means; and a means for determining that any two terminals to which the same proper name net name is added are included in a set of the same potential number.