JP2504242B2 - Signal processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal processing device, and in particular, it is possible to rewrite the contents of a memory storing a program into an idle time of processing, and to discretely process in time series. The present invention relates to a signal processing device suitable for so-called "digital signal processing" for processing quantized data.

[Conventional technology]

Conventionally, this type of signal processing device has a program memory,
An instruction decoder, a reset input, a program memory writing circuit, and a program input terminal are provided, and a sampling clock indicating the timing of quantization is input to the reset input. That is, the program starts to be executed from a predetermined address every cycle of the sampling clock. When rewriting a program in such a signal processing device, the processing time of the program to be executed within one sampling cycle is designed to be shorter than the sampling cycle. Then, the method of rewriting the contents of the program memory while the program within one sampling period is completed and the next period is started has been adopted. By doing so, from the outside, the same effect can be obtained as if the program memory was rewritten without interrupting the processing of the program. Such an effect is a function indispensable for a request to change the contents of a program without interrupting the sound especially during processing of a music signal.

Such processing is specifically executed as follows.
That is, a predetermined instruction is described in the logical final address of the program, the execution of the instruction is decoded by the instruction decoder, and then the program memory is rewritten by the memory rewriting circuit.

The rewritten program may be executed only for one sampling period. For example, when filtering a music signal, it may be desired to change only the characteristics of the filter. In this case, normally, only the filter coefficient needs to be changed, and in this type of signal processing apparatus, the filter coefficient is stored in a dedicated memory called a coefficient memory. In such a case, a program for changing the contents of the coefficient memory may be added to the program memory and the program may be executed for only one sampling period.

For this purpose, a conventional signal processing apparatus of this type has the following means. That is, the first program already stored (in this case, the logical final address must match the physically appropriate final address of this program, and that address must be the end of the program). Immediately after the predetermined instruction (herein, referred to as “termination instruction” is stored), a second program for rewriting the contents of the coefficient memory in which the coefficients of the filter are stored is written, and the logical program of the second program is written. Write the terminating command at the final address. The second program is not executed as it is because the first program is terminated by the termination instruction. In order to execute the second program, the program memory writing circuit is notified that the writing of the second program is completed. By doing this, the first
The terminating instruction of the program is invalidated for one sampling period, the second program is executed after the execution of the first program, and the execution of the program is stopped by the terminating instruction of the second program. In this way, the second program is executed and the filter coefficient is rewritten.

[Problems to be Solved by the Invention]

In the conventional signal processing apparatus of this type, when the execution time of the first and second programs exceeds the sampling period, the second program is not executed until the end, but there is no means for easily knowing it. The only way was to carefully estimate the execution time of the first program and calculate the allowed execution time of the second program so that the execution of the second program would be completed within that time. .
However, when the first program has a loop in which the number of executions changes due to external factors, it is almost impossible to accurately estimate the execution time of the first program. For this reason, the second program must be designed to be quite small in consideration of the margin, and within the limited sampling period,
It was difficult to get the maximum effect.

[Means for solving the problem]

According to the present invention, a first storage means for storing an instruction, a writing means for rewriting the contents of the first storage means from the outside, an input terminal, and a content thereof having a predetermined value when the input terminal is activated. Addressing means for designating the address of the first storage means to be set, decoding means for decoding a predetermined instruction read from the first storage means, and the contents of the first content by the output of the decoding means. When the state is set and the writing by the writing unit is completed, a second storage unit set to the second state and an output unit for outputting the content of the second storage unit to the outside are provided. Is characterized by.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diaphragm of a signal processing device according to an embodiment of the present invention. First, the operation of this embodiment will be described with reference to FIG.

The program memory 103 for storing the program and the input port 108 input the data to be written in the program memory 103 and the program address to be written from the data input terminal 111, and the program end input terminal 110 completes the program writing. When a write end signal is input, the program outputs a signal to the program memory 103, the address of the program to be written to the PC 105, and a signal that sets the content of the flag 109. Next, the program counter 105 for designating the address of the program memory 103, and the program memory 103 outputs the contents of the address designated by the PC 105 to the decoder 104, and the decoder 104 outputs from the program memory 103. Input data, decrypt, output decryption result to flag 109, flag output 102 is flag 10
The contents of 9 are output.

The PC 105 inputs the output of the reset signal input 107 and resets the contents of the PC 105 to 0 by the edge of the reset signal. Further, when the contents of the program memory for one address are decoded by the decoder 104, the PC 105 adds 1 to the contents of the PC 105.

Here, the signal input to the reset input 107 is a signal indicating a sampling cycle, and is a square wave having one cycle per sampling cycle, and the duty thereof is 50%.

The reset of the flag 109 is reset when the logically last instruction indicating the end of the program is executed in the program memory.

That is, the flag is reset if the program has been executed to the end, and the flag remains set if the program has not been executed.

Execution of the program is forcibly interrupted regardless of the contents of the program memory and the currently executed address, and the program is executed again from the address 0. Whether or not the program has been executed can be confirmed from the flag output 102.

A method of writing an instruction to the program memory, a detailed execution timing, and a block for executing the decoded content are not related to the description of the present invention, and thus the description thereof will be omitted.

FIG. 2 is a block diagram of a signal processing device according to another embodiment of the present invention. The program memory 103 for storing programs and the input port 208 are data input terminals 211.
The data to be written to the program memory 103, the program address to be written, and the number of addresses to be written are input, and a signal indicating that the writing of the program is completed is input.
To 3, the address of the program to write to the PC 105, and depending on the number of writes and the number of addresses to be written,
It is determined that the writing is completed, and a signal for setting the content of the flag 109 is output. Next, program memory
Program counter 105 that specifies the address of 103,
Further, the program memory 103 outputs the content of the address specified by the PC 105 to the decoder 104, the decoder 104 inputs the data output from the program memory 103, decodes it, and outputs the decoding result to the flag 109, Flag output 1
02 outputs the content of the flag 109.

The PC 105 inputs the output of the reset signal input 107 and resets the contents of the PC 105 to 0 by the edge of the reset signal. Further, when the contents of the program memory for one address are decoded by the decoder 104, the PC 105 adds 1 to the contents of the PC 105.

Here, the signal input to the reset input 107 is a signal indicating a sampling cycle, and is a square wave having one cycle per sampling cycle, and the duty thereof is 50%.

The reset of the flag 109 is reset when the logically last instruction indicating the end of the program is executed in the program memory.

That is, the flag is reset if the program has been executed to the end, and the flag remains set if the program has not been executed.

Execution of the program is forcibly interrupted regardless of the contents of the program memory and the currently executed address, and the program is executed again from the address 0. Whether or not the program has been executed can be confirmed from the flag output 102.

A method of writing an instruction to the program memory, a detailed execution timing, and a block for executing the decoded content are not related to the description of the present invention, and thus the description thereof will be omitted.

〔The invention's effect〕

As described above, the present invention can recognize whether or not the program counter has been executed to the end by having the means for resetting the flag when the program counter is reset for a certain period of time and may not be executed to the end.

As a result, there is an effect that it is not necessary to design the second program with a margin and to calculate it in a feasible range or to consider all external factors.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention,
FIG. 2 is a block diagram of another embodiment. 102 ... Flag output terminal, 103 ... Program memory,
104 …… decoder, 105 …… program counter, 107
...... Reset input, 108,208 …… Input port, 109 …… Flag, 110 …… Write end input terminal, 111,211 …… Data input terminal.

Claims (3)

(57) [Claims] 1. A first storage means for storing an instruction, a writing means for rewriting the contents of the first storage means from the outside, an input terminal, and a content having a predetermined value when the input terminal is activated. Addressing means for designating the address of the first storage means set to the first storage means, decoding means for decoding a predetermined instruction read from the first storage means, and the contents of the first content by the output of the decoding means. When the writing is completed by the writing means, the second storage means is set to the second state, and the output means for outputting the contents of the second storage means to the outside. A signal processing device characterized by that. 2. The signal processing device according to claim 1, wherein the instructions stored in the first storage means constitute a program, and the instructions decoded by the decoding means are logical programs of the program. A signal processing device characterized in that it is the last command. 3. The signal processing device according to claim 1, wherein the signal processing device according to claim 1 is activated by inputting to the input terminal a signal designating the start of execution of the program according to claim 2. A signal processing device characterized by that.