JP2501216B2 - Memory circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to speeding up a dual boat memory having a random boat and a serial boat.

[Prior Art] Conventionally, a dual port memory having a random port and a serial port transfers data for one row having memory cells to a data register once, and continuously reads the data register to speed up the serial port. Came.

[Problems to be Solved by the Invention] The conventional dual-port memory described above transfers data for one row having a memory cell array to the data register, so that data in the bit direction can be accessed at high speed, but serial access in the word direction is not possible. It has the drawback of not being able to speed up.

[Differences from the Prior Art of the Invention] In contrast to the conventional dual-port memory described above, the present invention is that the memory circuit operates in a time-division manner, so that the cycle time is significantly improved as compared with the conventional memory circuit. By utilizing the serial access to randomly access consecutive addresses by the address generation circuit, serial access in both the word direction and the bit direction can be executed at high speed.

[Means for Solving Problems] A memory circuit of the present invention includes a first register which takes in and outputs an address signal in synchronization with one inversion edge of a clock signal, and an address designated by supplied address information. And a memory cell array for reading and outputting stored data from the memory, and an address counter for fetching and outputting the output of the first register in response to a serial access start signal and updating the output in synchronization with the other inverted edge of the clock signal. A selector for selecting and outputting the first register for the first register and the address counter for second timing at a first timing within one cycle of the clock signal; and an address decoder for decoding the output of the selector. The inverted output of the decoded output from the address decoder is present in the clock signal. A second register which is taken in each time and is supplied to the memory cell array as the address information, and the memory cell array operates as the address counter while the address decoder is decoding the output signal of the first register. The storage data is output according to the signal obtained by decoding the output signal, and the memory cell array responds to the signal obtained by decoding the output of the first register while the address decoder is decoding the output signal of the address counter. It is characterized in that the stored data is output.

[Embodiment] First Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and shows only a portion related to the present invention. Register 1
Holds the address 111 at the timing of the control signal 304 output from the control circuit 3 based on the clock signal 211.
The address counter 2 outputs the output signal 101 of the register 1 at the timing of the control signal 303 synchronized with the fall of the clock signal 211 by the control signal 311 indicating the start of serial access.
Hold. The control circuit 3 inputs the clock signal 211 and the start of serial access, and the control signal 311 indicating whether the serial access is in the word direction or the bit direction, and inputs the control signals 301 and 30.
Outputs 2,303,304. The selector 4 switches between the output signal 101 of the register 1 and the output signal 201 of the address counter circuit 2 according to the control signal 301 and outputs it. The decoder 5 decodes the output signal 401 of the selector 4 and outputs the output signal 501. The register 6 holds the output signal 501 of the decoder 4 at the timing of the control signal 302. The memory cell array 7 selects one memory cell according to the output signal 601 of the register 6 and outputs data to the output signal 701. The sense amplifier 8 amplifies the output signal 701 of the memory cell array 7 and outputs the output signal 801. The register 9 holds the output signal 801 of the sense amplifier 8 at the timing of the control signal 302. The multiplexer 10 registers the register 9 at the timing of the control signal 301.
Output signal 901 of random port 1001 and serial port 1
Switch to 002 and output.

Next, the operation will be described with reference to FIG. FIG. 2 shows a timing chart of the first embodiment. Address A1, A
2, A3 are held in the register at the rising timing of the clock signal 211. When the cycle of the clock signal 211 is T, the data D (A1), D (A for the addresses A1, A2, A3
2), D (A3) is 1.5T after the addresses A1, A2, A3 are held
It will be output to the random port later. When the control signal 311 designates to start serial access in the bit direction from the address A1, the address A1 is held in the address counter circuit 2 and D (A1) is output to the serial port 1.5T after being held. Thereafter, the address counter circuit 2 increments the address A1 by +1 every cycle T and outputs it to the selector 4. Therefore, D (A1), D (A1 +
1) and D (A1 + 2) are sequentially output. When serial access in the word direction is designated, the address counter circuit 2 increments the address by the word.

As described above, in the present embodiment, since serial access is performed by the address generation by the address counter circuit, it is possible to access at the same speed in both the bit direction and the word direction.

Second Embodiment FIG. 3 is a block diagram showing a second embodiment of the present invention. The registers 11 and 12 are output signals 1001 of the multiplexer 10.
1002 is the rising timing of the control signal 302,
Hold at the fall timing. In this embodiment, both the random port and the serial port have the clock signal 211 of 1
There is an advantage that data for a period is retained.

[Effects of the Invention] As described above, the present invention utilizes the fact that the cycle time of the conventional memory circuit is significantly improved by operating the memory circuit in a time-division manner, and the serial access is performed by the address counter circuit. By doing so, it is possible to speed up serial access not only in the bit direction but also in the word direction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a timing chart diagram of the first embodiment, and FIG. 3 is a block diagram showing a second embodiment of the present invention. 1,6,9,11,12 ... Register, 2 ... Address counter circuit, 3 ... Control circuit, 4 ... Selector, 5 ... Decoder, 7 ... Memory cell array, 8 ... Sense amplifier, 10 ... … Multiplexer, 111 …… Address input line, 201 …… Address counter circuit 2 output line, 301,302,303,304,305 …… Control circuit 3 output line, 401 …… Selector 4 output line, 501 …… Decoder output line, 101,601,901,1101,1201, ...... Register output line, 701 …… Memory cell array output line, 801 …… Sense amplifier output line, 211 …… Clock input line, 311 …… Control signal input line, 1001,1002 …… Multiplexer output line.

Claims (1)

(57) [Claims] 1. A first register for receiving and outputting an address signal in synchronization with one inversion edge of a clock signal,
A memory cell array that reads out and outputs stored data from an address specified by the supplied address information, and captures and outputs the output of the first register in response to a serial access start signal, and outputs the output to the other inversion edge of the clock signal. An address counter that updates its output in synchronization; a selector that selects and outputs the first register at the first timing and the address counter at the second timing within one cycle of the clock signal; An address decoder that decodes the output of the selector, and a decode output from the address decoder that is fetched each time an inverted edge appears in the clock signal and supplied to the memory cell array as the address information.
Register of the address decoder, the address decoder
While the output signal of the register is being decoded, the memory cell array outputs stored data according to the signal obtained by decoding the output signal of the address counter, and the address decoder decodes the output signal of the address counter. The storage circuit, wherein the memory cell array outputs storage data in response to a signal obtained by decoding the output of the first register during a certain period.