JP2025506818A - 接合構造 - Google Patents

接合構造 Download PDF

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Publication number
JP2025506818A
JP2025506818A JP2024550200A JP2024550200A JP2025506818A JP 2025506818 A JP2025506818 A JP 2025506818A JP 2024550200 A JP2024550200 A JP 2024550200A JP 2024550200 A JP2024550200 A JP 2024550200A JP 2025506818 A JP2025506818 A JP 2025506818A
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JP
Japan
Prior art keywords
conductive
less
contact
singulated
conductive contact
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Pending
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JP2024550200A
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English (en)
Japanese (ja)
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JP2025506818A5 (cg-RX-API-DMAC10.html
Inventor
シプリアン エメカ ウゾー
ラジェッシュ カトカール
トーマス ワークマン
ガイウス ギルマン ジュニア ファウンテン
ギリアン ガオ
ジェレミー アルフレッド タイル
ガブリエル ゼット ゲバラ
キョン－モ バン
ローラ ウィルズ ミルカリミ
Original Assignee
アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド
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Publication of JP2025506818A publication Critical patent/JP2025506818A/ja
Publication of JP2025506818A5 publication Critical patent/JP2025506818A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/794—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
JP2024550200A 2022-02-24 2023-02-23 接合構造 Pending JP2025506818A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202263313639P 2022-02-24 2022-02-24
US63/313,639 2022-02-24
PCT/US2023/063147 WO2023164564A1 (en) 2022-02-24 2023-02-23 Bonded structures

Publications (2)

Publication Number Publication Date
JP2025506818A true JP2025506818A (ja) 2025-03-13
JP2025506818A5 JP2025506818A5 (cg-RX-API-DMAC10.html) 2026-03-04

Family

ID=87574555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024550200A Pending JP2025506818A (ja) 2022-02-24 2023-02-23 接合構造

Country Status (6)

Country Link
EP (1) EP4483406A4 (cg-RX-API-DMAC10.html)
JP (1) JP2025506818A (cg-RX-API-DMAC10.html)
KR (1) KR20240156613A (cg-RX-API-DMAC10.html)
CN (1) CN119013777A (cg-RX-API-DMAC10.html)
TW (1) TW202343714A (cg-RX-API-DMAC10.html)
WO (1) WO2023164564A1 (cg-RX-API-DMAC10.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230299123A1 (en) * 2022-03-18 2023-09-21 Intel Corporation Inductors for hybrid bonding interconnect architectures

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552425B1 (en) * 1998-12-18 2003-04-22 Intel Corporation Integrated circuit package
US20140038357A1 (en) * 2012-08-06 2014-02-06 Apple Inc. Singulated ic stiffener and de-bond process
US10510603B2 (en) * 2017-08-31 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive vias in semiconductor packages and methods of forming same
US10727219B2 (en) * 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
CN111916354B (zh) * 2019-05-07 2022-08-30 欣兴电子股份有限公司 线路载板及其制作方法
MY202540A (en) * 2019-06-11 2024-05-06 Intel Corp Multi-faceted integrated-circuit dice and packages
DE102020114141B4 (de) * 2019-10-18 2024-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integriertes schaltungspackage und verfahren
US11264362B2 (en) * 2020-05-28 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of fabricating the same
US11631647B2 (en) * 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230299123A1 (en) * 2022-03-18 2023-09-21 Intel Corporation Inductors for hybrid bonding interconnect architectures
US12652810B2 (en) * 2022-03-18 2026-06-09 Intel Corporation Inductors for hybrid bonding interconnect architectures

Also Published As

Publication number Publication date
TW202343714A (zh) 2023-11-01
EP4483406A4 (en) 2026-03-04
KR20240156613A (ko) 2024-10-30
US20230268300A1 (en) 2023-08-24
WO2023164564A1 (en) 2023-08-31
CN119013777A (zh) 2024-11-22
EP4483406A1 (en) 2025-01-01

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