JP2025504029A - 集積回路間のアドレス改変を実施するための方法及び装置 - Google Patents

集積回路間のアドレス改変を実施するための方法及び装置 Download PDF

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Publication number
JP2025504029A
JP2025504029A JP2024544935A JP2024544935A JP2025504029A JP 2025504029 A JP2025504029 A JP 2025504029A JP 2024544935 A JP2024544935 A JP 2024544935A JP 2024544935 A JP2024544935 A JP 2024544935A JP 2025504029 A JP2025504029 A JP 2025504029A
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address
value
target device
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JP2024544935A
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Japanese (ja)
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JP2025504029A5 (https=
Inventor
ウェイン ウォーターズ デリック
ブルース ジャン シャオシー
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テキサス インスツルメンツ インコーポレイテッド
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Publication of JP2025504029A publication Critical patent/JP2025504029A/ja
Publication of JP2025504029A5 publication Critical patent/JP2025504029A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
JP2024544935A 2022-01-28 2023-01-27 集積回路間のアドレス改変を実施するための方法及び装置 Pending JP2025504029A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/587,695 2022-01-28
US17/587,695 US12124393B2 (en) 2022-01-28 2022-01-28 Methods and apparatus to preform inter-integrated circuit address modification
PCT/US2023/011674 WO2023146998A1 (en) 2022-01-28 2023-01-27 Methods and apparatus to preform inter-integrated circuit address modification

Publications (2)

Publication Number Publication Date
JP2025504029A true JP2025504029A (ja) 2025-02-06
JP2025504029A5 JP2025504029A5 (https=) 2026-02-04

Family

ID=85380972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024544935A Pending JP2025504029A (ja) 2022-01-28 2023-01-27 集積回路間のアドレス改変を実施するための方法及び装置

Country Status (5)

Country Link
US (2) US12124393B2 (https=)
EP (1) EP4469904A1 (https=)
JP (1) JP2025504029A (https=)
CN (1) CN118613790A (https=)
WO (1) WO2023146998A1 (https=)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7653757B1 (en) * 2004-08-06 2010-01-26 Zilker Labs, Inc. Method for using a multi-master multi-slave bus for power management
US7533191B2 (en) * 2006-06-30 2009-05-12 Intel Corporation Methods and arrangements for devices to share a common address on a bus
US7702881B2 (en) * 2007-01-31 2010-04-20 Freescale Semiconductor, Inc. Method and system for data transfers across different address spaces
US8046527B2 (en) * 2007-02-22 2011-10-25 Mosaid Technologies Incorporated Apparatus and method for using a page buffer of a memory device as a temporary cache
US8255497B2 (en) * 2008-11-03 2012-08-28 Lincoln Global, Inc. Method of discovery and communication with industrial equipment
US8225021B2 (en) 2009-05-28 2012-07-17 Lexmark International, Inc. Dynamic address change for slave devices on a shared bus
US9021194B2 (en) * 2011-08-19 2015-04-28 Freescale Semiconductor, Inc. Memory management unit tag memory
EP2725499A1 (en) 2012-10-25 2014-04-30 Telefónica, S.A. Method for assigning dynamically an identifier to a slave device in I2C data bus
US9465761B2 (en) * 2013-07-19 2016-10-11 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Managing slave devices
US20170083468A1 (en) * 2015-09-21 2017-03-23 Qualcomm Incorporated Identifying multiple identical devices on a shared bus
US20190108149A1 (en) * 2017-10-10 2019-04-11 Qualcomm Incorporated I3c in-band interrupts directed to multiple execution environments
US11669784B2 (en) * 2019-12-11 2023-06-06 Google Llc Content provider recommendations to improve targetting and other settings

Also Published As

Publication number Publication date
CN118613790A (zh) 2024-09-06
US20230244624A1 (en) 2023-08-03
WO2023146998A1 (en) 2023-08-03
EP4469904A1 (en) 2024-12-04
US20250021508A1 (en) 2025-01-16
US12124393B2 (en) 2024-10-22

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